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evan.liu 2026-08-31 21:07:17 +08:00
commit f5bf66b8bb
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9
EventRecorderStub.scvd Normal file
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<?xml version="1.0" encoding="utf-8"?>
<component_viewer schemaVersion="0.1" xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
<component name="EventRecorderStub" version="1.0.0"/> <!--name and version of the component-->
<events>
</events>
</component_viewer>

885
Nu_Link_Driver.ini Normal file
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[Version]
Nu_LinkVersion=V5.9
[Process]
ProcessID=0x00000000
ProcessCreationTime_L=0x00000000
ProcessCreationTime_H=0x00000000
NuLinkID=0x00000000
[ChipSelect]
;ChipName=<NUC1xx|NUC2xx|M05x|N571|N572|Nano100|N512|Mini51|NUC505|General>
ChipName=NUC1xx
[NUC505]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=0
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x4000
ProgramAlgorithm=NUC505_SPIFLASH.FLM
[NUC4xx]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x4000
ProgramAlgorithm=NUC400_AP_512.FLM
TraceConf0=0x00000002
TraceConf1=0x014fb180
TraceConf2=0x00000800
TraceConf3=0x00000000
TraceConf4=0x00000001
TraceConf5=0x00000000
[NUC2xx]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x1000
ProgramAlgorithm=NUC200_AP_128.FLM
[NUC1311]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x1000
ProgramAlgorithm=NUC1311_AP_64.FLM
[NUC126]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x2000
ProgramAlgorithm=NUC126_AP_256.FLM
[NUC121]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x1000
ProgramAlgorithm=NUC121_AP_32.FLM
[NUC1xx]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x1000
ProgramAlgorithm=NUC100_AP_128.FLM
[NUC029]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x800
ProgramAlgorithm=NUC029_AP_16.FLM
[NM1820]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x800
ProgramAlgorithm=NM1820_AP_17_5.FLM
[NM1810]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x800
ProgramAlgorithm=NM1810_AP_29_5.FLM
[NM1500]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x1000
ProgramAlgorithm=NM1500_AP_128.FLM
[NM1330]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x1000
ProgramAlgorithm=NM1330_AP_64.FLM
[NM1320]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x1000
ProgramAlgorithm=NM1320_AP_32.FLM
[NM1230]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x1000
ProgramAlgorithm=NM1230_AP_64.FLM
[NM1200]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x800
ProgramAlgorithm=NM1200_AP_8.FLM
[NM1120]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x800
ProgramAlgorithm=NM1120_AP_29_5.FLM
[TF5100]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x1000
ProgramAlgorithm=TF5100_AP_64.FLM
[NDA102]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x800
ProgramAlgorithm=NDA102_AP_29_5.FLM
[Nano103]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x1000
ProgramAlgorithm=Nano103_AP_64.FLM
[Nano100]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x1000
ProgramAlgorithm=Nano100_AP_64.FLM
[N576]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=0
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x1000
ProgramAlgorithm=N576_AP_145.FLM
[N575]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=0
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x1000
ProgramAlgorithm=N575_AP_145.FLM
[N572]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x2000
ProgramAlgorithm=N572Fxxx.FLM
[N571]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x2000
ProgramAlgorithm=N571E000.FLM
[N570]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=0
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x1000
ProgramAlgorithm=N570_AP_64.FLM
[N569]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=0
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x1000
ProgramAlgorithm=N569_AP_64.FLM
[N512]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x1000
ProgramAlgorithm=N512_AP_64.FLM
[Mini57]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x800
ProgramAlgorithm=Mini57_AP_29_5.FLM
[Mini51]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x800
ProgramAlgorithm=Mini51_AP_16.FLM
[M481]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x4000
ProgramAlgorithm=M481_AP_512.FLM
TraceConf0=0x00000002
TraceConf1=0x00b71b00
TraceConf2=0x00000800
TraceConf3=0x00000000
TraceConf4=0x00000001
TraceConf5=0x00000000
[M480LD]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x4000
ProgramAlgorithm=M480LD_AP_256.FLM
[M479]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x4000
ProgramAlgorithm=M479_AP_256.FLM
[M451]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x4000
ProgramAlgorithm=M451_AP_256.FLM
[M251]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x2000
ProgramAlgorithm=M251_AP_192.FLM
[M2351]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=1
EnableFlashBreakpoint=0
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x4000
ProgramAlgorithm=M2351_AP_512.FLM
TraceConf0=0x00000002
TraceConf1=0x00b71b00
TraceConf2=0x00000800
TraceConf3=0x00000000
TraceConf4=0x00000001
TraceConf5=0x00000000
[M261]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=1
EnableFlashBreakpoint=0
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x4000
ProgramAlgorithm=M261_AP_512.FLM
TraceConf0=0x00000002
TraceConf1=0x00b71b00
TraceConf2=0x00000800
TraceConf3=0x00000000
TraceConf4=0x00000001
TraceConf5=0x00000000
[MR63]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=1
EnableFlashBreakpoint=0
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x4000
ProgramAlgorithm=MR63_AP_512.FLM
TraceConf0=0x00000002
TraceConf1=0x00b71b00
TraceConf2=0x00000800
TraceConf3=0x00000000
TraceConf4=0x00000001
TraceConf5=0x00000000
[M0564]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x2000
ProgramAlgorithm=M0564_AP_256.FLM
[M0519]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x1000
ProgramAlgorithm=M0519_AP_128.FLM
[M0518]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x1000
ProgramAlgorithm=M0518_AP_64.FLM
[M05x]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x800
ProgramAlgorithm=M0516_AP_64.FLM
[M031]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=1
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x800
ProgramAlgorithm=M031_AP_128.FLM
[NPCX]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=0
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x4000
ProgramAlgorithm=NPCX_AP_512.FLM
[I94000]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=0
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x4000
ProgramAlgorithm=I94000_AP_512.FLM
[ISD9300]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=0
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x1000
ProgramAlgorithm=ISD9300_AP_145.FLM
[I9200]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=0
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x1000
ProgramAlgorithm=I9200_AP_128.FLM
[ISD9xxx]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=0
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x1000
ProgramAlgorithm=ISD9100_AP_145.FLM
[ISD9000]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=0
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x1000
ProgramAlgorithm=ISD9000_AP_64.FLM
[AU9xxx]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
FlashSelect=APROM
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableFlashBreakpoint=0
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x1000
ProgramAlgorithm=AU9100_AP_145.FLM
[General]
Connect=0
Reset=Autodetect
MaxClock=1MHz
MemoryVerify=0
IOVoltage=3300
Erase=1
Program=1
Verify=1
ResetAndRun=0
EnableLog=0
MemAccessWhileRun=0
RAMForAlgorithmStart=0x20000000
RAMForAlgorithmSize=0x4000
ProgramAlgorithm=

2
Objects/ExtDll.iex Normal file
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[EXTDLL]
Count=0

16
Objects/test.sct Normal file
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; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x08000000 0x00007600 { ; load region size_region
ER_IROM1 0x08000000 0x00007600 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
.ANY (+XO)
}
RW_IRAM1 0x20000000 0x00000C00 { ; RW data
.ANY (+RW +ZI)
}
}

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docs/N32G003F5S7-STB_V1.0/CN_UG_N32G003F5S7_STB_Development_Board_Hardware_User_Guide_V1.0.pdf Normal file
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firmware/CMSIS/core/cmsis_armcc.h Normal file
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/**************************************************************************//**
* @file cmsis_armcc.h
* @brief CMSIS Cortex-M Core Function/Instruction Header File
* @version V4.30
* @date 20. October 2015
******************************************************************************/
/* Copyright (c) 2009 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CMSIS_ARMCC_H
#define __CMSIS_ARMCC_H
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
/* intrinsic void __enable_irq(); */
/* intrinsic void __disable_irq(); */
/**
\brief Get Control Register
\details Returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/**
\brief Set Control Register
\details Writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/**
\brief Get IPSR Register
\details Returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/**
\brief Get APSR Register
\details Returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/**
\brief Get xPSR Register
\details Returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/**
\brief Get Process Stack Pointer
\details Returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/**
\brief Set Process Stack Pointer
\details Assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/**
\brief Get Main Stack Pointer
\details Returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/**
\brief Set Main Stack Pointer
\details Assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/**
\brief Get Priority Mask
\details Returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/**
\brief Set Priority Mask
\details Assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
/**
\brief Enable FIQ
\details Enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/**
\brief Disable FIQ
\details Disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/**
\brief Get Base Priority
\details Returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/**
\brief Set Base Priority
\details Assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xFFU);
}
/**
\brief Set Base Priority with condition
\details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
or the new value increases the BASEPRI priority level.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
{
register uint32_t __regBasePriMax __ASM("basepri_max");
__regBasePriMax = (basePri & 0xFFU);
}
/**
\brief Get Fault Mask
\details Returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/**
\brief Set Fault Mask
\details Assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1);
}
#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U)
/**
\brief Get FPSCR
\details Returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0U);
#endif
}
/**
\brief Set FPSCR
\details Assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U)
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#endif
}
#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */
/*@} end of CMSIS_Core_RegAccFunctions */
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
/**
\brief No Operation
\details No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/**
\brief Wait For Interrupt
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
*/
#define __WFI __wfi
/**
\brief Wait For Event
\details Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/**
\brief Send Event
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/**
\brief Instruction Synchronization Barrier
\details Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or memory,
after the instruction has been completed.
*/
#define __ISB() do {\
__schedule_barrier();\
__isb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Synchronization Barrier
\details Acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() do {\
__schedule_barrier();\
__dsb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Data Memory Barrier
\details Ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() do {\
__schedule_barrier();\
__dmb(0xF);\
__schedule_barrier();\
} while (0U)
/**
\brief Reverse byte order (32 bit)
\details Reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/**
\brief Reverse byte order (16 bit)
\details Reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
#endif
/**
\brief Reverse byte order in signed short value
\details Reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
{
revsh r0, r0
bx lr
}
#endif
/**
\brief Rotate Right in unsigned value (32 bit)
\details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
/**
\brief Breakpoint
\details Causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
/**
\brief Reverse bit order of value
\details Reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
#define __RBIT __rbit
#else
__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */
result = value; /* r will be reversed bits of v; first get LSB of v */
for (value >>= 1U; value; value >>= 1U)
{
result <<= 1U;
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
return(result);
}
#endif
/**
\brief Count leading zeros
\details Counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U)
/**
\brief LDR Exclusive (8 bit)
\details Executes a exclusive LDR instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
#else
#define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (16 bit)
\details Executes a exclusive LDR instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
#else
#define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief LDR Exclusive (32 bit)
\details Executes a exclusive LDR instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
#else
#define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop")
#endif
/**
\brief STR Exclusive (8 bit)
\details Executes a exclusive STR instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXB(value, ptr) __strex(value, ptr)
#else
#define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (16 bit)
\details Executes a exclusive STR instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXH(value, ptr) __strex(value, ptr)
#else
#define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief STR Exclusive (32 bit)
\details Executes a exclusive STR instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020)
#define __STREXW(value, ptr) __strex(value, ptr)
#else
#define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop")
#endif
/**
\brief Remove the exclusive lock
\details Removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/**
\brief Signed Saturate
\details Saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/**
\brief Unsigned Saturate
\details Saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/**
\brief Rotate Right with Extend (32 bit)
\details Moves each bit of a bitstring right by one bit.
The carry input is shifted in at the left end of the bitstring.
\param [in] value Value to rotate
\return Rotated value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value)
{
rrx r0, r0
bx lr
}
#endif
/**
\brief LDRT Unprivileged (8 bit)
\details Executes a Unprivileged LDRT instruction for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr))
/**
\brief LDRT Unprivileged (16 bit)
\details Executes a Unprivileged LDRT instruction for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr))
/**
\brief LDRT Unprivileged (32 bit)
\details Executes a Unprivileged LDRT instruction for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr))
/**
\brief STRT Unprivileged (8 bit)
\details Executes a Unprivileged STRT instruction for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRBT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (16 bit)
\details Executes a Unprivileged STRT instruction for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRHT(value, ptr) __strt(value, ptr)
/**
\brief STRT Unprivileged (32 bit)
\details Executes a Unprivileged STRT instruction for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
*/
#define __STRT(value, ptr) __strt(value, ptr)
#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
/* ################### Compiler specific Intrinsics ########################### */
/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
Access to dedicated SIMD instructions
@{
*/
#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */
#define __SADD8 __sadd8
#define __QADD8 __qadd8
#define __SHADD8 __shadd8
#define __UADD8 __uadd8
#define __UQADD8 __uqadd8
#define __UHADD8 __uhadd8
#define __SSUB8 __ssub8
#define __QSUB8 __qsub8
#define __SHSUB8 __shsub8
#define __USUB8 __usub8
#define __UQSUB8 __uqsub8
#define __UHSUB8 __uhsub8
#define __SADD16 __sadd16
#define __QADD16 __qadd16
#define __SHADD16 __shadd16
#define __UADD16 __uadd16
#define __UQADD16 __uqadd16
#define __UHADD16 __uhadd16
#define __SSUB16 __ssub16
#define __QSUB16 __qsub16
#define __SHSUB16 __shsub16
#define __USUB16 __usub16
#define __UQSUB16 __uqsub16
#define __UHSUB16 __uhsub16
#define __SASX __sasx
#define __QASX __qasx
#define __SHASX __shasx
#define __UASX __uasx
#define __UQASX __uqasx
#define __UHASX __uhasx
#define __SSAX __ssax
#define __QSAX __qsax
#define __SHSAX __shsax
#define __USAX __usax
#define __UQSAX __uqsax
#define __UHSAX __uhsax
#define __USAD8 __usad8
#define __USADA8 __usada8
#define __SSAT16 __ssat16
#define __USAT16 __usat16
#define __UXTB16 __uxtb16
#define __UXTAB16 __uxtab16
#define __SXTB16 __sxtb16
#define __SXTAB16 __sxtab16
#define __SMUAD __smuad
#define __SMUADX __smuadx
#define __SMLAD __smlad
#define __SMLADX __smladx
#define __SMLALD __smlald
#define __SMLALDX __smlaldx
#define __SMUSD __smusd
#define __SMUSDX __smusdx
#define __SMLSD __smlsd
#define __SMLSDX __smlsdx
#define __SMLSLD __smlsld
#define __SMLSLDX __smlsldx
#define __SEL __sel
#define __QADD __qadd
#define __QSUB __qsub
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
((int64_t)(ARG3) << 32U) ) >> 32U))
#endif /* (__CORTEX_M >= 0x04) */
/*@} end of group CMSIS_SIMD_intrinsics */
#endif /* __CMSIS_ARMCC_H */

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@ -0,0 +1,665 @@
/**************************************************************************//**
* @file core_cm0.h
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
* @version V2.10
* @date 19. July 2011
*
* @note
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#if defined ( __ICCARM__ )
#pragma system_include /* treat file as system include file for MISRA check */
#endif
#ifdef __cplusplus
extern "C" {
#endif
#ifndef __CORE_CM0_H_GENERIC
#define __CORE_CM0_H_GENERIC
/** \mainpage CMSIS Cortex-M0
This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.
It consists of:
- Cortex-M Core Register Definitions
- Cortex-M functions
- Cortex-M instructions
The CMSIS Cortex-M0 Core Peripheral Access Layer contains C and assembly functions that ease
access to the Cortex-M Core
*/
/** \defgroup CMSIS_MISRA_Exceptions CMSIS MISRA-C:2004 Compliance Exceptions
CMSIS violates following MISRA-C2004 Rules:
- Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.<br>
Function definitions in header files are used to allow 'inlining'.
- Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
Unions are used for effective representation of core registers.
- Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.<br>
Function-like macros are used to allow more efficient code.
*/
/*******************************************************************************
* CMSIS definitions
******************************************************************************/
/** \defgroup CMSIS_core_definitions CMSIS Core Definitions
This file defines all structures and symbols for CMSIS core:
- CMSIS version number
- Cortex-M core
- Cortex-M core Revision Number
@{
*/
/* CMSIS CM0 definitions */
#define __CM0_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */
#define __CM0_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
#define __CORTEX_M (0x00) /*!< Cortex core */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#endif
/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */
#define __FPU_USED 0
#if defined ( __CC_ARM )
#if defined __TARGET_FPU_VFP
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __ICCARM__ )
#if defined __ARMVFP__
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __GNUC__ )
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
#warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
#endif
#elif defined ( __TASKING__ )
/* add preprocessor checks */
#endif
#include <stdint.h> /*!< standard types definitions */
#include "core_cmInstr.h" /*!< Core Instruction Access */
#include "core_cmFunc.h" /*!< Core Function Access */
#endif /* __CORE_CM0_H_GENERIC */
#ifndef __CMSIS_GENERIC
#ifndef __CORE_CM0_H_DEPENDANT
#define __CORE_CM0_H_DEPENDANT
/* check device defines and use defaults */
#if defined __CHECK_DEVICE_DEFINES
#ifndef __CM0_REV
#define __CM0_REV 0x0000
#warning "__CM0_REV not defined in device header file; using default!"
#endif
#ifndef __NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS 2
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
#endif
#ifndef __Vendor_SysTickConfig
#define __Vendor_SysTickConfig 0
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
#endif
#endif
/* IO definitions (access restrictions to peripheral registers) */
#ifdef __cplusplus
#define __I volatile /*!< defines 'read only' permissions */
#else
#define __I volatile const /*!< defines 'read only' permissions */
#endif
#define __O volatile /*!< defines 'write only' permissions */
#define __IO volatile /*!< defines 'read / write' permissions */
/*@} end of group CMSIS_core_definitions */
/*******************************************************************************
* Register Abstraction
******************************************************************************/
/** \defgroup CMSIS_core_register CMSIS Core Register
Core Register contain:
- Core Register
- Core NVIC Register
- Core SCB Register
- Core SysTick Register
*/
/** \ingroup CMSIS_core_register
\defgroup CMSIS_CORE CMSIS Core
Type definitions for the Cortex-M Core Registers
@{
*/
/** \brief Union type to access the Application Program Status Register (APSR).
*/
typedef union
{
struct
{
#if (__CORTEX_M != 0x04)
uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
#else
uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
#endif
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} APSR_Type;
/** \brief Union type to access the Interrupt Program Status Register (IPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} IPSR_Type;
/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
*/
typedef union
{
struct
{
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
#if (__CORTEX_M != 0x04)
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
#else
uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
#endif
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} xPSR_Type;
/** \brief Union type to access the Control Registers (CONTROL).
*/
typedef union
{
struct
{
uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
} b; /*!< Structure used for bit access */
uint32_t w; /*!< Type used for word access */
} CONTROL_Type;
/*@} end of group CMSIS_CORE */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_NVIC CMSIS NVIC
Type definitions for the Cortex-M NVIC Registers
@{
*/
/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
*/
typedef struct
{
__IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
uint32_t RESERVED0[31];
__IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
uint32_t RSERVED1[31];
__IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
uint32_t RESERVED2[31];
__IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
uint32_t RESERVED3[31];
uint32_t RESERVED4[64];
__IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
} NVIC_Type;
/*@} end of group CMSIS_NVIC */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_SCB CMSIS SCB
Type definitions for the Cortex-M System Control Block Registers
@{
*/
/** \brief Structure type to access the System Control Block (SCB).
*/
typedef struct
{
__I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
uint32_t RESERVED0;
__IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
__IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
__IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
uint32_t RESERVED1;
__IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
__IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
} SCB_Type;
/* SCB CPUID Register Definitions */
#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
/* SCB Interrupt Control State Register Definitions */
#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
/* SCB Application Interrupt and Reset Control Register Definitions */
#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
/* SCB System Control Register Definitions */
#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
/* SCB Configuration Control Register Definitions */
#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
/* SCB System Handler Control and State Register Definitions */
#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
/*@} end of group CMSIS_SCB */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_SysTick CMSIS SysTick
Type definitions for the Cortex-M System Timer Registers
@{
*/
/** \brief Structure type to access the System Timer (SysTick).
*/
typedef struct
{
__IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
__IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
__IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
__I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
} SysTick_Type;
/* SysTick Control / Status Register Definitions */
#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
/* SysTick Reload Register Definitions */
#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
/* SysTick Current Register Definitions */
#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
/* SysTick Calibration Register Definitions */
#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
/*@} end of group CMSIS_SysTick */
/** \ingroup CMSIS_core_register
\defgroup CMSIS_CoreDebug CMSIS Core Debug
Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP
and not via processor. Therefore they are not covered by the Cortex-M0 header file.
@{
*/
/*@} end of group CMSIS_CoreDebug */
/** \ingroup CMSIS_core_register
@{
*/
/* Memory mapping of Cortex-M0 Hardware */
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
/*@} */
/*******************************************************************************
* Hardware Abstraction Layer
******************************************************************************/
/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface
Core Function Interface contains:
- Core NVIC Functions
- Core SysTick Functions
- Core Register Access Functions
*/
/* ########################## NVIC functions #################################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions
@{
*/
/* Interrupt Priorities are WORD accessible only under ARMv6M */
/* The following MACROS handle generation of the register offset and byte masks */
#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
/** \brief Enable External Interrupt
This function enables a device specific interrupt in the NVIC interrupt controller.
The interrupt number cannot be a negative value.
\param [in] IRQn Number of the external interrupt to enable
*/
static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Disable External Interrupt
This function disables a device specific interrupt in the NVIC interrupt controller.
The interrupt number cannot be a negative value.
\param [in] IRQn Number of the external interrupt to disable
*/
static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Get Pending Interrupt
This function reads the pending register in the NVIC and returns the pending bit
for the specified interrupt.
\param [in] IRQn Number of the interrupt for get pending
\return 0 Interrupt status is not pending
\return 1 Interrupt status is pending
*/
static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
}
/** \brief Set Pending Interrupt
This function sets the pending bit for the specified interrupt.
The interrupt number cannot be a negative value.
\param [in] IRQn Number of the interrupt for set pending
*/
static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/** \brief Clear Pending Interrupt
This function clears the pending bit for the specified interrupt.
The interrupt number cannot be a negative value.
\param [in] IRQn Number of the interrupt for clear pending
*/
static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
}
/** \brief Set Interrupt Priority
This function sets the priority for the specified interrupt. The interrupt
number can be positive to specify an external (device specific)
interrupt, or negative to specify an internal (core) interrupt.
Note: The priority cannot be set for every core interrupt.
\param [in] IRQn Number of the interrupt for set priority
\param [in] priority Priority to set
*/
static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
if(IRQn < 0) {
SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
else {
NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
(((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
}
/** \brief Get Interrupt Priority
This function reads the priority for the specified interrupt. The interrupt
number can be positive to specify an external (device specific)
interrupt, or negative to specify an internal (core) interrupt.
The returned priority value is automatically aligned to the implemented
priority bits of the microcontroller.
\param [in] IRQn Number of the interrupt for get priority
\return Interrupt Priority
*/
static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if(IRQn < 0) {
return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
else {
return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
}
/** \brief System Reset
This function initiate a system reset request to reset the MCU.
*/
static __INLINE void NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
while(1); /* wait until reset */
}
/*@} end of CMSIS_Core_NVICFunctions */
/* ################################## SysTick function ############################################ */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions
@{
*/
#if (__Vendor_SysTickConfig == 0)
/** \brief System Tick Configuration
This function initialises the system tick timer and its interrupt and start the system tick timer.
Counter is in free running mode to generate periodical interrupts.
\param [in] ticks Number of ticks between two interrupts
\return 0 Function succeeded
\return 1 Function failed
*/
static __INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */
NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */
SysTick->VAL = 0; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0); /* Function successful */
}
#endif
/*@} end of CMSIS_Core_SysTickFunctions */
#endif /* __CORE_CM0_H_DEPENDANT */
#endif /* __CMSIS_GENERIC */
#ifdef __cplusplus
}
#endif

609
firmware/CMSIS/core/core_cmFunc.h Normal file
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@ -0,0 +1,609 @@
/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V2.10
* @date 26. July 2011
*
* @note
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/* intrinsic void __enable_irq(); */
/* intrinsic void __disable_irq(); */
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
static __INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
static __INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/** \brief Get ISPR Register
This function returns the content of the ISPR Register.
\return ISPR Register value
*/
static __INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
static __INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
static __INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
static __INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
static __INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
static __INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
static __INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
static __INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
static __INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
static __INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
static __INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xff);
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
static __INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
static __INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1);
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
static __INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
static __INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** \brief Enable IRQ Interrupts
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)
{
__ASM volatile ("cpsie i");
}
/** \brief Disable IRQ Interrupts
This function disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i");
}
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void)
{
uint32_t result;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return(result);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) );
}
/** \brief Get ISPR Register
This function returns the content of the ISPR Register.
\return ISPR Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
return(result);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
return(result);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
return(result);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
return(result);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
return(result);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask" : "=r" (result) );
return(result);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) );
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void)
{
__ASM volatile ("cpsie f");
}
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void)
{
__ASM volatile ("cpsid f");
}
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)
{
uint32_t result;
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
return(result);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value)
{
__ASM volatile ("MSR basepri, %0" : : "r" (value) );
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
uint32_t result;
__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
return(result);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
#endif /* __CORE_CMFUNC_H */

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/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V2.10
* @date 19. July 2011
*
* @note
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
#define __WFI __wfi
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
#define __ISB() __isb(0xF)
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() __dsb(0xF)
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() __dmb(0xF)
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
static __INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
static __INLINE __ASM int32_t __REVSH(int32_t value)
{
revsh r0, r0
bx lr
}
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __RBIT __rbit
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXB(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXH(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXW(value, ptr) __strex(value, ptr)
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#endif /* (__CORTEX_M >= 0x03) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
__attribute__( ( always_inline ) ) static __INLINE void __NOP(void)
{
__ASM volatile ("nop");
}
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) static __INLINE void __WFI(void)
{
__ASM volatile ("wfi");
}
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) static __INLINE void __WFE(void)
{
__ASM volatile ("wfe");
}
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
__attribute__( ( always_inline ) ) static __INLINE void __SEV(void)
{
__ASM volatile ("sev");
}
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
__attribute__( ( always_inline ) ) static __INLINE void __ISB(void)
{
__ASM volatile ("isb");
}
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__attribute__( ( always_inline ) ) static __INLINE void __DSB(void)
{
__ASM volatile ("dsb");
}
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__attribute__( ( always_inline ) ) static __INLINE void __DMB(void)
{
__ASM volatile ("dmb");
}
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value)
{
uint32_t result;
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value)
{
uint32_t result;
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value)
{
uint32_t result;
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr)
{
uint8_t result;
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr)
{
uint16_t result;
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{
uint32_t result;
__ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{
uint32_t result;
__ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void)
{
__ASM volatile ("clrex");
}
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value)
{
uint8_t result;
__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
#endif /* (__CORTEX_M >= 0x03) */
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#endif
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
#endif /* __CORE_CMINSTR_H */

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/**
* Copyright (c) 2022, Nations Technologies Inc.
*
* All rights reserved.
*
* This software is the exclusive property of Nations Technologies Inc. (Hereinafter
* referred to as NATIONS). This software, and the product of NATIONS described herein
* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties
* of the People's Republic of China and other applicable jurisdictions worldwide.
*
* NATIONS does not grant any license under its patents, copyrights, trademarks, or other
* intellectual property rights. Names and brands of third party may be mentioned or referred
* thereto (if any) for identification purposes only.
*
* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and
* improvements to this software at any time without notice. Please contact NATIONS and obtain
* the latest version of this software before placing orders.
* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes
* no responsibility for the accuracy and reliability of this software.
*
* It is the responsibility of the user of this software to properly design, program, and test
* the functionality and safety of any application made of this information and any resulting product.
* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or
* consequential damages arising in any way out of the use of this software or the Product.
*
* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any
* malfunction or failure of which may cause loss of human life, bodily injury or severe property
* damage. Such applications are deemed, "Insecure Usage".
*
* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS
* harmless from and against all claims, costs, damages, and other liabilities, arising from or related
* to any customer's Insecure Usage.
* Any express or implied warranty with regard to this software or the Product, including,but not
* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement
* are disclaimed to the fullest extent permitted by law.
* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe
* or otherwise distribute this software for any purposes, in whole or in part.
*
* NATIONS products and technologies shall not be used for or incorporated into any products or systems
* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations.
* User shall comply with any applicable export control laws and regulations promulgated and administered by
* the governments of any countries asserting jurisdiction over the parties or transactions.
**/
/**
*\*\file n32g003_conf.h
*\*\author Nations
*\*\version v1.0.0
*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
**/
#ifndef __N32G003_CONF_H__
#define __N32G003_CONF_H__
/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */
#include "n32g003_adc.h"
#include "n32g003_crc.h"
#include "n32g003_comp.h"
#include "n32g003_dbg.h"
#include "n32g003_flash.h"
#include "n32g003_gpio.h"
#include "n32g003_i2c.h"
#include "n32g003_pwr.h"
#include "n32g003_rcc.h"
#include "n32g003_spi.h"
#include "n32g003_tim.h"
#include "n32g003_uart.h"
#include "n32g003_iwdg.h"
#include "n32g003_exti.h"
#include "n32g003_beeper.h"
#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
/* Uncomment the line below to expanse the "assert_param" macro in the
Standard Peripheral Library drivers code */
#endif /* __N32G003_CONF_H___CONF_H */
/******************* (C) COPYRIGHT 2022 NATIONZ *****END OF FILE****/

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; Copyright (c) 2022, Nations Technologies Inc.
;
; All rights reserved.
;
; This software is the exclusive property of Nations Technologies Inc. (Hereinafter
; referred to as NATIONS). This software, and the product of NATIONS described herein
; (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties
; of the People's Republic of China and other applicable jurisdictions worldwide.
;
; NATIONS does not grant any license under its patents, copyrights, trademarks, or other
; intellectual property rights. Names and brands of third party may be mentioned or referred
; thereto (if any) for identification purposes only.
;
; NATIONS reserves the right to make changes, corrections, enhancements, modifications, and
; improvements to this software at any time without notice. Please contact NATIONS and obtain
; the latest version of this software before placing orders.
; Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes
; no responsibility for the accuracy and reliability of this software.
;
; It is the responsibility of the user of this software to properly design, program, and test
; the functionality and safety of any application made of this information and any resulting product.
; In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or
; consequential damages arising in any way out of the use of this software or the Product.
;
; NATIONS Products are neither intended nor warranted for usage in systems or equipment, any
; malfunction or failure of which may cause loss of human life, bodily injury or severe property
; damage. Such applications are deemed, "Insecure Usage".
;
; All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS
; harmless from and against all claims, costs, damages, and other liabilities, arising from or related
; to any customer's Insecure Usage.
; Any express or implied warranty with regard to this software or the Product, including,but not
; limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement
; are disclaimed to the fullest extent permitted by law.
; Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe
; or otherwise distribute this software for any purposes, in whole or in part.
;
; NATIONS products and technologies shall not be used for or incorporated into any products or systems
; whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations.
; User shall comply with any applicable export control laws and regulations promulgated and administered by
; the governments of any countries asserting jurisdiction over the parties or transactions.
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000200
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD PVD_IRQHandler ; PVD through EXTI Line 18 detect
DCD FLASH_IRQHandler ; Flash
DCD EXTI0_1_IRQHandler ; EXTI Line 0.1
DCD EXTI2_3_IRQHandler ; EXTI Line 2.3
DCD EXTI4_17_IRQHandler ; EXTI Line 4..17
DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break/Update/Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM3_IRQHandler ; TIM3
DCD TIM6_IRQHandler ; TIM6
DCD ADC_IRQHandler ; ADC
DCD I2C_EV_IRQHandler ; I2C event
DCD I2C_ER_IRQHandler ; I2C error
DCD SPI_IRQHandler ; SPI
DCD UART1_IRQHandler ; UART1
DCD UART2_IRQHandler ; UART2
DCD COMP_IRQHandler ; COMP
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT System_Initializes
LDR R0, =System_Initializes
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT PVD_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT EXTI0_1_IRQHandler [WEAK]
EXPORT EXTI2_3_IRQHandler [WEAK]
EXPORT EXTI4_17_IRQHandler [WEAK]
EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM6_IRQHandler [WEAK]
EXPORT ADC_IRQHandler [WEAK]
EXPORT I2C_EV_IRQHandler [WEAK]
EXPORT I2C_ER_IRQHandler [WEAK]
EXPORT SPI_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT UART2_IRQHandler [WEAK]
EXPORT COMP_IRQHandler [WEAK]
PVD_IRQHandler
FLASH_IRQHandler
EXTI0_1_IRQHandler
EXTI2_3_IRQHandler
EXTI4_17_IRQHandler
TIM1_BRK_UP_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM3_IRQHandler
TIM6_IRQHandler
ADC_IRQHandler
I2C_EV_IRQHandler
I2C_ER_IRQHandler
SPI_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
COMP_IRQHandler
B .
ENDP
ALIGN
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ALIGN
ENDIF
END

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/**
* Copyright (c) 2022, Nations Technologies Inc.
*
* All rights reserved.
*
* This software is the exclusive property of Nations Technologies Inc. (Hereinafter
* referred to as NATIONS). This software, and the product of NATIONS described herein
* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties
* of the People's Republic of China and other applicable jurisdictions worldwide.
*
* NATIONS does not grant any license under its patents, copyrights, trademarks, or other
* intellectual property rights. Names and brands of third party may be mentioned or referred
* thereto (if any) for identification purposes only.
*
* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and
* improvements to this software at any time without notice. Please contact NATIONS and obtain
* the latest version of this software before placing orders.
* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes
* no responsibility for the accuracy and reliability of this software.
*
* It is the responsibility of the user of this software to properly design, program, and test
* the functionality and safety of any application made of this information and any resulting product.
* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or
* consequential damages arising in any way out of the use of this software or the Product.
*
* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any
* malfunction or failure of which may cause loss of human life, bodily injury or severe property
* damage. Such applications are deemed, "Insecure Usage".
*
* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS
* harmless from and against all claims, costs, damages, and other liabilities, arising from or related
* to any customer's Insecure Usage.
* Any express or implied warranty with regard to this software or the Product, including,but not
* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement
* are disclaimed to the fullest extent permitted by law.
* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe
* or otherwise distribute this software for any purposes, in whole or in part.
*
* NATIONS products and technologies shall not be used for or incorporated into any products or systems
* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations.
* User shall comply with any applicable export control laws and regulations promulgated and administered by
* the governments of any countries asserting jurisdiction over the parties or transactions.
**/
/**
*\*\file system_n32g003.c
*\*\author Nations
*\*\version v1.0.0
*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
*/
#include "n32g003.h"
/* Uncomment the line corresponding to the desired System clock (SYSCLK)
frequency (after reset the HSI is used as SYSCLK source)
IMPORTANT NOTE:
==============
1. After each device reset the HSI is used as System clock source.
2. Please make sure that the selected System clock doesn't exceed your
device's maximum frequency.
3. If none of the define below is enabled, the HSI is used as System clock
source.
4. The System clock configuration functions provided within this file assume
that:
- For Low, Medium and High density Value line devices an external 8MHz
crystal is used to drive the System clock.
- For Low, Medium and High density devices an external 8MHz crystal is
used to drive the System clock.
- For Connectivity line devices an external 25MHz crystal is used to
drive the System clock. If you are using different crystal you have to adapt
those functions accordingly.
*/
#define SYSCLK_USE_HSI48M 0
#define SYSCLK_USE_HSI40M 1
/*** Configure system clock frequency ***/
#ifndef SYSCLK_FREQ
#define SYSCLK_FREQ 48000000
#endif
/******* Select one ******
** SYSCLK_USE_HSI48M **
** SYSCLK_USE_HSI40M ***/
#ifndef SYSCLK_SRC
#define SYSCLK_SRC SYSCLK_USE_HSI48M
#endif
#if SYSCLK_SRC == SYSCLK_USE_HSI48M
#if (SYSCLK_FREQ == SYSCLK_FREQ_48M)
#define SYS_DIV RCC_CFG_SYSPRES_DIV1
#elif (SYSCLK_FREQ == SYSCLK_FREQ_24M)
#define SYS_DIV RCC_CFG_SYSPRES_DIV2
#elif (SYSCLK_FREQ == SYSCLK_FREQ_8M)
#define SYS_DIV RCC_CFG_SYSPRES_DIV6
#else
#error Cannot make a prescaler to SYSCLK_FREQ.
#endif
#elif SYSCLK_SRC == SYSCLK_USE_HSI40M
#if (SYSCLK_FREQ == SYSCLK_FREQ_40M)
#define SYS_DIV RCC_CFG_SYSPRES_DIV1
#elif (SYSCLK_FREQ == SYSCLK_FREQ_8M)
#define SYS_DIV RCC_CFG_SYSPRES_DIV5
#else
#error Cannot make a prescaler to SYSCLK_FREQ.
#endif
#else
#error wrong value for SYSCLK_SRC
#endif
/* If you want to use VECT_TAB_SRAM, release the comment*/
/* #define VECT_TAB_SRAM */
/* Vector Table base offset field. This value must be a multiple of 0x200. */
#define VECT_TAB_OFFSET 0x0
/** Clock Definitions **/
/* System Clock Frequency (Core Clock) */
uint32_t SystemCoreClockFrequency = SYSCLK_FREQ;
const uint8_t AHBPrescTable[16] = {1, 1, 1, 1, 1, 1, 1, 1, 2, 4, 8, 12, 16, 24, 24,24};
static void System_Clock_Set(void);
/**
*\*\name System_Initializes.
*\*\fun Setup the microcontroller system
*\*\ Initialize the Embedded Flash Interface, update the
*\*\ SystemCoreClockFrequency variable.
*\*\param none.
*\*\return none
*\*\note This function should be used only after reset.
**/
void System_Initializes(void)
{
/* Reset the RCC clock configuration to the default reset state(for debug purpose) */
/* Set HSI 48M bit */
PWR->CTRL3 &= ~((uint16_t)0x0040); //48M
/* Set SYSPRES[1:0] bit */
RCC->CFG |= (uint32_t)0x00003000;
/* Reset MCO[1:0] APBPRES[2:0] AHBPRES[3:0] bit */
RCC->CFG &= (uint32_t)0xF9FFF80F;
/* Reset LSIDETEN bit */
RCC->LSICTRL &= (uint32_t)0xFFFFFF7F;
/* Reset TIM1CLKSEL TIM6CLKSEL ADCPRES[3:0]bit */
RCC->CFG2 &= (uint32_t)0x3FFFFFF0;
/* Set ADC1MPRES[1:0] ADCPRES[3:0]bit */
RCC->CFG2 |= (uint32_t)0x00000C01;
/* Enable Prefetch Buffer */
FLASH->AC |= (uint32_t)(FLASH_AC_PRFTBFEN);
/* Configure the System clock frequency, HCLK PCLK prescalers */
/* Configure the Flash Latency cycles and enable prefetch buffer */
System_Clock_Set();
#ifdef VECT_TAB_SRAM
FLASH->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
#else
FLASH->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
#endif
}
/**
*\*\name System_Clock_Frequency_Update.
*\*\fun Update SystemCoreClockFrequency variable according to Clock Register Values.
*\*\ The SystemCoreClockFrequency variable contains the core clock (HCLK), it can
*\*\ be used by the user application to setup the SysTick timer or
*\*\ configure other parameters.
*\*\param none.
*\*\return none
*\*\note Each time the core clock (HCLK) changes, this function must be called
*\*\ to update SystemCoreClockFrequency variable value. Otherwise, any
*\*\ configuration based on this variable will be incorrect.
*\*\
*\*\note The system frequency computed by this function is not the real
*\*\ frequency in the chip. It is calculated based on the predefined
*\*\ constant and the selected clock source.
*\*\
**/
void System_Core_Clock_Frequency_Update(void)
{
uint32_t temp_value = 0;
uint32_t hclkdiv_value = 0;
/* Get SYSCLK source
* -------------------------------------------------------*/
temp_value = PWR->CTRL3 & PWR_CTRL3_HSISEL;
switch (temp_value)
{
case PWR_CTRL3_HSISEL: /* HSI 40M used as system clock */
if((RCC->CFG & RCC_CFG_SYSPRES) == RCC_CFG_SYSPRES_DIV1)
{
SystemCoreClockFrequency = SYSCLK_FREQ_40M;
}
else
{
SystemCoreClockFrequency = SYSCLK_FREQ_8M;
}
break;
default:/* HSI 48M used as system clock */
if((RCC->CFG & RCC_CFG_SYSPRES) == RCC_CFG_SYSPRES_DIV1)
{
SystemCoreClockFrequency = SYSCLK_FREQ_48M;
}
else if((RCC->CFG & RCC_CFG_SYSPRES) == RCC_CFG_SYSPRES_DIV2)
{
SystemCoreClockFrequency = SYSCLK_FREQ_24M;
}
else
{
SystemCoreClockFrequency = SYSCLK_FREQ_8M;
}
break;
}
/* Compute HCLK clock frequency ----------------*/
/* Get HCLK prescaler */
hclkdiv_value = AHBPrescTable[((RCC->CFG & RCC_CFG_AHBPRES) >> 4)];
/* HCLK clock frequency */
SystemCoreClockFrequency /= hclkdiv_value;
}
/**
*\*\name Systeminit_Flash_Latency_Set
*\*\fun Sets the code latency value.
*\*\note This function can be used for N32G003 devices.
*\*\param flash_latency :
*\*\ - FLASH_AC_LATENCY_0 FLASH Zero Latency cycle, 0 < HCLK <= 24MHz
*\*\ - FLASH_AC_LATENCY_1 FLASH One Latency cycle, 24MHz < HCLK<= 48MHz
*\*\return none
**/
static void Systeminit_Flash_Latency_Set(uint32_t flash_latency)
{
uint32_t temp_value = 0;
/* Read the AC register */
temp_value = FLASH->AC;
/* Sets the Latency value */
temp_value &= (~FLASH_LATENCY_MASK);
temp_value |= flash_latency;
/* Write the AC register */
FLASH->AC = temp_value;
}
/**
*\*\name System_Clock_Set.
*\*\fun Configures the System clock frequency, HCLK and PCLK prescalers.
*\*\param none.
*\*\return none
**/
static void System_Clock_Set(void)
{
volatile uint32_t temp_value = 0,status_value = 0;
volatile uint32_t counter_value = 0;
/* Flash wait state 0: SYSCLK <= 24M 1: SYSCLK <= 48M */
if(SYSCLK_FREQ <= SYSCLK_FREQ_24M)
{
/*8M\24M */
Systeminit_Flash_Latency_Set(FLASH_AC_LATENCY_0);
}
else
{
/*40M\48M */
Systeminit_Flash_Latency_Set(FLASH_AC_LATENCY_1);
}
/* HCLK = SYSCLK */
RCC->CFG |= (uint32_t)RCC_CFG_AHBPRES_DIV1;
/* PCLK = HCLK */
RCC->CFG |= (uint32_t)RCC_CFG_APBPRES_DIV1;
#if (SYSCLK_SRC == SYSCLK_USE_HSI48M)
/* Select HSI 48M*/
PWR->CTRL3 &= ~PWR_CTRL3_HSISEL; //48M
/* Wait till HSI is ready and if Time out is reached exit */
do
{
status_value = RCC->HSICTRL & RCC_HSICTRL_HSI48MRDF;
counter_value++;
} while ((status_value == 0) && (counter_value != HSI_STARTUP_TIMEOUT));
if(status_value == RCC_HSICTRL_HSI48MRDF)
{
RCC_Sysclk_Config(SYS_DIV);
}
else
{
while(1);
}
#elif (SYSCLK_SRC == SYSCLK_USE_HSI40M)
/* Select HSI 40M */
PWR->CTRL3 |= PWR_CTRL3_HSISEL; //40M
/* Wait till HSI is ready and if Time out is reached exit */
do
{
status_value = RCC->HSICTRL & RCC_HSICTRL_HSI40MRDF;
counter_value++;
} while ((status_value == 0) && (counter_value != HSI_STARTUP_TIMEOUT));
if(status_value == RCC_HSICTRL_HSI40MRDF)
{
RCC_Sysclk_Config(SYS_DIV);
}
else
{
while(1);
}
#endif
}

80
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/**
* Copyright (c) 2022, Nations Technologies Inc.
*
* All rights reserved.
*
* This software is the exclusive property of Nations Technologies Inc. (Hereinafter
* referred to as NATIONS). This software, and the product of NATIONS described herein
* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties
* of the People's Republic of China and other applicable jurisdictions worldwide.
*
* NATIONS does not grant any license under its patents, copyrights, trademarks, or other
* intellectual property rights. Names and brands of third party may be mentioned or referred
* thereto (if any) for identification purposes only.
*
* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and
* improvements to this software at any time without notice. Please contact NATIONS and obtain
* the latest version of this software before placing orders.
* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes
* no responsibility for the accuracy and reliability of this software.
*
* It is the responsibility of the user of this software to properly design, program, and test
* the functionality and safety of any application made of this information and any resulting product.
* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or
* consequential damages arising in any way out of the use of this software or the Product.
*
* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any
* malfunction or failure of which may cause loss of human life, bodily injury or severe property
* damage. Such applications are deemed, "Insecure Usage".
*
* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS
* harmless from and against all claims, costs, damages, and other liabilities, arising from or related
* to any customer's Insecure Usage.
* Any express or implied warranty with regard to this software or the Product, including,but not
* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement
* are disclaimed to the fullest extent permitted by law.
* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe
* or otherwise distribute this software for any purposes, in whole or in part.
*
* NATIONS products and technologies shall not be used for or incorporated into any products or systems
* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations.
* User shall comply with any applicable export control laws and regulations promulgated and administered by
* the governments of any countries asserting jurisdiction over the parties or transactions.
**/
/**
*\*\file system_n32g003.h
*\*\author Nations
*\*\version v1.0.0
*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
**/
#ifndef __SYSTEM_N32G003_H
#define __SYSTEM_N32G003_H
#ifdef __cplusplus
extern "C" {
#endif
#define SYSCLK_FREQ_48M (48000000)
#define SYSCLK_FREQ_40M (40000000)
#define SYSCLK_FREQ_24M (24000000)
#define SYSCLK_FREQ_8M (8000000)
extern uint32_t SystemCoreClockFrequency; /* System Clock Frequency (Core Clock) */
extern void System_Initializes(void);
extern void System_Core_Clock_Frequency_Update(void);
#ifdef __cplusplus
}
#endif
#endif /*__SYSTEM_N32G003_H */

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/**
* Copyright (c) 2022, Nations Technologies Inc.
*
* All rights reserved.
*
* This software is the exclusive property of Nations Technologies Inc. (Hereinafter
* referred to as NATIONS). This software, and the product of NATIONS described herein
* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties
* of the People's Republic of China and other applicable jurisdictions worldwide.
*
* NATIONS does not grant any license under its patents, copyrights, trademarks, or other
* intellectual property rights. Names and brands of third party may be mentioned or referred
* thereto (if any) for identification purposes only.
*
* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and
* improvements to this software at any time without notice. Please contact NATIONS and obtain
* the latest version of this software before placing orders.
* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes
* no responsibility for the accuracy and reliability of this software.
*
* It is the responsibility of the user of this software to properly design, program, and test
* the functionality and safety of any application made of this information and any resulting product.
* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or
* consequential damages arising in any way out of the use of this software or the Product.
*
* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any
* malfunction or failure of which may cause loss of human life, bodily injury or severe property
* damage. Such applications are deemed, "Insecure Usage".
*
* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS
* harmless from and against all claims, costs, damages, and other liabilities, arising from or related
* to any customer's Insecure Usage.
* Any express or implied warranty with regard to this software or the Product, including,but not
* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement
* are disclaimed to the fullest extent permitted by law.
* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe
* or otherwise distribute this software for any purposes, in whole or in part.
*
* NATIONS products and technologies shall not be used for or incorporated into any products or systems
* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations.
* User shall comply with any applicable export control laws and regulations promulgated and administered by
* the governments of any countries asserting jurisdiction over the parties or transactions.
**/
/**
*\*\file misc.h
*\*\author Nations
*\*\version v1.0.0
*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
**/
#ifndef __MISC_H__
#define __MISC_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "n32g003.h"
/** MISC Driving Functions Declaration **/
/** NVIC Init Structure definition **/
typedef struct
{
IRQn_Type NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.
This parameter can be a value of @ref IRQn_Type
(For the complete N32G003 Devices IRQ Channels list, please
refer to n32g003.h file) */
uint8_t NVIC_IRQChannelPriority; /*!< Specifies the priority for the IRQ channel
specified in NVIC_IRQChannel. This parameter can be a value
between 0 and 3 */
FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
will be enabled or disabled.
This parameter can be set either to ENABLE or DISABLE */
} NVIC_InitType;
/** MISC driver modules **/
#define AIRCR_VECTKEY_MASK SCB_AIRCR_VECTKEY /* access key */
/** NVIC Priority **/
#define NVIC_PRIORITY_0 ((uint8_t)0x00)
#define NVIC_PRIORITY_1 ((uint8_t)0x01)
#define NVIC_PRIORITY_2 ((uint8_t)0x02)
#define NVIC_PRIORITY_3 ((uint8_t)0x03)
/** System_Low_Power **/
#define NVIC_LP_SEVONPEND (SCB_SCR_SEVONPEND)
#define NVIC_LP_SLEEPDEEP (SCB_SCR_SLEEPDEEP)
#define NVIC_LP_SLEEPONEXIT (SCB_SCR_SLEEPONEXIT)
/** SysTick_clock_source **/
#define SYSTICK_CLKSOURCE_HCLK_DIV8 (~SysTick_CTRL_CLKSOURCE)
#define SYSTICK_CLKSOURCE_HCLK (SysTick_CTRL_CLKSOURCE)
void NVIC_Initializes(NVIC_InitType* NVIC_structure_initializes);
void NVIC_System_LowPower_Enable(uint8_t low_power_mode);
void NVIC_System_Low_Power_Disable(uint8_t low_power_mode);
void SysTick_Clock_Source_Set(uint32_t systick_clock_source);
#ifdef __cplusplus
}
#endif
#endif /* __MISC_H */

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/**
* Copyright (c) 2022, Nations Technologies Inc.
*
* All rights reserved.
*
* This software is the exclusive property of Nations Technologies Inc. (Hereinafter
* referred to as NATIONS). This software, and the product of NATIONS described herein
* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties
* of the People's Republic of China and other applicable jurisdictions worldwide.
*
* NATIONS does not grant any license under its patents, copyrights, trademarks, or other
* intellectual property rights. Names and brands of third party may be mentioned or referred
* thereto (if any) for identification purposes only.
*
* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and
* improvements to this software at any time without notice. Please contact NATIONS and obtain
* the latest version of this software before placing orders.
* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes
* no responsibility for the accuracy and reliability of this software.
*
* It is the responsibility of the user of this software to properly design, program, and test
* the functionality and safety of any application made of this information and any resulting product.
* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or
* consequential damages arising in any way out of the use of this software or the Product.
*
* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any
* malfunction or failure of which may cause loss of human life, bodily injury or severe property
* damage. Such applications are deemed, "Insecure Usage".
*
* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS
* harmless from and against all claims, costs, damages, and other liabilities, arising from or related
* to any customer's Insecure Usage.
* Any express or implied warranty with regard to this software or the Product, including,but not
* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement
* are disclaimed to the fullest extent permitted by law.
* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe
* or otherwise distribute this software for any purposes, in whole or in part.
*
* NATIONS products and technologies shall not be used for or incorporated into any products or systems
* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations.
* User shall comply with any applicable export control laws and regulations promulgated and administered by
* the governments of any countries asserting jurisdiction over the parties or transactions.
**/
/**
*\*\file n32g003_adc.h
*\*\author Nations
*\*\version v1.0.0
*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
**/
#ifndef __N32G003_ADC_H__
#define __N32G003_ADC_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "n32g003.h"
/** ADC init structure definition **/
typedef struct
{
FunctionalState MultiChEn; /* Specifies whether the conversion is performed in
Scan (multichannels) or Single (one channel) mode */
FunctionalState ContinueConvEn; /* Specifies whether the conversion is performed in
Continuous or Single mode */
uint32_t ExtTrigSelect; /* Defines the external trigger used to start the analog
to digital conversion of regular channels */
uint32_t DatAlign; /* Specifies whether the ADC data alignment is left or right */
uint32_t ChsNumber; /* Specifies the number of ADC channels that will be converted
using the sequencer for regular channel group */
} ADC_InitType;
/** ADC scan conversion define **/
#define ADC_MULTCH_ENABLE ((uint32_t)(0x00001000)) /* ADC_CTRL2 SCANMD bits */
#define ADC_MULTCH_DISABLE ((uint32_t)(~0x00001000))
/** ADC continue conversion define **/
#define ADC_CTU_ENABLE ((uint32_t)(0x00000002)) /* ADC_CTRL2 CTU bits */
#define ADC_CTU_DISABLE ((uint32_t)(~0x00000002))
/** ADC external trigger sources for regular channels conversion define **/
#define ADC_EXT_TRIGCONV_REGULAR_MASK ((uint32_t)(~(0x00000078|0x00000080))) /* ADC_CTRL2 EXTRSEL[3:0] bits Mask */
#define ADC_EXT_TRIGCONV_REGULAR_T1_CC1 ((uint32_t)(0x00000000|0x00000080))
#define ADC_EXT_TRIGCONV_REGULAR_T1_CC2 ((uint32_t)(0x00000008|0x00000080))
#define ADC_EXT_TRIGCONV_REGULAR_T1_CC3 ((uint32_t)(0x00000010|0x00000080))
#define ADC_EXT_TRIGCONV_REGULAR_T1_CC4 ((uint32_t)(0x00000018|0x00000080))
#define ADC_EXT_TRIGCONV_REGULAR_T1_TRGO ((uint32_t)(0x00000020|0x00000080))
#define ADC_EXT_TRIGCONV_REGULAR_T3_TRGO ((uint32_t)(0x00000028|0x00000080))
#define ADC_EXT_TRIGCONV_REGULAR_T3_CC1 ((uint32_t)(0x00000030|0x00000080))
#define ADC_EXT_TRIGCONV_REGULAR_T3_CC2 ((uint32_t)(0x00000038|0x00000080))
#define ADC_EXT_TRIGCONV_REGULAR_EXT_INT11 ((uint32_t)(0x00000040|0x00000080))
#define ADC_EXT_TRIGCONV_REGULAR_SWSTRRCH ((uint32_t)0x00000048)
/** ADC data alignment define **/
#define ADC_ALIG_MASK ((uint32_t)(~0x00000004)) /* ADC_CTRL2 ALIG bits Mask */
#define ADC_DAT_ALIGN_R ((uint32_t)0x00000000)
#define ADC_DAT_ALIGN_L ((uint32_t)0x00000004)
/** ADC regular channel sequence length define **/
#define ADC_REGULAR_LEN_MSAK ((uint32_t)(~0x00000E00)) /* ADC_CTRL2 LEN[2:0] bits Mask */
#define ADC_REGULAR_LEN_1 ((uint32_t)0x00000000)
#define ADC_REGULAR_LEN_2 ((uint32_t)0x00000200)
#define ADC_REGULAR_LEN_3 ((uint32_t)0x00000400)
#define ADC_REGULAR_LEN_4 ((uint32_t)0x00000600)
#define ADC_REGULAR_LEN_5 ((uint32_t)0x00000800)
/** ADC channels define **/
#define ADC_SQR_MASK ((uint32_t)~0x000f0000)
#define ADC_SQR_OFFSET ((uint32_t)0X10)
#define ADC_CH_0 ((uint8_t)0x00)
#define ADC_CH_1 ((uint8_t)0x01)
#define ADC_CH_2 ((uint8_t)0x02)
#define ADC_CH_3 ((uint8_t)0x03)
#define ADC_CH_4 ((uint8_t)0x04)
#define ADC_CH_5 ((uint8_t)0x05)
#define ADC_CH_6 ((uint8_t)0x06)
#define ADC_CH_7 ((uint8_t)0x07)
#define ADC_CH_8 ((uint8_t)0x08)
#define ADC_CH_9 ((uint8_t)0x09)
#define ADC_CH_10 ((uint8_t)0x0A)
#define ADC_CH_INT_VBG ((uint8_t)ADC_CH_9)
#define ADC_CH_INT_VDDA ((uint8_t)ADC_CH_10)
#define ADC_Channel_00_PA1 ((uint8_t)0x00)
#define ADC_Channel_01_PA2 ((uint8_t)0x01)
#define ADC_Channel_02_PA5 ((uint8_t)0x02)
#define ADC_Channel_03_PA10 ((uint8_t)0x03)
#define ADC_Channel_04_PA12 ((uint8_t)0x04)
#define ADC_Channel_05_PA13 ((uint8_t)0x05)
#define ADC_Channel_06_PA14 ((uint8_t)0x06)
#define ADC_Channel_07_PB0 ((uint8_t)0x07)
#define ADC_Channel_08_PB1 ((uint8_t)0x08)
#define ADC_Channel_09_VBG ((uint8_t)0x09)
#define ADC_Channel_10_VDDA ((uint8_t)0x0A)
/** ADC converter operation define **/
#define ADC_TURN_ON ((uint32_t)0x00000001) /* A/D Converter ON / OFF */
#define ADC_TURN_OFF ((uint32_t)(~0x00000001))
/** ADC interrupts define **/
#define ADC_INT_ENDC ((uint32_t)0x00000010) /* Interrupt enable for EOC */
#define ADC_INT_AWD ((uint32_t)0x00000020) /* Analog Watchdog interrupt enable */
#define ADC_INT_ENDCA ((uint32_t)0x00000020) /* Interrupt enable for any EOC */
#define ADC_SET_INT_TYPE_ENDCA ((uint8_t) 0x01) /* Interrupt enable for any EOC */
#define ADC_SET_INT_TYPE_OTHER ((uint8_t) 0x00) /* Interrupt enable for other */
#define ADC_EXTTRIGCONV_REGULAR_ENABLE ((uint32_t)ADC_CTRL2_EXTRTRIG)
#define ADC_EXTTRIGCONV_REGULAR_DISABLE ((uint32_t)(~ADC_CTRL2_EXTRTRIG))
#define ADC_EXTRTRIG_SWSTRRCH_ENABLE ((uint32_t)(ADC_CTRL2_EXTRTRIG | ADC_CTRL2_SWSTRRCH))
#define ADC_EXTRTRIG_SWSTRRCH_DISABLE ((uint32_t)(~(ADC_CTRL2_EXTRTRIG | ADC_CTRL2_SWSTRRCH)))
#define ADC_EXTRTRIG_SWSTRRCH_GET_STS ((uint32_t)ADC_CTRL2_SWSTRRCH)
/** ADC sampling time define **/
#define ADC_SAMP_TIME_MASK ((uint32_t)~0x0000001F)
#define ADC_SAMP_TIME_RESERVED ((uint32_t)0x0)
#define ADC_SAMP_TIME_8CYCLES ((uint32_t)0x1)
#define ADC_SAMP_TIME_12CYCLES ((uint32_t)0x2)
#define ADC_SAMP_TIME_14CYCLES ((uint32_t)0x3)
#define ADC_SAMP_TIME_20CYCLES ((uint32_t)0x4)
#define ADC_SAMP_TIME_26CYCLES ((uint32_t)0x5)
#define ADC_SAMP_TIME_30CYCLES ((uint32_t)0x6)
#define ADC_SAMP_TIME_42CYCLES ((uint32_t)0x7)
#define ADC_SAMP_TIME_56CYCLES ((uint32_t)0x8)
#define ADC_SAMP_TIME_72CYCLES ((uint32_t)0x9)
#define ADC_SAMP_TIME_88CYCLES ((uint32_t)0xA)
#define ADC_SAMP_TIME_120CYCLES ((uint32_t)0xB)
#define ADC_SAMP_TIME_182CYCLES ((uint32_t)0xC)
#define ADC_SAMP_TIME_240CYCLES ((uint32_t)0xD)
#define ADC_SAMP_TIME_380CYCLES ((uint32_t)0xE)
#define ADC_SAMP_TIME_760CYCLES ((uint32_t)0xF)
#define ADC_SAMP_TIME_1520CYCLES ((uint32_t)0x10)
#define ADC_SAMP_TIME_3040CYCLES ((uint32_t)0x11)
/** ADC analog watchdog mode define **/
#define ADC_ANALOG_WTDG_MODE_MASK ((uint32_t)(~0x00000040))
#define ADC_ANALOG_WTDG_SINGLE_MODE ((uint32_t)0x00000040)/* Enable the watchdog on a single channel in scan mode */
#define ADC_ANALOG_WTDG_SCAN_MODE ((uint32_t)0x00000000)
/** ADC analog watchdog single mode channel define**/
#define ADC_ANALOG_WTDG_SINGLE_CH_MASK ((uint32_t)(~0x0000000F))/* AWDG_CH[4:0] bits (Analog watchdog channel select bits) */
#define ADC_ANALOG_WTDG_SINGLE_CH0 ((uint8_t)0X00)
#define ADC_ANALOG_WTDG_SINGLE_CH1 ((uint8_t)0X01)
#define ADC_ANALOG_WTDG_SINGLE_CH2 ((uint8_t)0X02)
#define ADC_ANALOG_WTDG_SINGLE_CH3 ((uint8_t)0X03)
#define ADC_ANALOG_WTDG_SINGLE_CH4 ((uint8_t)0X04)
#define ADC_ANALOG_WTDG_SINGLE_CH5 ((uint8_t)0X05)
#define ADC_ANALOG_WTDG_SINGLE_CH6 ((uint8_t)0X06)
#define ADC_ANALOG_WTDG_SINGLE_CH7 ((uint8_t)0X07)
#define ADC_ANALOG_WTDG_SINGLE_CH8 ((uint8_t)0X08)
#define ADC_ANALOG_WTDG_SINGLE_CH9 ((uint8_t)0X09)
#define ADC_ANALOG_WTDG_SINGLE_CH10 ((uint8_t)0X0A)
/** ADC ADC Analog watchdog on regular channels define **/
#define ADC_ANALOG_WTDG_REGULAR ((uint32_t)0x00000080) /* ADC_CTRL1 AWDGERCH bit */
/** ADC flags definition **/
#define ADC_RUN_FLAG ((uint8_t)0x01)
#define ADC_RD_FLAG ((uint8_t)0x02)
#define ADC_INT_FLAG_AWDG ((uint8_t)0x01)
#define ADC_INT_FLAG_ENDC ((uint8_t)0x02)
#define ADC_INT_FLAG_ENDCA ((uint8_t)0x08)
#define ADC_FLAG_AWDG ((uint8_t)0x01)
#define ADC_FLAG_ENDC ((uint8_t)0x02)
#define ADC_FLAG_STR ((uint8_t)0x04)
#define ADC_FLAG_ENDCA ((uint8_t)0x08)
/** ADC flags ex definition **/
#define ADC_FLAG_BUF_RDY ((uint8_t)0x04)
#define ADC_FLAG_RDY ((uint8_t)0x08)
#define ADC_FLAG_PD_RDY ((uint8_t)0x10)
/** ADC regular data register define **/
#define ADC_DATA_OFFSET0 ((uint8_t)0x00)
#define ADC_DATA_OFFSET1 ((uint8_t)0X01)
#define ADC_DATA_OFFSET2 ((uint8_t)0X02)
#define ADC_DATA_OFFSET3 ((uint8_t)0X03)
#define ADC_DATA_OFFSET4 ((uint8_t)0X04)
/** ADC internal input buffer definition **/
#define ADC_IN_BUFFER_ENABLE ((uint32_t)0x00000002) /*ADC internal input buffer enable.*/
#define ADC_IN_BUFFER_DISABLE ((uint32_t)(~0x00000002))
/* ADC data registers read define */
#define ADC_DATA_REG_READ(data, num) (*(uint32_t*)(&data+num))
/** ADC Driving Functions Declaration **/
void ADC_Reset(void);
void ADC_Multichannels_Enable(void);
void ADC_Multichannels_Disable(void);
void ADC_Continue_Conversion_Enable(void);
void ADC_Continue_Conversion_Disable(void);
void ADC_Regular_Group_External_Trigger_Source_Config(uint32_t external_trigger_sources);
void ADC_Data_Alignment_Config(uint32_t data_alignment);
void ADC_Regular_Channels_Number_Config(uint32_t channels_number);
void ADC_Initializes(ADC_InitType* ADC_initstruct);
void ADC_Initializes_Structure(ADC_InitType* ADC_initstruct);
void ADC_ON(void);
void ADC_OFF(void);
void ADC_Interrupts_Enable(u8 eoc_any, uint32_t adc_interrupt);
void ADC_Interrupts_Disable(u8 eoc_any, uint32_t adc_interrupt);
FlagStatus ADC_Regular_Channels_Software_Conversion_Operation(uint32_t conversion_operation);
void ADC_Channel_Sample_Time_Config(uint8_t sample_time);
void ADC_External_Trigger_Conversion_Config(uint32_t group_operation);
uint16_t ADC_Regular_Conversion_Data_Get(void);
uint16_t ADC_Regular_Group_Conversion_Data_Get(uint8_t number);
void ADC_Analog_Watchdog_Mode_Channel_Config(uint32_t mode, uint8_t channel);
void ADC_Analog_Watchdog_Enable(uint32_t wcdg_mode);
void ADC_Analog_Watchdog_Disable(uint32_t wcdg_mode);
void ADC_Analog_Watchdog_HighThresholds_Config(uint16_t high_thresholds);
void ADC_Analog_Watchdog_LowThresholds_Config(uint16_t low_thresholds);
FlagStatus ADC_INTFlag_Status_Get(uint8_t adc_flag);
FlagStatus ADC_Flag_Status_Get(uint8_t selflag, uint8_t adc_runflag, uint8_t adc_rdflag);
void ADC_INTFlag_Status_Clear(uint8_t adc_flag);
void ADC_Flag_Status_Clear(uint8_t adc_flag);
void ADC_Regular_Sequence_Single_Config(uint8_t channel);
void ADC_Regular_Sequence_Multi_Config(uint8_t channel,uint8_t number);
void ADC_Internal_Input_Buffer_Enable(void);
void ADC_Internal_Input_Buffer_Disable(void);
#ifdef __cplusplus
}
#endif
#endif /*__N32G003_ADC_H__ */

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/**
* Copyright (c) 2022, Nations Technologies Inc.
*
* All rights reserved.
*
* This software is the exclusive property of Nations Technologies Inc. (Hereinafter
* referred to as NATIONS). This software, and the product of NATIONS described herein
* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties
* of the People's Republic of China and other applicable jurisdictions worldwide.
*
* NATIONS does not grant any license under its patents, copyrights, trademarks, or other
* intellectual property rights. Names and brands of third party may be mentioned or referred
* thereto (if any) for identification purposes only.
*
* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and
* improvements to this software at any time without notice. Please contact NATIONS and obtain
* the latest version of this software before placing orders.
* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes
* no responsibility for the accuracy and reliability of this software.
*
* It is the responsibility of the user of this software to properly design, program, and test
* the functionality and safety of any application made of this information and any resulting product.
* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or
* consequential damages arising in any way out of the use of this software or the Product.
*
* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any
* malfunction or failure of which may cause loss of human life, bodily injury or severe property
* damage. Such applications are deemed, "Insecure Usage".
*
* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS
* harmless from and against all claims, costs, damages, and other liabilities, arising from or related
* to any customer's Insecure Usage.
* Any express or implied warranty with regard to this software or the Product, including,but not
* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement
* are disclaimed to the fullest extent permitted by law.
* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe
* or otherwise distribute this software for any purposes, in whole or in part.
*
* NATIONS products and technologies shall not be used for or incorporated into any products or systems
* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations.
* User shall comply with any applicable export control laws and regulations promulgated and administered by
* the governments of any countries asserting jurisdiction over the parties or transactions.
**/
/**
*\*\file n32g003_beeper.h
*\*\author Nations
*\*\version v1.0.0
*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
**/
#ifndef __N32G003_BEEPER_H__
#define __N32G003_BEEPER_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "n32g003.h"
#define BEEPER_ENABLE (BEEPER_CTRL_EN) /* Enable Beeper */
#define BEEPER_DISABLE (~BEEPER_CTRL_EN) /* Disable Beeper */
#define BEEPER_INV_ENABLE (BEEPER_CTRL_INV_EN) /* Only one output, the other output is off */
#define BEEPER_INV_DISABLE (~BEEPER_CTRL_INV_EN) /* Both outputs are on, and the outputs are complementary */
#define BEEPER_FREQ_SEL_MASK (~BEEPER_CTRL_FREQ_SEL)
#define BEEPER_FREQ_8KHZ (BEEPER_CTRL_FREQ_SEL_8K)
#define BEEPER_FREQ_4KHZ (BEEPER_CTRL_FREQ_SEL_4K)
#define BEEPER_FREQ_2KHZ (BEEPER_CTRL_FREQ_SEL_2K)
#define BEEPER_FREQ_1KHZ (BEEPER_CTRL_FREQ_SEL_1K)
void BEEPER_Reset(void);
void BEEPER_Frequency_Select(uint32_t freq_selection);
void BEEPER_Inverted_Enable(void);
void BEEPER_Inverted_Disable(void);
void BEEPER_Enable(void);
void BEEPER_Disable(void);
#ifdef __cplusplus
}
#endif
#endif /* __N32G003_BEEPER_H__ */

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/**
* Copyright (c) 2022, Nations Technologies Inc.
*
* All rights reserved.
*
* This software is the exclusive property of Nations Technologies Inc. (Hereinafter
* referred to as NATIONS). This software, and the product of NATIONS described herein
* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties
* of the People's Republic of China and other applicable jurisdictions worldwide.
*
* NATIONS does not grant any license under its patents, copyrights, trademarks, or other
* intellectual property rights. Names and brands of third party may be mentioned or referred
* thereto (if any) for identification purposes only.
*
* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and
* improvements to this software at any time without notice. Please contact NATIONS and obtain
* the latest version of this software before placing orders.
* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes
* no responsibility for the accuracy and reliability of this software.
*
* It is the responsibility of the user of this software to properly design, program, and test
* the functionality and safety of any application made of this information and any resulting product.
* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or
* consequential damages arising in any way out of the use of this software or the Product.
*
* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any
* malfunction or failure of which may cause loss of human life, bodily injury or severe property
* damage. Such applications are deemed, "Insecure Usage".
*
* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS
* harmless from and against all claims, costs, damages, and other liabilities, arising from or related
* to any customer's Insecure Usage.
* Any express or implied warranty with regard to this software or the Product, including,but not
* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement
* are disclaimed to the fullest extent permitted by law.
* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe
* or otherwise distribute this software for any purposes, in whole or in part.
*
* NATIONS products and technologies shall not be used for or incorporated into any products or systems
* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations.
* User shall comply with any applicable export control laws and regulations promulgated and administered by
* the governments of any countries asserting jurisdiction over the parties or transactions.
**/
/**
*\*\file n32g003_comp.h
*\*\author Nations
*\*\version v1.0.0
*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
**/
#ifndef __N32G003_COMP_H
#define __N32G003_COMP_H
#ifdef __cplusplus
extern "C" {
#endif
#include "n32g003.h"
#include <stdbool.h>
/** Bit operation definition **/
#define SetBitMsk(reg, bit, msk) ((reg) = ((reg) & ~(msk) | (bit)))
#define ClrBit(reg, bit) ((reg) &= ~(bit))
#define SetBit(reg, bit) ((reg) |= (bit))
#define GetBit(reg, bit) ((reg) & (bit))
/** COMP init structure definition **/
typedef struct
{
/* ctrl define */
uint32_t Blking; /* Specifies which timer can control the comp output blanking with its capture event */
uint32_t Hyst; /* Specifies the comp hysteresis level with low/medium/high level */
uint32_t PolRev; /* Specifies the comp output polarity */
uint32_t OutSel; /* Specifies which timer input that can be connecte to the comp output */
uint32_t SubSel; /* Specifies the comp subtract level with 0/100mv/200mv/300mv level */
uint32_t InpSel; /* Specifies the comp inpsel */
uint32_t InmSel; /* Specifies the comp inmsel */
uint32_t En; /* enable or disable the comp */
/* filter define */
uint8_t SampWindow; /* Initializes comp sampwindow value ~5bit */
uint8_t Threshold; /* ~5bit ,need > SampWindow/2 */
uint8_t FilterEn; /* enable or disable the comp filter */
/* filter prescale */
uint16_t ClkPsc; /* Initializes comp clkpsc value ~5bit */
} COMP_InitType;
/** COMP blanking definition **/
#define COMP_BLANKING_MASK ((uint32_t)(~COMP_CTRL_BLKING))
#define COMP_BLANKING_NO ((uint32_t)0x00000000)
#define COMP_BLANKING_TIM1_OC5 ((uint32_t)COMP_CTRL_BLKING)
/** COMP hysteresis definition **/
#define COMP_HYST_MASK ((uint32_t)(~COMP_CTRL_HYST))
#define COMP_HYST_NO ((uint32_t)0x00000000)
#define COMP_HYST_LOW ((uint32_t)COMP_CTRL_HYST_0)
#define COMP_HYST_MID ((uint32_t)COMP_CTRL_HYST_1)
#define COMP_HYST_HIGH ((uint32_t)(COMP_CTRL_HYST_0 | COMP_CTRL_HYST_1))
/** COMP output polarity definition **/
#define COMP_OUTPOL_MASK ((uint32_t)(~COMP_CTRL_POL))
#define COMP_OUTPOL_FLIP ((uint32_t)COMP_CTRL_POL)
#define COMP_OUTPOL_NFLIP ((uint32_t)0x00000000)
/** COMP subtract definition **/
#define COMP_SUB_MASK ((uint32_t)(~COMP_CTRL_CMPVOS))
#define COMP_SUB_NO ((uint32_t)0x00000000)
#define COMP_SUB_100mV ((uint32_t)COMP_CTRL_CMPVOS_0)
#define COMP_SUB_200mV ((uint32_t)COMP_CTRL_CMPVOS_1)
#define COMP_SUB_300mV ((uint32_t)(COMP_CTRL_CMPVOS_0 | COMP_CTRL_CMPVOS_1))
/** COMP non inverting input definition **/
#define COMP_INPSEL_MASK ((uint32_t)(~COMP_CTRL_INPSEL))
#define COMP_INPSEL_RES ((uint32_t)0x00000000)
/** comp inp sel **/
#define COMP_INPSEL_PB0 ((uint32_t)0x00000000)
#define COMP_INPSEL_PA5 ((uint32_t)0x00000004)
/** COMP inverting input definition **/
#define COMP_INMSEL_MASK ((uint32_t)(~COMP_CTRL_INMSEL))
#define COMP_INMSEL_RES ((uint32_t)0x00000000)
/** comp inm sel **/
#define COMP_INMSEL_PB1 ((uint32_t)0x00000000)
#define COMP_INMSEL_PA4 ((uint32_t)0x00000002)
/** COMP output connection definition **/
#define COMP_OUTSEL_MASK ((uint32_t)(~COMP_CTRL_OUTTRG))
#define COMP_OUTSEL_RES ((uint32_t)0x00000000)
/** comp out trig **/
#define COMP_OUTSEL_NO ((uint32_t)0x00000000)
#define COMP_OUTSEL_TIM1_BKIN ((uint32_t)0x00000080)
#define COMP_OUTSEL_TIM1_IC1 ((uint32_t)0x00000100)
#define COMP_OUTSEL_TIM1_OCREFCLEAR ((uint32_t)0x00000180)
#define COMP_OUTSEL_TIM3_IC1 ((uint32_t)0x00000200)
#define COMP_OUTSEL_TIM3_OCREFCLEAR ((uint32_t)0x00000280)
/** COMP switch definition **/
#define COMP_ENABLE ((uint32_t)COMP_CTRL_EN)
#define COMP_DISABLE ((uint32_t)(~COMP_CTRL_EN))
/** COMP filter definition **/
#define COMP_FILTER_SAMPW_MASK ((uint16_t)(~COMP_FILC_SAMPW)) /* Low filter sample window size. Number of samples to monitor is SAMPWIN+1. */
#define COMP_FILTER_THRESHOLD_MASK ((uint16_t)(~COMP_FILC_THRESH)) /* For proper operation, the value of THRESHOLD must be greater than SAMPWIN / 2. */
#define COMP_FILTER_ENABLE ((uint16_t)COMP_FILC_FILEN) /* Filter enable. */
#define COMP_FILTER_DISABLE ((uint16_t)(~COMP_FILC_FILEN)) /* Filter disable. */
/** COMP filter prescale definition **/
#define COMP_FILTER_CLKPSC_MASK ((uint16_t)(~COMP_FILP_CLKPSC)) /* Low filter sample clock prescale.Number of system clocks between samples = CLK_PRE_CYCLE + 1, e.g. */
/** COMP lock definition**/
#define COMP_LOCK_MSK ((uint16_t)(~COMP_LOCK_CMPLK)) /* COMP Lock bit */
#define COMP_LOCK ((uint16_t)COMP_LOCK_CMPLK) /* COMP Lock bit */
/** COMP interrupt enable definition **/
#define COMP_INTEN_MSK ((uint16_t)(~COMP_INTEN_CMPIEN))
#define COMP_INTEN ((uint16_t)COMP_INTEN_CMPIEN) /* This bit control Interrput enable of COMP. */
/** COMP interrupt status clear definition **/
#define COMP_INTS_CLEAR ((uint32_t)(~COMP_INTSTS_CMPIS))
/** COMP output status definition**/
#define COMP_OUT_MASK ((uint32_t)(~COMP_CTRL_OUT))
#define COMP_OUT ((uint32_t)COMP_CTRL_OUT)
/** COMP Driving Functions Declaration **/
void COMP_Reset(void);
void COMP_Initializes_Structure(COMP_InitType* COMP_initstruct);
void COMP_Filter_SampWindow_Config(uint8_t sampwin_value);
void COMP_Filter_Threshold_Config(uint8_t Threshold_value);
void COMP_Filter_Enable(void);
void COMP_Filter_Disable(void);
void COMP_Filter_Clock_Prescale_Config(uint16_t clkpsc_value);
void COMP_Blking_Soucre_Config(uint32_t blking_mode);
void COMP_Hysteresis_Level_Config(uint32_t hyst_mode);
void COMP_Output_Polarity_Config(uint32_t output_pol);
void COMP_InpSel_Config(uint32_t vpsel);
void COMP_InmSel_Config(uint32_t vpsel);
void COMP_Subtract_Level_Config(uint32_t sub_mode);
void COMP_Output_Trigger_Config(uint32_t outtrgsel);
void COMP_ON(void);
void COMP_OFF(void);
void COMP_Lock_Config(void);
void COMP_Interrupt_Enable(uint32_t inten);
void COMP_Interrupt_Disable(uint32_t inten);
uint8_t COMP_Interrupt_Status_Get(void);
void COMP_Interrupt_Status_Clear(void);
FlagStatus COMP_Output_Status_Get(void);
void COMP_Filter_Control_Config(uint32_t sw, uint8_t threshold , uint8_t sampwindow);
void COMP_Initializes(COMP_InitType* COMP_initstruct);
#ifdef __cplusplus
}
#endif
#endif /* __N32G003_COMP_H */

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/**
* Copyright (c) 2022, Nations Technologies Inc.
*
* All rights reserved.
*
* This software is the exclusive property of Nations Technologies Inc. (Hereinafter
* referred to as NATIONS). This software, and the product of NATIONS described herein
* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties
* of the People's Republic of China and other applicable jurisdictions worldwide.
*
* NATIONS does not grant any license under its patents, copyrights, trademarks, or other
* intellectual property rights. Names and brands of third party may be mentioned or referred
* thereto (if any) for identification purposes only.
*
* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and
* improvements to this software at any time without notice. Please contact NATIONS and obtain
* the latest version of this software before placing orders.
* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes
* no responsibility for the accuracy and reliability of this software.
*
* It is the responsibility of the user of this software to properly design, program, and test
* the functionality and safety of any application made of this information and any resulting product.
* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or
* consequential damages arising in any way out of the use of this software or the Product.
*
* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any
* malfunction or failure of which may cause loss of human life, bodily injury or severe property
* damage. Such applications are deemed, "Insecure Usage".
*
* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS
* harmless from and against all claims, costs, damages, and other liabilities, arising from or related
* to any customer's Insecure Usage.
* Any express or implied warranty with regard to this software or the Product, including,but not
* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement
* are disclaimed to the fullest extent permitted by law.
* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe
* or otherwise distribute this software for any purposes, in whole or in part.
*
* NATIONS products and technologies shall not be used for or incorporated into any products or systems
* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations.
* User shall comply with any applicable export control laws and regulations promulgated and administered by
* the governments of any countries asserting jurisdiction over the parties or transactions.
**/
/**
*\*\file n32g003_crc.h
*\*\author Nations
*\*\version v1.0.0
*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
*/
#ifndef __N32G003_CRC_H_
#define __N32G003_CRC_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "n32g003.h"
/*** CRC Structure Definition Start ***/
/*** CRC Structure Definition End ***/
/*** CRC Macro Definition Start ***/
/** CRC clear the CRC16 check value definition **/
#define CRC_CRC16_VALUE_CLEAR ((uint32_t)CRC16_CTRL_RESET)
#define CRC_CRC16_VALUE_NO_CLEAR ((uint32_t)CRC16_CTRL_NO_RESET)
/** CRC little-endian and big-endian definition **/
#define CRC_LITTLE_ENDIAN_ENABLE ((uint32_t)CRC16_CTRL_LITTLE) /* Set little-endian */
#define CRC_BIG_ENDIAN_ENABLE ((uint32_t)CRC16_CTRL_BIG) /* Set big-endian */
/*** CRC Macro Definition End ***/
/*** CRC Driving Functions Declaration ***/
uint16_t CRC16_Calculate(uint8_t data);
uint16_t CRC16_Buffer_Calculate(uint8_t p_buf[], uint32_t buf_len);
void CRC16_Set(uint8_t data);
uint16_t CRC16_Get(void);
void CRC16_Little_Endian_Format_Set(void);
void CRC16_Big_Endian_Format_Set(void);
void CRC16_Value_Clean_Enable(void);
void CRC16_Value_Clean_Disable(void);
void CRC_LRC_Set(uint8_t data);
uint8_t CRC_LRC_Get(void);
#ifdef __cplusplus
}
#endif
#endif /* __N32G003_CRC_H_ */

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/**
* Copyright (c) 2022, Nations Technologies Inc.
*
* All rights reserved.
*
* This software is the exclusive property of Nations Technologies Inc. (Hereinafter
* referred to as NATIONS). This software, and the product of NATIONS described herein
* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties
* of the People's Republic of China and other applicable jurisdictions worldwide.
*
* NATIONS does not grant any license under its patents, copyrights, trademarks, or other
* intellectual property rights. Names and brands of third party may be mentioned or referred
* thereto (if any) for identification purposes only.
*
* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and
* improvements to this software at any time without notice. Please contact NATIONS and obtain
* the latest version of this software before placing orders.
* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes
* no responsibility for the accuracy and reliability of this software.
*
* It is the responsibility of the user of this software to properly design, program, and test
* the functionality and safety of any application made of this information and any resulting product.
* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or
* consequential damages arising in any way out of the use of this software or the Product.
*
* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any
* malfunction or failure of which may cause loss of human life, bodily injury or severe property
* damage. Such applications are deemed, "Insecure Usage".
*
* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS
* harmless from and against all claims, costs, damages, and other liabilities, arising from or related
* to any customer's Insecure Usage.
* Any express or implied warranty with regard to this software or the Product, including,but not
* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement
* are disclaimed to the fullest extent permitted by law.
* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe
* or otherwise distribute this software for any purposes, in whole or in part.
*
* NATIONS products and technologies shall not be used for or incorporated into any products or systems
* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations.
* User shall comply with any applicable export control laws and regulations promulgated and administered by
* the governments of any countries asserting jurisdiction over the parties or transactions.
**/
/**
*\*\file n32g003_dbg.h
*\*\author Nations
*\*\version v1.0.0
*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
**/
#ifndef __N32G003_DBG_H__
#define __N32G003_DBG_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "n32g003.h"
void UCID_Get(uint8_t *UCIDbuf);
void UID_Get(uint8_t *UIDbuf);
void DBGMCU_ID_Get(uint8_t *DBGIDbuf);
#ifdef __cplusplus
}
#endif
#endif /* __N32G003_DBG_H__ */

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/**
* Copyright (c) 2022, Nations Technologies Inc.
*
* All rights reserved.
*
* This software is the exclusive property of Nations Technologies Inc. (Hereinafter
* referred to as NATIONS). This software, and the product of NATIONS described herein
* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties
* of the People's Republic of China and other applicable jurisdictions worldwide.
*
* NATIONS does not grant any license under its patents, copyrights, trademarks, or other
* intellectual property rights. Names and brands of third party may be mentioned or referred
* thereto (if any) for identification purposes only.
*
* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and
* improvements to this software at any time without notice. Please contact NATIONS and obtain
* the latest version of this software before placing orders.
* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes
* no responsibility for the accuracy and reliability of this software.
*
* It is the responsibility of the user of this software to properly design, program, and test
* the functionality and safety of any application made of this information and any resulting product.
* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or
* consequential damages arising in any way out of the use of this software or the Product.
*
* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any
* malfunction or failure of which may cause loss of human life, bodily injury or severe property
* damage. Such applications are deemed, "Insecure Usage".
*
* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS
* harmless from and against all claims, costs, damages, and other liabilities, arising from or related
* to any customer's Insecure Usage.
* Any express or implied warranty with regard to this software or the Product, including,but not
* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement
* are disclaimed to the fullest extent permitted by law.
* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe
* or otherwise distribute this software for any purposes, in whole or in part.
*
* NATIONS products and technologies shall not be used for or incorporated into any products or systems
* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations.
* User shall comply with any applicable export control laws and regulations promulgated and administered by
* the governments of any countries asserting jurisdiction over the parties or transactions.
**/
/***
*\*\file n32g003_exti.h
*\*\author Nations
*\*\version v1.0.0
*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
***/
#ifndef __N32G003_EXTI_H
#define __N32G003_EXTI_H
#ifdef __cplusplus
extern "C" {
#endif
#include "n32g003.h"
/*** EXTI Structure Definition Start ***/
/** EXTI mode enumeration **/
typedef enum
{
EXTI_Mode_Interrupt = 0x00,
EXTI_Mode_Event = 0x04
} EXTI_ModeType;
/** EXTI Trigger enumeration **/
typedef enum
{
EXTI_Trigger_Rising = 0x08,
EXTI_Trigger_Falling = 0x0C,
EXTI_Trigger_Rising_Falling = 0x10
} EXTI_TriggerType;
/** EXTI Init Structure definition **/
typedef struct
{
uint32_t EXTI_Line; /* Specifies the EXTI lines to be enabled or disabled. */
EXTI_ModeType EXTI_Mode; /* Specifies the mode for the EXTI lines. */
EXTI_TriggerType EXTI_Trigger; /* Specifies the trigger signal active edge for the EXTI lines. */
FunctionalState EXTI_LineCmd; /* Specifies the new state of the selected EXTI lines. */
} EXTI_InitType;
/*** EXTI Structure Definition End ***/
/*** EXTI Macro Definition Start ***/
/** EXTI_Lines **/
#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */
#define EXTI_LINE0 ((uint32_t)0x00001) /* External interrupt line 0 Connected to the PA0 */
#define EXTI_LINE1 ((uint32_t)0x00002) /* External interrupt line 1 Connected to the PA1 */
#define EXTI_LINE2 ((uint32_t)0x00004) /* External interrupt line 2 Connected to the PA2 */
#define EXTI_LINE3 ((uint32_t)0x00008) /* External interrupt line 3 Connected to the PA3 */
#define EXTI_LINE4 ((uint32_t)0x00010) /* External interrupt line 4 Connected to the PA4 */
#define EXTI_LINE5 ((uint32_t)0x00020) /* External interrupt line 5 Connected to the PA5 */
#define EXTI_LINE6 ((uint32_t)0x00040) /* External interrupt line 6 Connected to the PA6 */
#define EXTI_LINE7 ((uint32_t)0x00080) /* External interrupt line 7 Connected to the PA7 */
#define EXTI_LINE8 ((uint32_t)0x00100) /* External interrupt line 8 Connected to the PA8 */
#define EXTI_LINE9 ((uint32_t)0x00200) /* External interrupt line 9 Connected to the PA9 */
#define EXTI_LINE10 ((uint32_t)0x00400) /* External interrupt line 10 Connected to the PA10 */
#define EXTI_LINE11 ((uint32_t)0x00800) /* External interrupt line 11 Connected to the PA11 */
#define EXTI_LINE12 ((uint32_t)0x01000) /* External interrupt line 12 Connected to the PA12 */
#define EXTI_LINE13 ((uint32_t)0x02000) /* External interrupt line 13 Connected to the PA13 */
#define EXTI_LINE14 ((uint32_t)0x04000) /* External interrupt line 14 Connected to the PA14 */
#define EXTI_LINE15 ((uint32_t)0x08000) /* External interrupt line 15 Connected to the PA15 */
#define EXTI_LINE16 ((uint32_t)0x10000) /* External interrupt line 16 Connected to the PB0 */
#define EXTI_LINE17 ((uint32_t)0x20000) /* External interrupt line 17 Connected to the PB1 */
#define EXTI_LINE18 ((uint32_t)0x40000) /* External interrupt line 18 Connected to the PVD Output */
#define EXTI_LINE19 ((uint32_t)0x80000) /* External interrupt line 19 Connected to the TIM6 interrupt */
/*** EXTI Macro Definition End ***/
/** EXTI Driving Functions Declaration **/
void EXTI_Reset(void);
void EXTI_Peripheral_Initializes(EXTI_InitType* EXTI_InitStruct);
void EXTI_Work_Mode_Config(uint32_t exti_line,uint32_t exti_mode);
void EXTI_Trigger_Config(uint32_t exti_line,uint32_t exti_trigger);
void EXTI_LineCmd_Disable(uint32_t exti_line,uint32_t exti_linecmd,uint32_t exti_mode);
void EXTI_Structure_Initializes(EXTI_InitType* EXTI_InitStruct);
void EXTI_Software_Interrupt_Trigger(uint32_t exti_line);
FlagStatus EXTI_Flag_Status_Get(uint32_t exti_line);
void EXTI_Flag_Status_Clear(uint32_t exti_line);
ITStatus EXTI_Interrupt_Status_Get(uint32_t exti_line);
void EXTI_Interrupt_Status_Clear(uint32_t exti_line);
#ifdef __cplusplus
}
#endif
#endif /* __N32G003_EXTI_H__ */

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/**
* Copyright (c) 2022, Nations Technologies Inc.
*
* All rights reserved.
*
* This software is the exclusive property of Nations Technologies Inc. (Hereinafter
* referred to as NATIONS). This software, and the product of NATIONS described herein
* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties
* of the People's Republic of China and other applicable jurisdictions worldwide.
*
* NATIONS does not grant any license under its patents, copyrights, trademarks, or other
* intellectual property rights. Names and brands of third party may be mentioned or referred
* thereto (if any) for identification purposes only.
*
* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and
* improvements to this software at any time without notice. Please contact NATIONS and obtain
* the latest version of this software before placing orders.
* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes
* no responsibility for the accuracy and reliability of this software.
*
* It is the responsibility of the user of this software to properly design, program, and test
* the functionality and safety of any application made of this information and any resulting product.
* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or
* consequential damages arising in any way out of the use of this software or the Product.
*
* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any
* malfunction or failure of which may cause loss of human life, bodily injury or severe property
* damage. Such applications are deemed, "Insecure Usage".
*
* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS
* harmless from and against all claims, costs, damages, and other liabilities, arising from or related
* to any customer's Insecure Usage.
* Any express or implied warranty with regard to this software or the Product, including,but not
* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement
* are disclaimed to the fullest extent permitted by law.
* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe
* or otherwise distribute this software for any purposes, in whole or in part.
*
* NATIONS products and technologies shall not be used for or incorporated into any products or systems
* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations.
* User shall comply with any applicable export control laws and regulations promulgated and administered by
* the governments of any countries asserting jurisdiction over the parties or transactions.
**/
/**
*\*\file n32g003_flash.h
*\*\author Nations
*\*\version v1.0.0
*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
**/
#ifndef __N32G003_FLASH_H
#define __N32G003_FLASH_H
#ifdef __cplusplus
extern "C" {
#endif
#include "n32g003.h"
/** FLASH Status **/
typedef enum
{
FLASH_BUSY = 1,
FLASH_ERR_PG,
FLASH_ERR_WRP,
FLASH_EOP,
FLASH_ERR_RDP2,
FLASH_ERR_ADD,
FLASH_TIMEOUT
}FLASH_STS;
/** Flash Access Control Register bits **/
#define FLASH_PRFTBS_MSK ((uint32_t)FLASH_AC_PRFTBFSTS)
/** Prefetch_Buffer_Enable_Disable **/
#define FLASH_PREFETCHBUF_EN ((uint32_t)FLASH_AC_PRFTBFEN) /* FLASH Prefetch Buffer Enable */
#define FLASH_PREFETCHBUF_DIS (~((uint32_t)FLASH_AC_PRFTBFEN)) /* FLASH Prefetch Buffer Disable */
/** Flash_Latency **/
#define FLASH_LATENCY_0 ((uint32_t)FLASH_AC_LATENCY_0) /* FLASH Zero Latency cycle */
#define FLASH_LATENCY_1 ((uint32_t)FLASH_AC_LATENCY_1) /* FLASH One Latency cycle */
#define FLASH_LATENCY_MASK ((uint32_t)FLASH_AC_LATENCY)
/** FLASH Keys **/
#define FLASH_KEY1 ((uint32_t)0x45670123)
#define FLASH_KEY2 ((uint32_t)0xCDEF89AB)
/** Flash Control Register bits **/
#define FLASH_CTRL_SET_PG ((uint32_t)FLASH_CTRL_PG)
#define FLASH_CTRL_RESET_PG (~((uint32_t)FLASH_CTRL_PG))
#define FLASH_CTRL_SET_PER ((uint32_t)FLASH_CTRL_PER)
#define FLASH_CTRL_RESET_PER (~((uint32_t)FLASH_CTRL_PER))
#define FLASH_CTRL_SET_MER ((uint32_t)FLASH_CTRL_MER)
#define FLASH_CTRL_RESET_MER (~((uint32_t)FLASH_CTRL_MER))
#define FLASH_CTRL_SET_OPTPG ((uint32_t)FLASH_CTRL_OPTPG)
#define FLASH_CTRL_RESET_OPTPG (~((uint32_t)FLASH_CTRL_OPTPG))
#define FLASH_CTRL_SET_OPTER ((uint32_t)FLASH_CTRL_OPTER)
#define FLASH_CTRL_RESET_OPTER (~((uint32_t)FLASH_CTRL_OPTER))
#define FLASH_CTRL_SET_MMER ((uint32_t)FLASH_CTRL_MMER)
#define FLASH_CTRL_RESET_MMER (~((uint32_t)FLASH_CTRL_MMER))
#define FLASH_CTRL_SET_START ((uint32_t)FLASH_CTRL_START)
#define FLASH_CTRL_SET_LOCK ((uint32_t)FLASH_CTRL_LOCK)
#define FLASH_CTRL_SET_OPTWE ((uint32_t)FLASH_CTRL_OPTWRE)
/** Option byte **/
#define FLASH_L1_RDP_KEY ((uint32_t)0xFFFF00A5)
#define FLASH_L2_RDP_KEY ((uint32_t)0xFFFF33CC)
#define FLASH_OB_DATA0_MASK (FLASH_OB_DATA0_MSK)
#define FLASH_OB_DATA1_MASK (FLASH_OB_DATA1_MSK)
/** OB Register related definition**/
#define FLASH_USER_MASK (FLASH_USER_USER)
#define FLASH_RDP1_MASK (FLASH_RDP_RDP1)
#define FLASH_RDP2_MASK ((uint32_t)0xFF00FFFF)
#define FLASH_FLAG_OBERR (FLASH_OB_OBERR)
/** FLASH Mask **/
#define FLASH_RDPRTL1_MSK ((uint32_t)FLASH_OB_RDPRT1)
#define FLASH_RDPRTL2_MSK ((uint32_t)FLASH_OB_RDPRT2)
#define FLASH_OB_USER_MSK ((uint32_t)FLASH_OB_USER)
/** Option_Bytes_RDPx **/
#define FLASH_OB_RDP1_ENABLE ((uint8_t)0x00) /* Enable RDP1 */
#define FLASH_OB_RDP1_DISABLE ((uint8_t)0xA5) /* DISABLE RDP1 */
#define FLASH_OB_RDP2_ENABLE ((uint8_t)0xCC) /* Enable RDP2 */
#define FLASH_OB_RDP2_DISABLE ((uint8_t)0x00) /* Disable RDP2 */
/** Option_Bytes_IWatchdog **/
#define FLASH_OB_IWDG_SW ((uint16_t)0x0001) /* Software IWDG selected */
#define FLASH_OB_IWDG_HW ((uint16_t)0x0000) /* Hardware IWDG selected */
/** Option_Bytes_nRST_STOP **/
#define FLASH_OB_STOP_NORST ((uint16_t)0x0002) /* No reset generated when entering in STOP */
#define FLASH_OB_STOP_RST ((uint16_t)0x0000) /* Reset generated when entering in STOP */
/** Option_Bytes_nRST_PD **/
#define FLASH_OB_PD_NORST ((uint16_t)0x0004) /* No reset generated when entering in PD */
#define FLASH_OB_PD_RST ((uint16_t)0x0000) /* Reset generated when entering in PD */
/** Option_Bytes_LOCK_BOOT **/
#define FLASH_OB_LOCK_BOOT ((uint16_t)0x0008) /* First 3KB FLASH LOCK*/
#define FLASH_OB_NOLOCK_BOOT ((uint16_t)0x0000) /* First 3KB FLASH NOLOCK */
/** Option_Bytes_PA0_IO **/
#define FLASH_OB_PA0_IO ((uint16_t)0x0000) /* PA0 is general pin */
#define FLASH_OB_PA0_NRST ((uint16_t)0x0010) /* PA0 is RESET pin */
/** Option_Bytes_USER_LVREN **/
#define FLASH_OB_USER_LVR_ENABLE ((uint16_t)0x0000) /* LVR enable */
#define FLASH_OB_USER_LVR_DISABLE ((uint16_t)0x0010) /* LVR disable */
/** Option_Bytes_USER_LVRFIL **/
#define FLASH_OB_USER_LVRFIL_ENABLE ((uint16_t)0x0000) /* LVR filter enable */
#define FLASH_OB_USER_LVRFIL_DISABLE ((uint16_t)0x0020) /* LVR filter disable */
/** Option_Bytes_USER_LVRFIL **/
#define FLASH_OB_USER_LVRRST_ENABLE ((uint16_t)0x0000) /* LVR reset enable */
#define FLASH_OB_USER_LVRRST_DISABLE ((uint16_t)0x0040) /* LVR reset disable */
/** FLASH USER Mask **/
#define FLASH_USER_LVRCNT_MSK ((uint32_t)FLASH_USER_LVRCNT)
#define FLASH_USER_LVRLS_MSK ((uint32_t)FLASH_USER_LVRLS)
#define FLASH_USER_POR_DELAY_MSK ((uint32_t)FLASH_USER_POR_DELAY)
#define FLASH_USER_RDP_OFFSET (REG_BIT16_OFFSET)
#define FLASH_OB_TO_USER_OFFSET (REG_BIT14_OFFSET)
#define FLASH_OB_OFFSET (REG_BIT2_OFFSET)
#define FLASH_DATA0_DATA1_OFFSET (REG_BIT16_OFFSET)
#define FLASH_USER2_USER3_OFFSET (REG_BIT16_OFFSET)
#define FLASH_OB_DATA0_OFFSET (REG_BIT10_OFFSET)
#define FLASH_OB_DATA1_OFFSET (REG_BIT18_OFFSET)
#define FLASH_USER3_OFFSET (REG_BIT8_OFFSET)
#define FLASH_USER4_OFFSET (REG_BIT16_OFFSET)
/** Delay definition **/
#define ERASE_TIMEOUT ((uint32_t)0x000B0000)
#define PROGRAM_TIMEOUT ((uint32_t)0x00002000)
#define FLASH_WORD_LENGTH ((uint32_t)0x00000003)
/** FLASH_Interrupts **/
#define FLASH_INT_ERROR ((uint32_t)FLASH_CTRL_ERRITE) /* PGERR WRPERR ERROR error interrupt source */
#define FLASH_INT_EOP ((uint32_t)FLASH_CTRL_EOPITE) /* End of FLASH Operation Interrupt source */
/** FLASH_Flags **/
#define FLASH_FLAG_BUSY ((uint32_t)FLASH_STS_BUSY) /* FLASH Busy flag */
#define FLASH_FLAG_PGERR ((uint32_t)FLASH_STS_PGERR) /* FLASH Program error flag */
#define FLASH_FLAG_WRPERR ((uint32_t)FLASH_STS_WRPERR) /* FLASH Write protected error flag */
#define FLASH_FLAG_EOP ((uint32_t)FLASH_STS_EOP) /* FLASH End of Operation flag */
#define FLASH_FLAG_SPERR ((uint32_t)FLASH_STS_SPRERR) /* FLASH Special Pattern Read error */
#define FLASH_FLAG_CFGERR ((uint32_t)FLASH_STS_CFGERR) /* FLASH Configuration registers error when checking */
/** FLASH_STS_CLRFLAG **/
#define FLASH_STS_CLRFLAG (FLASH_FLAG_PGERR | FLASH_FLAG_WRPERR | FLASH_FLAG_EOP)
/** FLASH_VTOR_CLRFLAG **/
#define FLASH_VTOR_ENABLE ((uint32_t)FLASH_VTOR_EN) /* FLASH Busy flag */
#define FLASH_VTOR_DISABLE ((uint32_t)0x00000000) /* FLASH Busy flag */
/** Delay definition **/
#define ERASE_TIMEOUT ((uint32_t)0x000B0000)
#define PROGRAM_TIMEOUT ((uint32_t)0x00002000)
#define FLASH_WORD_LENGTH ((uint32_t)0x00000003)
/** Functions used for N32G003 devices **/
void FLASH_Latency_Set(uint32_t flash_latency);
uint8_t FLASH_Latency_Get(void);
void FLASH_Prefetch_Buffer_Enable(void);
void FLASH_Prefetch_Buffer_Disable(void);
void FLASH_Unlock(void);
void FLASH_Lock(void);
void Option_Bytes_Unlock(void);
void Option_Bytes_Lock(void);
FlagStatus Option_Bytes_Lock_Status_Get(void);
FLASH_STS FLASH_One_Page_Erase(uint32_t page_address);
FLASH_STS FLASH_Mass_Erase(void);
FLASH_STS FLASH_48Page_Mass_Erase(void);
FLASH_STS FLASH_Word_Program(uint32_t address, uint32_t data);
FLASH_STS FLASH_Option_Bytes_Erase(void);
FLASH_STS FLASH_Option_Bytes_User_RDP1_Program(uint8_t option_byte_rdp1, uint16_t option_byte_iwdg, \
uint16_t option_byte_stop, uint16_t option_byte_PD, \
uint16_t option_byte_lock_boot, uint16_t option_byte_PA0_NRST);
FLASH_STS FLASH_Option_Bytes_DATA_Program(uint8_t option_byte_data0,uint8_t option_byte_data1);
FLASH_STS FLASH_Option_Bytes_User2_User3_Program(uint8_t option_byte_user2,uint8_t option_byte_LVR_cnt, \
uint8_t option_byte_LVR,uint8_t option_byte_LVR_filter,uint8_t option_byte_LVR_reset);
FLASH_STS FLASH_Option_Bytes_User4_RDP2_Program(uint8_t option_byte_rdp2,uint8_t option_byte_user4);
FLASH_STS FLASH_Read_Out_Protection_L1_Enable(void);
FLASH_STS FLASH_Read_Out_Protection_L1_Disable(void);
FLASH_STS FLASH_Read_Out_Protection_L2_Enable(void);
FlagStatus FLASH_Option_Bytes_User_Get(uint32_t option_byte_bit);
uint32_t FLASH_Option_Bytes_User2_Get(void);
uint32_t FLASH_User_LVRLS_Get(void);
FlagStatus FLASH_Option_Bytes_User3_Get(uint32_t option_byte_bit);
uint32_t FLASH_Option_Bytes_User4_Get(void);
FlagStatus FLASH_Read_Out_Protection_Status_Get(void);
FlagStatus FLASH_Read_Out_Protection_L2_Status_Get(void);
FlagStatus FLASH_Prefetch_Buffer_Status_Get(void);
void FLASH_Interrupt_Enable(uint32_t flash_interrupts);
void FLASH_Interrupt_Disable(uint32_t flash_interrupts);
FlagStatus FLASH_Flag_Status_Get(uint32_t flash_flag);
FlagStatus FLASH_Option_Bytes_Flag_Get(uint32_t flash_flag);
void FLASH_Flag_Status_Clear(uint32_t flash_flag);
FLASH_STS FLASH_Status_Get(void);
FLASH_STS FLASH_Last_Operation_Wait(uint32_t timeout);
void FLASH_VTOR_Address_Set(uint32_t VTOR_address,uint32_t VTOR_cmd);
#ifdef __cplusplus
}
#endif
#endif /* __N32G003_FLASH_H */

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/**
* Copyright (c) 2022, Nations Technologies Inc.
*
* All rights reserved.
*
* This software is the exclusive property of Nations Technologies Inc. (Hereinafter
* referred to as NATIONS). This software, and the product of NATIONS described herein
* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties
* of the People's Republic of China and other applicable jurisdictions worldwide.
*
* NATIONS does not grant any license under its patents, copyrights, trademarks, or other
* intellectual property rights. Names and brands of third party may be mentioned or referred
* thereto (if any) for identification purposes only.
*
* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and
* improvements to this software at any time without notice. Please contact NATIONS and obtain
* the latest version of this software before placing orders.
* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes
* no responsibility for the accuracy and reliability of this software.
*
* It is the responsibility of the user of this software to properly design, program, and test
* the functionality and safety of any application made of this information and any resulting product.
* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or
* consequential damages arising in any way out of the use of this software or the Product.
*
* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any
* malfunction or failure of which may cause loss of human life, bodily injury or severe property
* damage. Such applications are deemed, "Insecure Usage".
*
* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS
* harmless from and against all claims, costs, damages, and other liabilities, arising from or related
* to any customer's Insecure Usage.
* Any express or implied warranty with regard to this software or the Product, including,but not
* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement
* are disclaimed to the fullest extent permitted by law.
* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe
* or otherwise distribute this software for any purposes, in whole or in part.
*
* NATIONS products and technologies shall not be used for or incorporated into any products or systems
* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations.
* User shall comply with any applicable export control laws and regulations promulgated and administered by
* the governments of any countries asserting jurisdiction over the parties or transactions.
**/
/**
*\*\file n32g003_gpio.h
*\*\author Nations
*\*\version v1.0.0
*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
**/
#ifndef __N32G003_GPIO_H__
#define __N32G003_GPIO_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "n32g003.h"
#define GPIOA_POSITION1 (8U)
#define GPIOA_POSITION2 (9U)
#define GPIO_AF_MODE ((uint32_t)GPIO_PMODE0_2)
#define GPIO_ANALOG_MODE ((uint32_t)GPIO_PMODE0_Msk)
#define GPIO_PU_MODE ((uint32_t)GPIO_PUPD0_1)
#define GPIO_PD_MODE ((uint32_t)GPIO_PUPD0_2)
#define GPIO_SR_SLOW (GPIO_SR_SR0)
#define GPIO_LOW_DRIVER (GPIO_DS_DS0)
#define GPIO_OUTPUT_TYPE_MASK ((uint32_t)0x00000010)
#define GPIO_SET_PMODE_MASK ((uint32_t)0x00000003)
#define GPIO_AF_MASK ((uint32_t)0x0000000F)
#define GPIO_PMODE_MASK ((uint32_t)GPIO_PMODE0_Msk)
#define GPIO_PUPD_MASK ((uint32_t)GPIO_PUPD0_Msk)
#define GPIO_POTYPE_MASK (GPIO_POTYPE_POT0)
#define GPIO_SR_MASK (GPIO_SR_SR0)
#define GPIO_DS_MASK (GPIO_DS_DS0)
#define GPIO_PLOCKK_MASK (GPIO_PLOCK_PLOCKK)
#define AF_SELECTION_MASK (0x08)
#define AF_WRITE_POSITION_MASK (0x07U)
#define IO_POSITION_MASK (1U)
#define MULTIPLIER_FACTOR_2 (2U)
#define MULTIPLIER_FACTOR_4 (4U)
#define SHIFT_POTYPE (REG_BIT4_OFFSET)
#define SHIFT_PBSC_HIGH16 (REG_BIT16_OFFSET)
#define GPIO_GET_PERIPH(INDEX) (((INDEX)==((uint8_t)0x00))? GPIOA : GPIOB )
/**
*\*\name GPIO_ModeType.
*\*\fun GPIO mode definition.
*\*\ Values convention: 0x00YZ
*\*\ - Y : Output type (Push Pull or Open Drain)
*\*\ - Z : IO Direction mode (Input, Output, Alternate or Analog)
*/
#define GPIO_MODE_INPUT ((uint32_t)0x00000000U) /* Input Floating Mode */
#define GPIO_MODE_OUT_PP ((uint32_t)0x00000001U) /* Output Push Pull Mode */
#define GPIO_MODE_OUT_OD ((uint32_t)0x00000011U) /* Output Open Drain Mode */
#define GPIO_MODE_AF_PP ((uint32_t)0x00000002U) /* Alternate Function Push Pull Mode */
#define GPIO_MODE_AF_OD ((uint32_t)0x00000012U) /* Alternate Function Open Drain Mode */
#define GPIO_MODE_ANALOG ((uint32_t)0x00000003U) /* Analog Mode */
/** GPIO Pull-Up or Pull-Down Activation **/
#define GPIO_NO_PULL ((uint32_t)GPIO_PUPD0_0) /* No Pull-up or Pull-down activation */
#define GPIO_PULL_UP ((uint32_t)GPIO_PUPD0_1) /* Pull-up activation */
#define GPIO_PULL_DOWN ((uint32_t)GPIO_PUPD0_2) /* Pull-down activation */
/** slew rate config **/
#define GPIO_SLEW_RATE_FAST ((uint32_t)0x00000000U)
#define GPIO_SLEW_RATE_SLOW ((uint32_t)0x00000001U)
/** driver strength config **/
#define GPIO_HIGH_DREIVE ((uint32_t)0x00000000U)
#define GPIO_LOW_DREIVE ((uint32_t)0x00000001U)
/** GPIO Init Structure Definition **/
typedef struct
{
uint32_t Pin; /* Specifies the GPIO pins to be configured. */
uint32_t GPIO_Mode; /* Specifies the operating mode for the selected pins. */
uint32_t GPIO_Pull; /* Specifies the Pull-up or Pull-Down activation for the selected pins. */
uint32_t GPIO_Slew_Rate; /* Specify the reverse speed for the selected pins. */
uint32_t GPIO_Current; /* Driving drive capability of the select pins. */
uint32_t GPIO_Alternate; /* Peripheral to be connected to the selected pins. */
}GPIO_InitType;
/** Bit_SET and Bit_RESET enumeration **/
typedef enum
{
PIN_RESET = 0,
PIN_SET
}Bit_CommandType;
/** GPIO_pins_define **/
#define GPIO_PIN_0 ((uint16_t)0x0001U) /* Pin 0 selected */
#define GPIO_PIN_1 ((uint16_t)0x0002U) /* Pin 1 selected */
#define GPIO_PIN_2 ((uint16_t)0x0004U) /* Pin 2 selected */
#define GPIO_PIN_3 ((uint16_t)0x0008U) /* Pin 3 selected */
#define GPIO_PIN_4 ((uint16_t)0x0010U) /* Pin 4 selected */
#define GPIO_PIN_5 ((uint16_t)0x0020U) /* Pin 5 selected */
#define GPIO_PIN_6 ((uint16_t)0x0040U) /* Pin 6 selected */
#define GPIO_PIN_7 ((uint16_t)0x0080U) /* Pin 7 selected */
#define GPIO_PIN_8 ((uint16_t)0x0100U) /* Pin 8 selected */
#define GPIO_PIN_9 ((uint16_t)0x0200U) /* Pin 9 selected */
#define GPIO_PIN_10 ((uint16_t)0x0400U) /* Pin 10 selected */
#define GPIO_PIN_11 ((uint16_t)0x0800U) /* Pin 11 selected */
#define GPIO_PIN_12 ((uint16_t)0x1000U) /* Pin 12 selected */
#define GPIO_PIN_13 ((uint16_t)0x2000U) /* Pin 13 selected */
#define GPIO_PIN_14 ((uint16_t)0x4000U) /* Pin 14 selected */
#define GPIO_PIN_15 ((uint16_t)0x8000U) /* Pin 15 selected */
#define GPIO_PIN_ALL ((uint16_t)0xFFFFU) /* All pins selected */
/** GPIO Port Sources **/
#define GPIOA_PORT_SOURCE ((uint8_t)0x00)
#define GPIOB_PORT_SOURCE ((uint8_t)0x01)
/** GPIO Pin Sources **/
#define GPIO_PIN_SOURCE0 ((uint8_t)0x00)
#define GPIO_PIN_SOURCE1 ((uint8_t)0x01)
#define GPIO_PIN_SOURCE2 ((uint8_t)0x02)
#define GPIO_PIN_SOURCE3 ((uint8_t)0x03)
#define GPIO_PIN_SOURCE4 ((uint8_t)0x04)
#define GPIO_PIN_SOURCE5 ((uint8_t)0x05)
#define GPIO_PIN_SOURCE6 ((uint8_t)0x06)
#define GPIO_PIN_SOURCE7 ((uint8_t)0x07)
#define GPIO_PIN_SOURCE8 ((uint8_t)0x08)
#define GPIO_PIN_SOURCE9 ((uint8_t)0x09)
#define GPIO_PIN_SOURCE10 ((uint8_t)0x0A)
#define GPIO_PIN_SOURCE11 ((uint8_t)0x0B)
#define GPIO_PIN_SOURCE12 ((uint8_t)0x0C)
#define GPIO_PIN_SOURCE13 ((uint8_t)0x0D)
#define GPIO_PIN_SOURCE14 ((uint8_t)0x0E)
#define GPIO_PIN_SOURCE15 ((uint8_t)0x0F)
/** EXTI line and GPIO sources **/
#define AFIO_ADC_TRIG_PA0 ((uint8_t)0x00) /* PA0 */
#define AFIO_ADC_TRIG_PA1 ((uint8_t)0x01) /* PA1 */
#define AFIO_ADC_TRIG_PA2 ((uint8_t)0x02) /* PA2 */
#define AFIO_ADC_TRIG_PA3 ((uint8_t)0x03) /* PA3 */
#define AFIO_ADC_TRIG_PA4 ((uint8_t)0x04) /* PA4 */
#define AFIO_ADC_TRIG_PA5 ((uint8_t)0x05) /* PA5 */
#define AFIO_ADC_TRIG_PA6 ((uint8_t)0x06) /* PA6 */
#define AFIO_ADC_TRIG_PA7 ((uint8_t)0x07) /* PA7 */
#define AFIO_ADC_TRIG_PA8 ((uint8_t)0x08) /* PA8 */
#define AFIO_ADC_TRIG_PA9 ((uint8_t)0x09) /* PA9 */
#define AFIO_ADC_TRIG_PA10 ((uint8_t)0x0A) /* PA10 */
#define AFIO_ADC_TRIG_PA11 ((uint8_t)0x0B) /* PA11 */
#define AFIO_ADC_TRIG_PA12 ((uint8_t)0x0C) /* PA12 */
#define AFIO_ADC_TRIG_PA13 ((uint8_t)0x0D) /* PA13 */
#define AFIO_ADC_TRIG_PA14 ((uint8_t)0x0E) /* PA14 */
#define AFIO_ADC_TRIG_PA15 ((uint8_t)0x0F) /* PA15 */
#define AFIO_ADC_TRIG_PB0 ((uint8_t)0x10) /* PB0 */
#define AFIO_ADC_TRIG_PB1 ((uint8_t)0x11) /* PB1 */
/** GPIOx_Alternate_function_selection Alternate function selection **/
/** Alternate function AF0 **/
#define ALTERNATE_FUN_0 ((uint8_t)0x00U)
#define GPIO_AF0_SWDIO (ALTERNATE_FUN_0) /* SWDIO Alternate Function mapping */
#define GPIO_AF0_SWCLK (ALTERNATE_FUN_0) /* SWCLK Alternate Function mapping */
#define GPIO_AF0_TIM1 (ALTERNATE_FUN_0) /* TIM1 Alternate Function mapping */
#define GPIO_AF0_TIM3 (ALTERNATE_FUN_0) /* TIM3 Alternate Function mapping */
#define GPIO_AF0_SPI (ALTERNATE_FUN_0) /* SPI Alternate Function mapping */
/** Alternate function AF1 **/
#define ALTERNATE_FUN_1 ((uint8_t)0x01U)
#define GPIO_AF1_UART2 (ALTERNATE_FUN_1) /* UART2 Alternate Function mapping */
#define GPIO_AF1_TIM3 (ALTERNATE_FUN_1) /* TIM3 Alternate Function mapping */
/** Alternate function AF2 **/
#define ALTERNATE_FUN_2 ((uint8_t)0x02U)
#define GPIO_AF2_UART1 (ALTERNATE_FUN_2) /* UART1 Alternate Function mapping */
#define GPIO_AF2_TIM1 (ALTERNATE_FUN_2) /* TIM1 Alternate Function mapping */
#define GPIO_AF2_TIM3 (ALTERNATE_FUN_2) /* TIM3 Alternate Function mapping */
/** Alternate function AF3 **/
#define ALTERNATE_FUN_3 ((uint8_t)0x03U)
#define GPIO_AF3_EVENTOUT (ALTERNATE_FUN_3) /* EVENTOUT Alternate Function mapping */
#define GPIO_AF3_TIM1 (ALTERNATE_FUN_3) /* TIM1 Alternate Function mapping */
#define GPIO_AF3_COMP (ALTERNATE_FUN_3) /* COMP Alternate Function mapping */
/** Alternate function AF4 **/
#define ALTERNATE_FUN_4 ((uint8_t)0x04U)
#define GPIO_AF4_TIM1 (ALTERNATE_FUN_4) /* TIM1 Alternate Function mapping */
/** Alternate function AF5 **/
#define ALTERNATE_FUN_5 ((uint8_t)0x05U)
#define GPIO_AF5_UART1 (ALTERNATE_FUN_5) /* UART1 Alternate Function mapping */
#define GPIO_AF5_TIM1 (ALTERNATE_FUN_5) /* TIM1 Alternate Function mapping */
#define GPIO_AF5_SPI (ALTERNATE_FUN_5) /* SPI Alternate Function mapping */
/** Alternate function AF6 **/
#define ALTERNATE_FUN_6 ((uint8_t)0x06U)
#define GPIO_AF6_SPI (ALTERNATE_FUN_6) /* SPI Alternate Function mapping */
#define GPIO_AF6_I2C (ALTERNATE_FUN_6) /* I2C Alternate Function mapping */
#define GPIO_AF6_TIM3 (ALTERNATE_FUN_6) /* TIM3 Alternate Function mapping */
#define GPIO_AF6_UART2 (ALTERNATE_FUN_6) /* UART2 Alternate Function mapping */
#define GPIO_AF6_MCO (ALTERNATE_FUN_6) /* MCO Alternate Function mapping */
/** Alternate function AF7 **/
#define ALTERNATE_FUN_7 ((uint8_t)0x07U)
#define GPIO_AF7_BEEPER (ALTERNATE_FUN_7) /* BEEPER Alternate Function mapping */
/** Alternate function AF8 **/
#define ALTERNATE_FUN_8 ((uint8_t)0x08U)
#define GPIO_AF8_UART2 (ALTERNATE_FUN_8) /* UART2 Alternate Function mapping */
/** Alternate function AF15 **/
#define ALTERNATE_FUN_15 ((uint8_t)0x0FU) /* NON Alternate Function mapping */
#define GPIO_NO_AF (ALTERNATE_FUN_15)
/** SPI mode definition in AFIO register **/
#define AFIO_SPI_NSS ((uint32_t)AFIO_CFG_SPI_NSS)
#define AFIO_SPI_NSS_HIGH_IMPEDANCE (0x0UL)
#define AFIO_SPI_NSS_High_LEVEL (0x1UL)
/** TIM3_CH2 internal remap definition in AFIO register **/
#define AFIO_TIM3CH2_MAP ((uint32_t)AFIO_CFG_TIM3CH2_MAP)
#define TIM3CH2_TO_PORT (0x0UL)
#define TIM3CH2_TO_LSI (0x1UL)
/** GPIO_Exported_Functions **/
void GPIO_Reset(GPIO_Module* GPIOx);
void GPIO_Alternate_Function_Reset(void);
void GPIOA_Pin_Reset(uint16_t pin);
void GPIOB_Pin_Reset(uint16_t pin);
void GPIO_Alternate_Set(GPIO_Module* GPIOx, uint32_t alternate, uint32_t position);
void GPIO_Mode_Set(GPIO_Module* GPIOx, uint32_t mode, uint32_t position);
void GPIO_Pull_Set(GPIO_Module* GPIOx, uint32_t pull, uint32_t position);
void GPIO_SlewRate_Set(GPIO_Module* GPIOx, uint32_t slew_rate, uint32_t position);
void GPIO_Driver_Set(GPIO_Module* GPIOx, uint32_t current, uint32_t position);
void GPIO_Peripheral_Initialize(GPIO_Module* GPIOx, GPIO_InitType* GPIO_InitStructure);
void GPIO_Structure_Initialize(GPIO_InitType* GPIO_InitStruct);
uint8_t GPIO_Input_Pin_Data_Get(GPIO_Module* GPIOx, uint16_t pin);
uint16_t GPIO_Input_Data_Get(GPIO_Module* GPIOx);
uint8_t GPIO_Output_Pin_Data_Get(GPIO_Module* GPIOx, uint16_t pin);
uint16_t GPIO_Output_Data_Get(GPIO_Module* GPIOx);
void GPIO_Pins_Set(GPIO_Module* GPIOx, uint16_t pin);
void GPIO_Pins_Reset(GPIO_Module* GPIOx, uint16_t pin);
void GPIO_PBSC_Pins_Reset(GPIO_Module* GPIOx, uint16_t pin);
void GPIO_PBC_Pins_Reset(GPIO_Module* GPIOx, uint16_t pin);
void GPIO_Write(GPIO_Module* GPIOx, uint16_t data_value);
void GPIO_Pin_Toggle(GPIO_Module* GPIOx, uint16_t pin);
void GPIO_Pin_Lock_Set(GPIO_Module* GPIOx, uint16_t pin);
void GPIO_Pin_Remap_Set(uint8_t port_source, uint8_t pin_source, uint32_t alternate_function);
void AFIO_ADC_External_Trigger_Set(uint8_t ADC_trigger);
void AFIO_SPI_NSS_Mode_Set(uint32_t SPI_NSS_mode);
void AFIO_TIM3CH2_Remap(uint32_t TIM3CH2_remap);
#ifdef __cplusplus
}
#endif
#endif /* __N32G003_GPIO_H__ */

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/**
* Copyright (c) 2022, Nations Technologies Inc.
*
* All rights reserved.
*
* This software is the exclusive property of Nations Technologies Inc. (Hereinafter
* referred to as NATIONS). This software, and the product of NATIONS described herein
* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties
* of the People's Republic of China and other applicable jurisdictions worldwide.
*
* NATIONS does not grant any license under its patents, copyrights, trademarks, or other
* intellectual property rights. Names and brands of third party may be mentioned or referred
* thereto (if any) for identification purposes only.
*
* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and
* improvements to this software at any time without notice. Please contact NATIONS and obtain
* the latest version of this software before placing orders.
* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes
* no responsibility for the accuracy and reliability of this software.
*
* It is the responsibility of the user of this software to properly design, program, and test
* the functionality and safety of any application made of this information and any resulting product.
* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or
* consequential damages arising in any way out of the use of this software or the Product.
*
* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any
* malfunction or failure of which may cause loss of human life, bodily injury or severe property
* damage. Such applications are deemed, "Insecure Usage".
*
* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS
* harmless from and against all claims, costs, damages, and other liabilities, arising from or related
* to any customer's Insecure Usage.
* Any express or implied warranty with regard to this software or the Product, including,but not
* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement
* are disclaimed to the fullest extent permitted by law.
* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe
* or otherwise distribute this software for any purposes, in whole or in part.
*
* NATIONS products and technologies shall not be used for or incorporated into any products or systems
* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations.
* User shall comply with any applicable export control laws and regulations promulgated and administered by
* the governments of any countries asserting jurisdiction over the parties or transactions.
**/
/**
*\*\file n32g003_i2c.h
*\*\author Nations
*\*\version v1.0.0
*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
**/
#ifndef __N32G003_I2C_H_
#define __N32G003_I2C_H_
#ifdef __cplusplus
extern "C"
{
#endif
#include "n32g003.h"
/** N32G003_StdPeriph_Driver
*
*/
/** I2C Init structure definition **/
typedef struct
{
uint32_t ClkSpeed; /* Specifies the clock frequency. */
uint16_t DutyCycle; /* Specifies the I2C duty cycle. */
uint16_t OwnAddr1; /* Specifies the first device own address. */
uint16_t AckEnable; /* Enables or disables the acknowledgement. */
uint16_t AddrMode; /* Specifies if 7-bit or 10-bit address is acknowledged. */
} I2C_InitType;
#define APB_FREQ_MAX_VALUE (48) /*48M*/
#define CLK_SPEED_100K (100000)
#define CLK_SPEED_400K (400000)
#define CLK_SPEED_1M (1000000)
#define SM_CLKCTRL_LOW_LIMIT (0x04)
#define FM_CLKCTRL_LOW_LIMIT (0x01)
#define SM_TRISE_100K (1000) /*1000ns*/
#define FM_TRISE_400K (300) /*300ns*/
#define FM_TRISE_1M (120) /*120ns*/
/** Register shift macro definition **/
#define RCC_FLAG_STS2_OFFSET (REG_BIT16_OFFSET)
#define RCC_FLAG_GET_OFFSET (REG_BIT28_OFFSET)
#define I2C_REG_BIT_MASK ((uint16_t)0x0000)
/* I2C EN mask */
#define I2C_EN_SET (I2C_CTRL1_EN)
#define I2C_EN_RESET (~I2C_CTRL1_EN)
/* I2C START mask */
#define I2C_START_SET (I2C_CTRL1_STARTGEN)
#define I2C_START_RESET (~I2C_CTRL1_STARTGEN)
/* I2C STOP mask */
#define I2C_STOP_SET (I2C_CTRL1_STOPGEN)
#define I2C_STOP_RESET (~I2C_CTRL1_STOPGEN)
/* I2C ACK mask */
#define I2C_ACK_SET (I2C_CTRL1_ACKEN)
#define I2C_ACK_RESET (~I2C_CTRL1_ACKEN)
/* I2C ENGC mask */
#define I2C_GCEN_SET (I2C_CTRL1_GCEN)
#define I2C_GCEN_RESET (~I2C_CTRL1_GCEN)
/* I2C SWRST mask */
#define I2C_SWRESET_SET (I2C_CTRL1_SWRESET)
#define I2C_SWRESET_RESET (~I2C_CTRL1_SWRESET)
/* I2C PEC mask */
#define I2C_PEC_SET (I2C_CTRL1_PEC)
#define I2C_PEC_RESET (~I2C_CTRL1_PEC)
/* I2C ENPEC mask */
#define I2C_PECEN_SET (I2C_CTRL1_PECEN)
#define I2C_PECEN_RESET (~I2C_CTRL1_PECEN)
/* I2C NOSTRETCH mask */
#define I2C_NOEXTEND_SET (I2C_CTRL1_NOEXTEND)
#define I2C_NOEXTEND_RESET (~I2C_CTRL1_NOEXTEND)
/* I2C registers Masks */
#define I2C_ACKEN_CLR_MASK (~(I2C_CTRL1_ACKEN))
#define I2C_ADDRMODE_CLR_MASK (~(I2C_OADDR1_ADDRMODE))
#define I2C_OADDR_CLR_MASK (~(I2C_OADDR1_ADDR0 | I2C_OADDR1_ADDR1_7 | I2C_OADDR1_ADDR8_9))
/* I2C FREQ mask */
#define I2C_CLKFREQ_RESET (~I2C_CTRL2_CLKFREQ)
/* I2C ADD0 mask */
#define I2C_ADDR0_SET (I2C_OADDR1_ADDR0)
#define I2C_ADDR0_RESET (~I2C_OADDR1_ADDR0)
/* I2C ENDUAL mask */
#define I2C_DUALEN_SET (((uint16_t)I2C_OADDR2_DUALEN))
#define I2C_DUALEN_RESET (~((uint16_t)I2C_OADDR2_DUALEN))
/* I2C ADD2 mask */
#define I2C_ADDR2_SET ((uint16_t)I2C_OADDR2_ADDR2)
#define I2C_ADDR2_RESET (~((uint16_t)I2C_OADDR2_ADDR2))
/* I2C F/S mask */
#define I2C_FSMODE_SET (I2C_CLKCTRL_FSMODE)
/* I2C CHCFG mask */
#define I2C_CLKCTRL_SET (I2C_CLKCTRL_CLKCTRL)
/* I2C TMRISE mask */
#define I2C_SDADFW_MASK (~I2C_GFLTRCTRL_SDADFW)
#define I2C_SCLDFW_MASK (~I2C_GFLTRCTRL_SCLDFW)
#define I2C_SDAAFW_MASK (~I2C_GFLTRCTRL_SDAAFW)
#define I2C_SCLAFW_MASK (~I2C_GFLTRCTRL_SCLAFW)
#define I2C_SDAAFENN_SET (I2C_GFLTRCTRL_SDAAFENN)
#define I2C_SDAAFENN_RESET (~I2C_GFLTRCTRL_SDAAFENN)
#define I2C_SCLAFENN_SET (I2C_GFLTRCTRL_SCLAFENN)
#define I2C_SCLAFENN_RESET (~I2C_GFLTRCTRL_SCLAFENN)
#define I2C_TMRISE_MASK (I2C_TMRISE_TRISE)
/* I2C FLAG mask */
#define I2C_FLAG_Mask ((uint32_t)0x00FFFFFF)
/* I2C Interrupt Enable mask */
#define I2C_INTEN_MASK ((uint32_t)0x07000000)
/** I2C_duty_cycle **/
#define I2C_SMDUTYCYCLE_1 (I2C_REG_BIT_MASK) /* I2C standard mode Tlow/Thigh = 1/1 */
#define I2C_FMDUTYCYCLE_16_9 (I2C_CLKCTRL_DUTY) /* I2C fast mode Tlow/Thigh = 16/9 */
#define I2C_FMDUTYCYCLE_2 (~I2C_CLKCTRL_DUTY) /* I2C fast mode Tlow/Thigh = 2 */
/** I2C_acknowledgement **/
#define I2C_ACKEN (I2C_CTRL1_ACKEN)
#define I2C_ACKDIS (I2C_REG_BIT_MASK)
/** I2C_transfer_direction **/
#define I2C_DIRECTION_SEND ((uint8_t)0x00)
#define I2C_DIRECTION_RECV ((uint8_t)0x01)
/** I2C_acknowledged_address **/
/* Bit 14 Should be kept at 1 by software*/
#define I2C_ADDR_MODE_7BIT (((uint16_t)0x4000) | I2C_REG_BIT_MASK)
#define I2C_ADDR_MODE_10BIT (((uint16_t)0x4000) | I2C_OADDR1_ADDRMODE)
/** I2C_registers **/
#define I2C_REG_CTRL1 ((uint8_t)0x00)
#define I2C_REG_CTRL2 ((uint8_t)0x04)
#define I2C_REG_OADDR1 ((uint8_t)0x08)
#define I2C_REG_OADDR2 ((uint8_t)0x0C)
#define I2C_REG_DAT ((uint8_t)0x10)
#define I2C_REG_STS1 ((uint8_t)0x14)
#define I2C_REG_STS2 ((uint8_t)0x18)
#define I2C_REG_CLKCTRL ((uint8_t)0x1C)
#define I2C_REG_TMRISE ((uint8_t)0x20)
#define I2C_REG_GFLTRCTRL ((uint8_t)0x24)
#define I2C_REG_BYTENUM ((uint8_t)0x28)
/** I2C_PEC_position **/
#define I2C_PEC_POS_NEXT (I2C_CTRL1_ACKPOS)
#define I2C_PEC_POS_CURRENT (~I2C_CTRL1_ACKPOS)
/** I2C_NCAK_position **/
#define I2C_NACK_POS_NEXT (I2C_CTRL1_ACKPOS)
#define I2C_NACK_POS_CURRENT (~I2C_CTRL1_ACKPOS)
/** I2C_Analog_Filter_Width **/
#define I2C_ANALOG_FILTER_WIDTH_5NS ((uint16_t)0x0000)
#define I2C_ANALOG_FILTER_WIDTH_15NS (I2C_GFLTRCTRL_SDAAFW_0)
#define I2C_ANALOG_FILTER_WIDTH_25NS (I2C_GFLTRCTRL_SDAAFW_1)
#define I2C_ANALOG_FILTER_WIDTH_35NS (I2C_GFLTRCTRL_SDAAFW_0|I2C_GFLTRCTRL_SDAAFW_1)
/** I2C_interrupts_definition **/
#define I2C_INT_BUF (I2C_CTRL2_BUFINTEN)
#define I2C_INT_EVENT (I2C_CTRL2_EVTINTEN)
#define I2C_INT_ERR (I2C_CTRL2_ERRINTEN)
/* I2C BYTE_NUM_EN mask */
#define I2C_BYTENUMEN_SET (I2C_BYTENUM_BYTENUMEN)
#define I2C_BYTENUMEN_RESET (~I2C_BYTENUM_BYTENUMEN)
/* I2C BYTE_NUM byte number mask */
#define I2C_BYTENUM_MASK (~I2C_BYTENUM_BYTENUM)
/* I2C master sended status after finishing receiving data bytes */
#define I2C_BYTENUM_LAST_STOP (~I2C_BYTENUM_RXFSEL)
#define I2C_BYTENUM_LAST_START (I2C_BYTENUM_RXFSEL)
/** I2C_interrupts_definition **/
#define I2C_INT_PECERR (((uint32_t)0x01000000) | ((uint32_t)I2C_STS1_PECERR))
#define I2C_INT_OVERRUN (((uint32_t)0x01000000) | ((uint32_t)I2C_STS1_OVERRUN))
#define I2C_INT_ACKFAIL (((uint32_t)0x01000000) | ((uint32_t)I2C_STS1_ACKFAIL))
#define I2C_INT_ARLOST (((uint32_t)0x01000000) | ((uint32_t)I2C_STS1_ARLOST))
#define I2C_INT_BUSERR (((uint32_t)0x01000000) | ((uint32_t)I2C_STS1_BUSERR))
#define I2C_INT_TXDATE (((uint32_t)0x06000000) | ((uint32_t)I2C_STS1_TXDATE))
#define I2C_INT_RXDATNE (((uint32_t)0x06000000) | ((uint32_t)I2C_STS1_RXDATNE))
#define I2C_INT_STOPF (((uint32_t)0x02000000) | ((uint32_t)I2C_STS1_STOPF))
#define I2C_INT_ADDR10F (((uint32_t)0x02000000) | ((uint32_t)I2C_STS1_ADDR10F))
#define I2C_INT_BYTEF (((uint32_t)0x02000000) | ((uint32_t)I2C_STS1_BSF))
#define I2C_INT_ADDRF (((uint32_t)0x02000000) | ((uint32_t)I2C_STS1_ADDRF))
#define I2C_INT_STARTBF (((uint32_t)0x02000000) | ((uint32_t)I2C_STS1_STARTBF))
/** I2C_flags_definition **/
/** STS2 register flags **/
#define I2C_FLAG_DUALFLAG (((uint32_t)I2C_STS2_DUALFLAG)<<16)
#define I2C_FLAG_GCALLADDR (((uint32_t)I2C_STS2_GCALLADDR)<<16)
#define I2C_FLAG_TRF (((uint32_t)I2C_STS2_TRF)<<16)
#define I2C_FLAG_BUSY (((uint32_t)I2C_STS2_BUSY)<<16)
#define I2C_FLAG_MSMODE (((uint32_t)I2C_STS2_MSMODE)<<16)
/** STS1 register flags **/
#define I2C_FLAG_PECERR (((uint32_t)0x10000000) | ((uint32_t)I2C_STS1_PECERR))
#define I2C_FLAG_OVERRUN (((uint32_t)0x10000000) | ((uint32_t)I2C_STS1_OVERRUN))
#define I2C_FLAG_ACKFAIL (((uint32_t)0x10000000) | ((uint32_t)I2C_STS1_ACKFAIL))
#define I2C_FLAG_ARLOST (((uint32_t)0x10000000) | ((uint32_t)I2C_STS1_ARLOST))
#define I2C_FLAG_BUSERR (((uint32_t)0x10000000) | ((uint32_t)I2C_STS1_BUSERR))
#define I2C_FLAG_TXDATE (((uint32_t)0x10000000) | ((uint32_t)I2C_STS1_TXDATE))
#define I2C_FLAG_RXDATNE (((uint32_t)0x10000000) | ((uint32_t)I2C_STS1_RXDATNE))
#define I2C_FLAG_STOPF (((uint32_t)0x10000000) | ((uint32_t)I2C_STS1_STOPF))
#define I2C_FLAG_ADDR10F (((uint32_t)0x10000000) | ((uint32_t)I2C_STS1_ADDR10F))
#define I2C_FLAG_BYTEF (((uint32_t)0x10000000) | ((uint32_t)I2C_STS1_BSF))
#define I2C_FLAG_ADDRF (((uint32_t)0x10000000) | ((uint32_t)I2C_STS1_ADDRF))
#define I2C_FLAG_STARTBF (((uint32_t)0x10000000) | ((uint32_t)I2C_STS1_STARTBF))
/** I2C_Events **/
/** I2C Master Events (Events grouped in order of communication) **/
/**
*\*\brief Communication start
*\*\After sending the START condition (I2C_Generate_Start_Enable() function) the master
*\*\has to wait for this event. It means that the Start condition has been correctly
*\*\released on the I2C bus (the bus is free, no other devices is communicating).
**/
/* MSMODE */
#define I2C_ROLE_MASTER (((uint32_t)I2C_STS2_MSMODE)<<16)
/* EV5 */
/* BUSY, MSMODE and STARTBF flag*/
#define I2C_EVT_MASTER_MODE_FLAG (((uint32_t)I2C_STS1_STARTBF)\
|((((uint32_t)I2C_STS2_BUSY)|((uint32_t)I2C_STS2_MSMODE))<<16))
/**
*\*\brief Address Acknowledge
*\*\After checking on EV5 (start condition correctly released on the bus), the
*\*\master sends the address of the slave(s) with which it will communicate
*\*\(I2C_7bit_Addr_Send() function, it also determines the direction of the communication:
*\*\Master transmitter or Receiver). Then the master has to wait that a slave acknowledges
*\*\his address. If an acknowledge is sent on the bus, one of the following events will
*\*\be set:
*\*\ 1) In case of Master Receiver (7-bit addressing): the I2C_EVT_MASTER_RXMODE_FLAG
*\*\ event is set.
*\*\ 2) In case of Master Transmitter (7-bit addressing): the I2C_EVT_MASTER_TXMODE_FLAG
*\*\ is set
*\*\ 3) In case of 10-Bit addressing mode, the master (just after generating the START
*\*\ and checking on EV5) has to send the header of 10-bit addressing mode (I2C_Data_Send()
*\*\ function). Then master should wait on EV9. It means that the 10-bit addressing
*\*\ header has been correctly sent on the bus. Then master should send the second part of
*\*\ the 10-bit address (LSB) using the function I2C_7bit_Addr_Send(). Then master
*\*\ should wait for event EV6.
**/
/* --EV6 */
/* BUSY, MSMODE, ADDRF, TXDATE and TRF flags */
#define I2C_EVT_MASTER_TXMODE_FLAG (((uint32_t)I2C_STS1_ADDRF)|((uint32_t)I2C_STS1_TXDATE)\
|((((uint32_t)I2C_STS2_BUSY)|((uint32_t)I2C_STS2_MSMODE)|((uint32_t)I2C_STS2_TRF))<<16))
/* BUSY, MSMODE and ADDRF flags */
#define I2C_EVT_MASTER_RXMODE_FLAG (((uint32_t)I2C_STS1_ADDRF)\
|((((uint32_t)I2C_STS2_BUSY)|((uint32_t)I2C_STS2_MSMODE))<<16))
/* --EV9 */
/* BUSY, MSMODE and ADD10RF flags */
#define I2C_EVT_MASTER_MODE_ADDRESS10_FLAG (((uint32_t)I2C_STS1_ADDR10F)\
|((((uint32_t)I2C_STS2_BUSY)|((uint32_t)I2C_STS2_MSMODE))<<16))
/**
*\*\brief Communication events
*\*\If a communication is established (START condition generated and slave address
*\*\acknowledged) then the master has to check on one of the following events for
*\*\communication procedures:
*\*\1) Master Receiver mode: The master has to wait on the event EV7 then to read
*\*\ the data received from the slave (I2C_Data_Recv() function).
*\*\2) Master Transmitter mode: The master has to send data (I2C_Data_Send()
*\*\ function) then to wait on event EV8 or EV8_2.
*\*\ These two events are similar:
*\*\ - EV8 means that the data has been written in the data register and is
*\*\ being shifted out.
*\*\ - EV8_2 means that the data has been physically shifted out and output
*\*\ on the bus.
*\*\ In most cases, using EV8 is sufficient for the application.
*\*\ Using EV8_2 leads to a slower communication but ensure more reliable test.
*\*\ EV8_2 is also more suitable than EV8 for testing on the last data transmission
*\*\ (before Stop condition generation).
*\*\note In case the user software does not guarantee that this event EV7 is
*\*\ managed before the current byte end of transfer, then user may check on EV7
*\*\ and BSF flag at the same time (ie. (I2C_EVT_MASTER_DATA_RECVD_FLAG | I2C_FLAG_BYTEF)).
*\*\ In this case the communication may be slower.
**/
/* Master RECEIVER mode -----------------------------*/
/* --EV7 */
/* BUSY, MSMODE and RXDATNE flags */
#define I2C_EVT_MASTER_DATA_RECVD_FLAG (((uint32_t)I2C_STS1_RXDATNE)\
|((((uint32_t)I2C_STS2_BUSY)|((uint32_t)I2C_STS2_MSMODE))<<16))
/* EV7x shifter register full */
/* BUSY, MSMODE, BSF and RXDATNE flags */
#define I2C_EVT_MASTER_DATA_RECVD_BSF_FLAG (((uint32_t)I2C_STS1_RXDATNE)|((uint32_t)I2C_STS1_BSF)\
|((((uint32_t)I2C_STS2_BUSY)|((uint32_t)I2C_STS2_MSMODE))<<16))
/* Master TRANSMITTER mode --------------------------*/
/* --EV8 */
/* TRF, BUSY, MSMODE, TXDATE flags */
#define I2C_EVT_MASTER_DATA_SENDING (((uint32_t)I2C_STS1_TXDATE)\
|((((uint32_t)I2C_STS2_BUSY)|((uint32_t)I2C_STS2_MSMODE)|((uint32_t)I2C_STS2_TRF))<<16))
/* --EV8_2 */
/* TRF, BUSY, MSMODE, TXDATE and BSF flags */
#define I2C_EVT_MASTER_DATA_SENDED (((uint32_t)I2C_STS1_BSF)|((uint32_t)I2C_STS1_TXDATE)\
|((((uint32_t)I2C_STS2_BUSY)|((uint32_t)I2C_STS2_MSMODE)|((uint32_t)I2C_STS2_TRF))<<16))
/*========================================
I2C Slave Events (Events grouped in order of communication)
==========================================*/
/**
*\*\brief Communication start events
*\*\Wait on one of these events at the start of the communication. It means that
*\*\the I2C peripheral detected a Start condition on the bus (generated by master
*\*\device) followed by the peripheral address. The peripheral generates an ACK
*\*\condition on the bus (if the acknowledge feature is enabled through function
*\*\I2C_ConfigAck()) and the events listed above are set :
*\*\1) In normal case (only one address managed by the slave), when the address
*\*\ sent by the master matches the own address of the peripheral (configured by
*\*\ OwnAddr1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set
*\*\ (where XXX could be TRANSMITTER or RECEIVER).
*\*\2) In case the address sent by the master matches the second address of the
*\*\ peripheral (configured by the function I2C_ConfigOwnAddr2() and enabled
*\*\ by the function I2C_EnableDualAddr()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED
*\*\ (where XXX could be TRANSMITTER or RECEIVER) are set.
*\*\3) In case the address sent by the master is General Call (address 0x00) and
*\*\ if the General Call is enabled for the peripheral (using function I2C_EnableGeneralCall())
*\*\ the following event is set I2C_EVT_SLAVE_GCALLADDR_MATCHED.
**/
/* --EV1 (all the events below are variants of EV1) */
/* 1) Case of One Single Address managed by the slave */
/* BUSY and ADDRF flags */
#define I2C_EVT_SLAVE_RECV_ADDR_MATCHED (((uint32_t)I2C_STS1_ADDRF)\
|((((uint32_t)I2C_STS2_BUSY))<<16))
/* TRF, BUSY, TXDATE and ADDRF flags */
#define I2C_EVT_SLAVE_SEND_ADDR_MATCHED (((uint32_t)I2C_STS1_TXDATE)|((uint32_t)I2C_STS1_ADDRF)\
|((((uint32_t)I2C_STS2_BUSY)|((uint32_t)I2C_STS2_TRF))<<16))
/* 2) Case of Dual address managed by the slave */
/* DUALF and BUSY flags */
#define I2C_EVT_SLAVE_RECV_ADDR2_MATCHED ((((uint32_t)I2C_STS2_BUSY)|((uint32_t)I2C_STS2_DUALFLAG))<<16)
/* DUALF, TRF, BUSY and TXDATE flags */
#define I2C_EVT_SLAVE_SEND_ADDR2_MATCHED (((uint32_t)I2C_STS1_TXDATE)\
|((((uint32_t)I2C_STS2_BUSY)|((uint32_t)I2C_STS2_DUALFLAG)|((uint32_t)I2C_STS2_TRF))<<16))
/* 3) Case of General Call enabled for the slave */
/* GENCALL and BUSY flags */
#define I2C_EVT_SLAVE_GCALLADDR_MATCHED ((((uint32_t)I2C_STS2_BUSY)|((uint32_t)I2C_STS2_GCALLADDR))<<16)
/**
*\*\brief Communication events
*\*\Wait on one of these events when EV1 has already been checked and:
*\*\- Slave RECEIVER mode:
*\*\ - EV2: When the application is expecting a data byte to be received.
*\*\ - EV4: When the application is expecting the end of the communication: master
*\*\ sends a stop condition and data transmission is stopped.
*\*\- Slave Transmitter mode:
*\*\ - EV3: When a byte has been transmitted by the slave and the application is expecting
*\*\ the end of the byte transmission. The two events I2C_EVT_SLAVE_DATA_SENDED and
*\*\ I2C_EVT_SLAVE_DATA_SENDING are similar. The second one can optionally be
*\*\ used when the user software doesn't guarantee the EV3 is managed before the
*\*\ current byte end of transfer.
*\*\ - EV3_2: When the master sends a NACK in order to tell slave that data transmission
*\*\ shall end (before sending the STOP condition). In this case slave has to stop sending
*\*\ data bytes and expect a Stop condition on the bus.
*\*\note In case the user software does not guarantee that the event EV2 is
*\*\ managed before the current byte end of transfer, then user may check on EV2
*\*\ and BSF flag at the same time (ie. (I2C_EVT_SLAVE_DATA_RECVD | I2C_FLAG_BYTEF)).
*\*\In this case the communication may be slower.
**/
/* Slave RECEIVER mode --------------------------*/
/* --EV2 */
/* BUSY and RXDATNE flags */
#define I2C_EVT_SLAVE_DATA_RECVD (((uint32_t)I2C_STS1_RXDATNE)\
|((((uint32_t)I2C_STS2_BUSY))<<16))
/* --EV2x */
/* no BUSY and RXDATNE flags */
#define I2C_EVT_SLAVE_DATA_RECVD_NOBUSY ((uint32_t)I2C_STS1_RXDATNE)
/* --EV4 */
/* STOPF flag */
#define I2C_EVT_SLAVE_STOP_RECVD ((uint32_t)I2C_STS1_STOPF)
/* Slave TRANSMITTER mode -----------------------*/
/* --EV3 */
/* TRF, BUSY, TXDATE and BSF flags */
#define I2C_EVT_SLAVE_DATA_SENDED (((uint32_t)I2C_STS1_BSF)|((uint32_t)I2C_STS1_TXDATE)\
|((((uint32_t)I2C_STS2_BUSY)|((uint32_t)I2C_STS2_TRF))<<16))
/* TRF, BUSY and TXDATE flags */
#define I2C_EVT_SLAVE_DATA_SENDING (((uint32_t)I2C_STS1_TXDATE)\
|((((uint32_t)I2C_STS2_BUSY)|((uint32_t)I2C_STS2_TRF))<<16))
/* --EV3_2 */
/* AF flag */
#define I2C_EVT_SLAVE_ACK_MISS ((uint32_t)I2C_STS1_ACKFAIL)
/*=========================== End of Events Description ==========================================*/
void I2C_Reset(I2C_Module* I2Cx);
void I2C_Initializes(I2C_Module* I2Cx, I2C_InitType* I2C_InitParam);
void I2C_Clock_Speed_Config(I2C_Module* I2Cx, uint32_t clk_speed, uint16_t duty_cycle);
void I2C_Acknowledgement_Config(I2C_Module* I2Cx, uint16_t ack);
void I2C_Addressing_Mode_Config(I2C_Module* I2Cx, uint16_t mode);
void I2C_Own_Addr1_Config(I2C_Module* I2Cx, uint16_t addr1);
void I2C_Initializes_Structure(I2C_InitType* I2C_InitStruct);
void I2C_ON(I2C_Module* I2Cx);
void I2C_OFF(I2C_Module* I2Cx);
void I2C_Generate_Start_Enable(I2C_Module* I2Cx);
void I2C_Generate_Start_Disable(I2C_Module* I2Cx);
void I2C_Generate_Stop_Enable(I2C_Module* I2Cx);
void I2C_Generate_Stop_Disable(I2C_Module* I2Cx);
void I2C_Acknowledg_Enable(I2C_Module* I2Cx);
void I2C_Acknowledg_Disable(I2C_Module* I2Cx);
void I2C_Own_Addr2_Set(I2C_Module* I2Cx, uint8_t address);
void I2C_Dual_Addr_Enable(I2C_Module* I2Cx);
void I2C_Dual_Addr_Disable(I2C_Module* I2Cx);
void I2C_General_Call_Enable(I2C_Module* I2Cx);
void I2C_General_Call_Disable(I2C_Module* I2Cx);
void I2C_Interrupts_Enable(I2C_Module* I2Cx, uint16_t I2C_IT);
void I2C_Interrupts_Disable(I2C_Module* I2Cx, uint16_t I2C_IT);
void I2C_Data_Send(I2C_Module* I2Cx, uint8_t data);
uint8_t I2C_Data_Recv(I2C_Module* I2Cx);
void I2C_7bit_Addr_Send(I2C_Module* I2Cx, uint8_t address, uint8_t mode);
uint16_t I2C_Register_Value_Get(I2C_Module* I2Cx, uint8_t I2C_Register);
void I2C_Software_Reset_Enable(I2C_Module* I2Cx);
void I2C_Software_Reset_Disable(I2C_Module* I2Cx);
void I2C_NACK_Position_Set(I2C_Module* I2Cx, uint16_t position);
void I2C_PEC_Send_Enable(I2C_Module* I2Cx);
void I2C_PEC_Send_Disable(I2C_Module* I2Cx);
void I2C_PEC_Position_Set(I2C_Module* I2Cx, uint16_t position);
void I2C_PEC_Compute_Enable(I2C_Module* I2Cx);
void I2C_PEC_Compute_Disable(I2C_Module* I2Cx);
uint8_t I2C_PEC_Get(I2C_Module* I2Cx);
void I2C_Extend_Clock_Enable(I2C_Module* I2Cx);
void I2C_Extend_Clock_Disable(I2C_Module* I2Cx);
void I2C_Fast_Mode_Duty_Cycle_Set(I2C_Module* I2Cx, uint16_t duty_cycle);
void I2C_SDA_Digital_Filter_Width_Set(I2C_Module* I2Cx, uint8_t width);
void I2C_SCL_Digital_Filter_Width_Set(I2C_Module* I2Cx, uint8_t width);
void I2C_SDA_Analog_Filter_Width_Set(I2C_Module* I2Cx, uint16_t width);
void I2C_SDA_Analog_Filter_Enable(I2C_Module* I2Cx);
void I2C_SDA_Analog_Filter_Disable(I2C_Module* I2Cx);
void I2C_SCL_Analog_Filter_Width_Set(I2C_Module* I2Cx, uint16_t width);
void I2C_SCL_Analog_Filter_Enable(I2C_Module* I2Cx);
void I2C_SCL_Analog_Filter_Disable(I2C_Module* I2Cx);
ErrorStatus I2C_Event_Check( I2C_Module* I2Cx, uint32_t I2C_event );
uint32_t I2C_Last_Event_Get( I2C_Module* I2Cx );
FlagStatus I2C_Flag_Status_Get( I2C_Module* I2Cx, uint32_t I2C_flag );
void I2C_Flag_Status_Clear( I2C_Module* I2Cx, uint32_t I2C_flag );
ITStatus I2C_Interrupt_Status_Get( I2C_Module* I2Cx, uint32_t Interrupt );
void I2C_Interrupt_Statu_Clear(I2C_Module* I2Cx, uint32_t Interrupt);
void I2C_ByteNum_enable(I2C_Module* I2Cx);
void I2C_ByteNum_Disable(I2C_Module* I2Cx);
void I2C_Master_Received_DataBytesNum_Set(I2C_Module* I2Cx, uint16_t Number_Of_bytes);
void I2C_ByteNum_Last_StartStop_Set(I2C_Module* I2Cx, uint16_t LastStatus);
#ifdef __cplusplus
}
#endif
#endif /*__N32G003_I2C_H */
/**
*
*/

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/**
* Copyright (c) 2022, Nations Technologies Inc.
*
* All rights reserved.
*
* This software is the exclusive property of Nations Technologies Inc. (Hereinafter
* referred to as NATIONS). This software, and the product of NATIONS described herein
* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties
* of the People's Republic of China and other applicable jurisdictions worldwide.
*
* NATIONS does not grant any license under its patents, copyrights, trademarks, or other
* intellectual property rights. Names and brands of third party may be mentioned or referred
* thereto (if any) for identification purposes only.
*
* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and
* improvements to this software at any time without notice. Please contact NATIONS and obtain
* the latest version of this software before placing orders.
* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes
* no responsibility for the accuracy and reliability of this software.
*
* It is the responsibility of the user of this software to properly design, program, and test
* the functionality and safety of any application made of this information and any resulting product.
* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or
* consequential damages arising in any way out of the use of this software or the Product.
*
* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any
* malfunction or failure of which may cause loss of human life, bodily injury or severe property
* damage. Such applications are deemed, "Insecure Usage".
*
* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS
* harmless from and against all claims, costs, damages, and other liabilities, arising from or related
* to any customer's Insecure Usage.
* Any express or implied warranty with regard to this software or the Product, including,but not
* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement
* are disclaimed to the fullest extent permitted by law.
* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe
* or otherwise distribute this software for any purposes, in whole or in part.
*
* NATIONS products and technologies shall not be used for or incorporated into any products or systems
* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations.
* User shall comply with any applicable export control laws and regulations promulgated and administered by
* the governments of any countries asserting jurisdiction over the parties or transactions.
**/
/**
*\*\file n32g003_iwdg.h
*\*\author Nations
*\*\version v1.0.0
*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
**/
#ifndef __n32g003_IWDG_H
#define __n32g003_IWDG_H
#ifdef __cplusplus
extern "C" {
#endif
#include "n32g003.h"
typedef enum
{
IWDG_PVU_FLAG = IWDG_STS_PVU,
IWDG_CRVU_FLAG = IWDG_STS_CRVU
}IWDG_STATUS_FLAG;
/** KEY register bit mask **/
#define KEY_RELOAD_COUNTER ((uint16_t)0xAAAA)
#define KEY_ENABLE_COUNTER ((uint16_t)0xCCCC)
#define IWDG_FREEZE ((uint16_t)0xDDDD)
#define IWDG_UNFREEZE ((uint16_t)0xDDDD)
/** PREDIV and RELV register write permission **/
typedef enum
{
IWDG_WRITE_CONFIG_ENABLE = 0x5555,
IWDG_WRITE_CONFIG_DISABLE = 0x0000
}IWDOG_WRITE_CONFIG;
typedef enum
{
IWDG_CONFIG_PRESCALER_DIV4 = (~IWDG_PREDIV_PD),
IWDG_CONFIG_PRESCALER_DIV8 = (IWDG_PREDIV_PD0),
IWDG_CONFIG_PRESCALER_DIV16 = (IWDG_PREDIV_PD1),
IWDG_CONFIG_PRESCALER_DIV32 = (IWDG_PREDIV_PD1 | IWDG_PREDIV_PD0),
IWDG_CONFIG_PRESCALER_DIV64 = (IWDG_PREDIV_PD2),
IWDG_CONFIG_PRESCALER_DIV128 = (IWDG_PREDIV_PD2 | IWDG_PREDIV_PD0),
IWDG_CONFIG_PRESCALER_DIV256 = (IWDG_PREDIV_PD2 | IWDG_PREDIV_PD1 | IWDG_PREDIV_PD0)
}IWDG_CONFIG_PRESCALER;
#define IWDG_FREEZE_FLAG ((uint16_t)IWDG_FREEZE_FREEZE)
void IWDG_Write_Protection_Disable(void);
void IWDG_Write_Protection_Enable(void);
void IWDG_Prescaler_Division_Set(IWDG_CONFIG_PRESCALER IWDG_prescaler);
void IWDG_Counter_Reload(uint16_t reload_value);
void IWDG_Key_Reload(void);
void IWDG_Enable(void);
ErrorStatus IWDG_Freeze_Enable(void);
ErrorStatus IWDG_Restore_From_Freeze(void);
FlagStatus IWDG_Status_Get(IWDG_STATUS_FLAG IWDG_flag);
#ifdef __cplusplus
}
#endif
#endif /* __n32g003_IWDG_H */

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/**
* Copyright (c) 2022, Nations Technologies Inc.
*
* All rights reserved.
*
* This software is the exclusive property of Nations Technologies Inc. (Hereinafter
* referred to as NATIONS). This software, and the product of NATIONS described herein
* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties
* of the People's Republic of China and other applicable jurisdictions worldwide.
*
* NATIONS does not grant any license under its patents, copyrights, trademarks, or other
* intellectual property rights. Names and brands of third party may be mentioned or referred
* thereto (if any) for identification purposes only.
*
* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and
* improvements to this software at any time without notice. Please contact NATIONS and obtain
* the latest version of this software before placing orders.
* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes
* no responsibility for the accuracy and reliability of this software.
*
* It is the responsibility of the user of this software to properly design, program, and test
* the functionality and safety of any application made of this information and any resulting product.
* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or
* consequential damages arising in any way out of the use of this software or the Product.
*
* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any
* malfunction or failure of which may cause loss of human life, bodily injury or severe property
* damage. Such applications are deemed, "Insecure Usage".
*
* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS
* harmless from and against all claims, costs, damages, and other liabilities, arising from or related
* to any customer's Insecure Usage.
* Any express or implied warranty with regard to this software or the Product, including,but not
* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement
* are disclaimed to the fullest extent permitted by law.
* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe
* or otherwise distribute this software for any purposes, in whole or in part.
*
* NATIONS products and technologies shall not be used for or incorporated into any products or systems
* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations.
* User shall comply with any applicable export control laws and regulations promulgated and administered by
* the governments of any countries asserting jurisdiction over the parties or transactions.
**/
/**
*\*\file n32g003_pwr.h
*\*\author Nations
*\*\version v1.0.0
*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
*/
#ifndef __N32G003_PWR_H
#define __N32G003_PWR_H
#ifdef __cplusplus
extern "C" {
#endif
#include "n32g003.h"
/*** PWR Structure Definition Start ***/
/** PWR wakeup PINx enmu definition **/
typedef enum
{
WAKEUP_PIN1 = 0x0100,
WAKEUP_PIN2 = 0x0200,
} WAKEUP_PINX;
/*** PWR Structure Definition End ***/
/*** PWR Macro Definition Start ***/
/** PWR CTRL register bit mask definition **/
#define PWR_CTRL_PLS_MASK (~((uint32_t)PWR_CTRL_PLS))
#define PWR_CTRL_PDSTP_MASK (~((uint32_t)PWR_CTRL_PDSTP))
#define PWR_CTRL_PDRS_MASK (~((uint32_t)PWR_CTRL_PDRS))
/** PWR CTRL2 register bit mask definition **/
#define PWR_CTRL2_LVRLS_MASK (~((uint32_t)PWR_CTRL2_LVRLS))
/** PWR CTRLSTS register bit mask definition **/
#define PWR_CTRLSTS_WKUPPOL_MASK (~((uint32_t)PWR_CTRLSTS_WKUPPOL))
/** PWR CTRL5 register bit mask definition **/
#define PWR_CTRL5_STPMRSEL_MASK (~((uint32_t)PWR_CTRL5_STPMRSEL))
/** PWR PVD enable definition **/
#define PWR_PVD_ENABLE ((uint32_t)PWR_CTRL_PVDEN)
/** PWR PVD interrupt enable definition **/
#define PWR_PVD_INT_ENABLE ((uint32_t)PWR_CTRL_PVDITEN)
/** PWR PVD Filter enable definition **/
#define PWR_PVD_FIL_ENABLE ((uint32_t)PWR_CTRL_PVDFILEN)
/** PWR LVR enable definition **/
#define PWR_LVR_ENABLE ((uint32_t)PWR_CTRL2_LVREN)
/** PWR LVR reset enable definition **/
#define PWR_LVR_RST_ENABLE ((uint32_t)PWR_CTRL2_LVRRSTEN)
/** PWR LVR Filter enable definition **/
#define PWR_LVR_FIL_ENABLE ((uint32_t)PWR_CTRL2_LVRFILEN)
/** PWR wakup PIN polarity definition **/
#define PWR_PIN_RISING ((uint32_t)0x00000001)
#define PWR_PIN_FALLING ((uint32_t)0x00000000)
/** PWR clear WKUPF definition **/
#define PWR_CLEAR_WKUPF ((uint32_t)PWR_CTRL_CLRWKUPF)
/** PWR PVD output Flag definition **/
#define PWR_PVD_OUTPUT_FLAG ((uint32_t)PWR_CTRLSTS_PVDO)
/** PWR PD Flag definition **/
#define PWR_DBGPD_FLAG ((uint32_t)PWR_CTRLSTS_DBGPDF)
/** PWR PA2/PA1wakeup Flag definition **/
#define PWR_WKUP_FLAG ((uint32_t)PWR_CTRLSTS_WKUPF)
/** PWR LVR output Flag definition **/
#define PWR_LVR_OUTPUT_FLAG ((uint32_t)PWR_CTRL2_LVRO)
/** PWR PD mode definition **/
#define PWR_PD_MODE ((uint32_t)PWR_CTRL_PDSTP)
/** PWR control HSI definition **/
#define PWR_CONTROL_HSI ((uint32_t)PWR_CTRL3_HSIPWR)
/** PWR control PDR select signal definition **/
#define PWR_CONTROL_PDR_SEL ((uint32_t)PWR_CTRL3_PDRSEL)
/** PWR HSI 40M trim definition **/
#define PWR_HSI_TRIM_40M ((uint32_t)PWR_CTRL3_HSISEL)
/** PWR enable VDDD output voltage select definition **/
#define PWR_VDDD_OUTPUT_SEL_EN ((uint32_t)PWR_CTRL6_STPMREN)
/** PWR PVD threshold level definition **/
#define PWR_PVD_LEVEL_1V8 ((uint32_t)(PWR_CTRL_PLS_0 \
& PWR_CTRL_PLS_1 \
& PWR_CTRL_PLS_2 \
& PWR_CTRL_PLS_3)) /* 1.8v PWR_CTRL bit[8:5]:0000 */
#define PWR_PVD_LEVEL_2V0 ((uint32_t)PWR_CTRL_PLS_0) /* 2.0v PWR_CTRL bit[8:5]:0001 */
#define PWR_PVD_LEVEL_2V2 ((uint32_t)PWR_CTRL_PLS_1) /* 2.2v PWR_CTRL bit[8:5]:0010 */
#define PWR_PVD_LEVEL_2V4 ((uint32_t)(PWR_CTRL_PLS_0 \
| PWR_CTRL_PLS_1)) /* 2.4v PWR_CTRL bit[8:5]:0011 */
#define PWR_PVD_LEVEL_2V6 ((uint32_t)PWR_CTRL_PLS_2) /* 2.6v PWR_CTRL bit[8:5]:0100 */
#define PWR_PVD_LEVEL_2V8 ((uint32_t)(PWR_CTRL_PLS_0 \
| PWR_CTRL_PLS_2)) /* 2.8v PWR_CTRL bit[8:5]:0101 */
#define PWR_PVD_LEVEL_3V0 ((uint32_t)(PWR_CTRL_PLS_1 \
| PWR_CTRL_PLS_2)) /* 3.0v PWR_CTRL bit[8:5]:0110 */
#define PWR_PVD_LEVEL_3V2 ((uint32_t)(PWR_CTRL_PLS_0 \
| PWR_CTRL_PLS_1 \
| PWR_CTRL_PLS_2)) /* 3.2v PWR_CTRL bit[8:5]:0111 */
#define PWR_PVD_LEVEL_3V4 ((uint32_t)PWR_CTRL_PLS_3) /* 3.4v PWR_CTRL bit[8:5]:1000 */
#define PWR_PVD_LEVEL_3V6 ((uint32_t)(PWR_CTRL_PLS_0 \
| PWR_CTRL_PLS_3)) /* 3.6v PWR_CTRL bit[8:5]:1001 */
#define PWR_PVD_LEVEL_3V8 ((uint32_t)(PWR_CTRL_PLS_1 \
| PWR_CTRL_PLS_3)) /* 3.8v PWR_CTRL bit[8:5]:1010 */
#define PWR_PVD_LEVEL_4V0 ((uint32_t)(PWR_CTRL_PLS_0 \
| PWR_CTRL_PLS_1 \
| PWR_CTRL_PLS_3)) /* 4.0v PWR_CTRL bit[8:5]:1011 */
#define PWR_PVD_LEVEL_4V2 ((uint32_t)(PWR_CTRL_PLS_2 \
| PWR_CTRL_PLS_3)) /* 4.2v PWR_CTRL bit[8:5]:1100 */
#define PWR_PVD_LEVEL_4V4 ((uint32_t)(PWR_CTRL_PLS_0 \
| PWR_CTRL_PLS_2 \
| PWR_CTRL_PLS_3)) /* 4.4v PWR_CTRL bit[8:5]:1101 */
#define PWR_PVD_LEVEL_4V6 ((uint32_t)(PWR_CTRL_PLS_1 \
| PWR_CTRL_PLS_2 \
| PWR_CTRL_PLS_3)) /* 4.6v PWR_CTRL bit[8:5]:1110 */
#define PWR_PVD_LEVEL_4V8 ((uint32_t)(PWR_CTRL_PLS_0 \
| PWR_CTRL_PLS_1 \
| PWR_CTRL_PLS_2 \
| PWR_CTRL_PLS_3)) /* 4.8v PWR_CTRL bit[8:5]:1111 */
/** PWR LVR threshold level definition **/
#define PWR_LVR_LEVEL_1V8 ((uint32_t)(PWR_CTRL2_LVRLS_0 \
& PWR_CTRL2_LVRLS_1 \
& PWR_CTRL2_LVRLS_2 \
& PWR_CTRL2_LVRLS_3)) /* 1.8v PWR_CTRL2 bit[14:11]:0000 */
#define PWR_LVR_LEVEL_2V0 ((uint32_t)PWR_CTRL2_LVRLS_0) /* 2.0v PWR_CTRL2 bit[14:11]:0001 */
#define PWR_LVR_LEVEL_2V2 ((uint32_t)PWR_CTRL2_LVRLS_1) /* 2.2v PWR_CTRL2 bit[14:11]:0010 */
#define PWR_LVR_LEVEL_2V4 ((uint32_t)(PWR_CTRL2_LVRLS_0 \
| PWR_CTRL2_LVRLS_1)) /* 2.4v PWR_CTRL2 bit[14:11]:0011 */
#define PWR_LVR_LEVEL_2V6 ((uint32_t)PWR_CTRL2_LVRLS_2) /* 2.6v PWR_CTRL2 bit[14:11]:0100 */
#define PWR_LVR_LEVEL_2V8 ((uint32_t)(PWR_CTRL2_LVRLS_0 \
| PWR_CTRL2_LVRLS_2)) /* 2.8v PWR_CTRL2 bit[14:11]:0101 */
#define PWR_LVR_LEVEL_3V0 ((uint32_t)(PWR_CTRL2_LVRLS_1 \
| PWR_CTRL2_LVRLS_2)) /* 3.0v PWR_CTRL2 bit[14:11]:0110 */
#define PWR_LVR_LEVEL_3V2 ((uint32_t)(PWR_CTRL2_LVRLS_0 \
| PWR_CTRL2_LVRLS_1 \
| PWR_CTRL2_LVRLS_2)) /* 3.2v PWR_CTRL2 bit[14:11]:0111 */
#define PWR_LVR_LEVEL_3V4 ((uint32_t)PWR_CTRL2_LVRLS_3) /* 3.4v PWR_CTRL2 bit[14:11]:1000 */
#define PWR_LVR_LEVEL_3V6 ((uint32_t)(PWR_CTRL2_LVRLS_0 \
| PWR_CTRL2_LVRLS_3)) /* 3.6v PWR_CTRL2 bit[14:11]:1001 */
#define PWR_LVR_LEVEL_3V8 ((uint32_t)(PWR_CTRL2_LVRLS_1 \
| PWR_CTRL2_LVRLS_3)) /* 3.8v PWR_CTRL2 bit[14:11]:1010 */
#define PWR_LVR_LEVEL_4V0 ((uint32_t)(PWR_CTRL2_LVRLS_0 \
| PWR_CTRL2_LVRLS_1 \
| PWR_CTRL2_LVRLS_3)) /* 4.0v PWR_CTRL2 bit[14:11]:1011 */
#define PWR_LVR_LEVEL_4V2 ((uint32_t)(PWR_CTRL2_LVRLS_2 \
| PWR_CTRL2_LVRLS_3)) /* 4.2v PWR_CTRL2 bit[14:11]:1100 */
#define PWR_LVR_LEVEL_4V4 ((uint32_t)(PWR_CTRL2_LVRLS_0 \
| PWR_CTRL2_LVRLS_2 \
| PWR_CTRL2_LVRLS_3)) /* 4.4v PWR_CTRL2 bit[14:11]:1101 */
#define PWR_LVR_LEVEL_4V6 ((uint32_t)(PWR_CTRL2_LVRLS_1 \
| PWR_CTRL2_LVRLS_2 \
| PWR_CTRL2_LVRLS_3)) /* 4.6v PWR_CTRL2 bit[14:11]:1110 */
#define PWR_LVR_LEVEL_4V8 ((uint32_t)(PWR_CTRL2_LVRLS_0 \
| PWR_CTRL2_LVRLS_1 \
| PWR_CTRL2_LVRLS_2 \
| PWR_CTRL2_LVRLS_3)) /* 4.8v PWR_CTRL2 bit[14:11]:1111 */
/** PWR PDR trigger level definition **/
#define PWR_PDR_LEVEL_0V8 ((uint32_t)PWR_CTRL_PDRS_0) /* 0.8v PWR_CTRL bit[10:9]:01 */
#define PWR_PDR_LEVEL_1V0 ((uint32_t)PWR_CTRL_PDRS_1) /* 1.0v PWR_CTRL bit[10:9]:10 */
#define PWR_PDR_LEVEL_1V2 ((uint32_t)(PWR_CTRL_PDRS_0 \
| PWR_CTRL_PDRS_1)) /* 0.2v PWR_CTRL bit[10:9]:11 */
/** PWR VDDD output voltage definition **/
#define PWR_VDDD_OUTPUT_1V5 ((uint32_t)PWR_CTRL5_STPMRSEL_0) /* 1.5v PWR_CTRL5 bit[3:2]:01 */
#define PWR_VDDD_OUTPUT_1V0 ((uint32_t)PWR_CTRL5_STPMRSEL_1) /* 1.0v PWR_CTRL5 bit[3:2]:10 */
#define PWR_VDDD_OUTPUT_1V2 ((uint32_t)(PWR_CTRL5_STPMRSEL_0 \
| PWR_CTRL5_STPMRSEL_1)) /* 0.2v PWR_CTRL5 bit[3:2]:11 */
/** PWR STOP mode entry definition **/
#define PWR_STOP_ENTRY_WFI ((uint8_t)0x01) /* enter STOP mode with WFI instruction */
#define PWR_STOP_ENTRY_WFE ((uint8_t)0x02) /* enter STOP mode with WFE instruction */
/** PWR PD mode entry definition **/
#define PWR_PD_ENTRY_WFI ((uint8_t)0x01) /* enter PD mode with WFI instruction */
#define PWR_PD_ENTRY_WFE ((uint8_t)0x02) /* enter PD mode with WFE instruction */
/** PWR DBG_CTRL definition **/
#define PWR_DBG_SLEEP ((uint32_t)DBG_CTRL_SLEEP)
#define PWR_DBG_STOP ((uint32_t)DBG_CTRL_STOP)
#define PWR_DBG_PD ((uint32_t)DBG_CTRL_PD)
#define PWR_DBG_IWDG ((uint32_t)DBG_CTRL_IWDGSTP)
#define PWR_DBG_TIM1 ((uint32_t)DBG_CTRL_TIM1STP)
#define PWR_DBG_TIM3 ((uint32_t)DBG_CTRL_TIM3STP)
#define PWR_DBG_TIM6 ((uint32_t)DBG_CTRL_TIM6STP)
/** PWR registers write protection keys definition **/
#define PWR_CTRL2_KEYS ((uint32_t)0xA5000000)
#define PWR_CTRL4_KEYS ((uint32_t)0x01753603)
/** PWR bit shift number definition **/
#define PWR_BIT_SHIFT_2 ((uint32_t)REG_BIT2_OFFSET)
#define PWR_BIT_SHIFT_10 ((uint32_t)REG_BIT10_OFFSET)
/*** PWR Macro Definition End ***/
/*** PWR Driving Functions Declaration ***/
void PWR_Reset(void);
void PWR_PVD_Enable(void);
void PWR_PVD_Disable(void);
void PWR_PVD_Interrupt_Enable(void);
void PWR_PVD_Interrupt_Disable(void);
void PWR_PVD_Filter_Enable(void);
void PWR_PVD_Filter_Disable(void);
void PWR_PVD_Level_Config(uint32_t level);
void PWR_LVR_Enable(void);
void PWR_LVR_Disable(void);
void PWR_LVR_Reset_Enable(void);
void PWR_LVR_Reset_Disable(void);
void PWR_LVR_Filter_Enable(void);
void PWR_LVR_Filter_Disable(void);
void PWR_LVR_Level_Config(uint32_t level);
void PWR_Wakeup_Pin_Enable(WAKEUP_PINX pin, uint32_t polarity);
void PWR_Wakeup_Pin_Disable(WAKEUP_PINX pin);
void PWR_STOP_Mode_Enter(uint8_t enter_mode);
void PWR_PD_Mode_Enter(uint8_t enter_mode);
void PWR_HSI_40M_Trim_Select(void);
void PWR_PDR_Trigger_Level_Config(uint32_t level);
void PWR_VDDD_Output_Config(uint32_t voltage_output);
void PWR_CTRL2_write_Protection_Enable(void);
void PWR_CTRL4_write_Protection_Enable(void);
FlagStatus PWR_Flag_Status_Get(uint32_t flag);
void PWR_Flag_Status_Clear(uint32_t flag);
void DBG_Peripheral_ON(uint32_t DBG_Periph);
void DBG_Peripheral_OFF(uint32_t DBG_Periph);
#ifdef __cplusplus
}
#endif
#endif /* __N32G003_PWR_H */

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/**
* Copyright (c) 2022, Nations Technologies Inc.
*
* All rights reserved.
*
* This software is the exclusive property of Nations Technologies Inc. (Hereinafter
* referred to as NATIONS). This software, and the product of NATIONS described herein
* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties
* of the People's Republic of China and other applicable jurisdictions worldwide.
*
* NATIONS does not grant any license under its patents, copyrights, trademarks, or other
* intellectual property rights. Names and brands of third party may be mentioned or referred
* thereto (if any) for identification purposes only.
*
* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and
* improvements to this software at any time without notice. Please contact NATIONS and obtain
* the latest version of this software before placing orders.
* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes
* no responsibility for the accuracy and reliability of this software.
*
* It is the responsibility of the user of this software to properly design, program, and test
* the functionality and safety of any application made of this information and any resulting product.
* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or
* consequential damages arising in any way out of the use of this software or the Product.
*
* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any
* malfunction or failure of which may cause loss of human life, bodily injury or severe property
* damage. Such applications are deemed, "Insecure Usage".
*
* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS
* harmless from and against all claims, costs, damages, and other liabilities, arising from or related
* to any customer's Insecure Usage.
* Any express or implied warranty with regard to this software or the Product, including,but not
* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement
* are disclaimed to the fullest extent permitted by law.
* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe
* or otherwise distribute this software for any purposes, in whole or in part.
*
* NATIONS products and technologies shall not be used for or incorporated into any products or systems
* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations.
* User shall comply with any applicable export control laws and regulations promulgated and administered by
* the governments of any countries asserting jurisdiction over the parties or transactions.
**/
/**
*\*\file n32g003_rcc.h
*\*\author Nations
*\*\version v1.0.0
*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
*/
#ifndef __n32g003_RCC_H
#define __n32g003_RCC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "n32g003.h"
/** RCC_Exported_Types **/
typedef struct
{
uint32_t SysclkFreq; /* returns SYSCLK clock frequency expressed in Hz */
uint32_t HclkFreq; /* returns HCLK clock frequency expressed in Hz */
uint32_t PclkFreq; /* returns PCLK clock frequency expressed in Hz */
uint32_t Adc1MClkFreq; /* returns ADC1MHCLK clock frequency expressed in Hz */
uint32_t AdcClkFreq; /* returns ADCHCLK clock frequency expressed in Hz */
}RCC_ClocksType;
/** RCC registers bit mask **/
#define HSI_FREQ_48M (48000000)
#define HSI_FREQ_40M (40000000)
/** Register shift macro definition **/
#define RCC_CFG_AHBPRES_OFFSET (REG_BIT4_OFFSET)
#define RCC_CFG_APBPRES_OFFSET (REG_BIT8_OFFSET)
#define RCC_CFG2_ADC1MPRES_OFFSET (REG_BIT10_OFFSET)
/* RCC Flag Mask */
#define FLAG_Mask ((uint8_t)0x1F)
/** Internal High Speed clock trimming **/
#define RCC_HSITRIM_MASK (~RCC_HSICTRL_HSITRIM)
/** Internal Low Speed clock trimming **/
#define RCC_LSITRIM_MASK (~RCC_LSICTRL_LSITRIM)
/** SYS_clock_source **/
#define RCC_HSICLK_DIV_MASK (~RCC_CFG_SYSPRES)
#define RCC_HSICLK_DIV1 (RCC_CFG_SYSPRES_DIV1)
#define RCC_HSICLK_DIV2 (RCC_CFG_SYSPRES_DIV2)
#define RCC_HSICLK_DIV5 (RCC_CFG_SYSPRES_DIV5)
#define RCC_HSICLK_DIV6 (RCC_CFG_SYSPRES_DIV6)
/** AHB_clock_source **/
#define RCC_SYSCLK_DIV_MASK (~RCC_CFG_AHBPRES)
#define RCC_SYSCLK_DIV1 (RCC_CFG_AHBPRES_DIV1)
#define RCC_SYSCLK_DIV2 (RCC_CFG_AHBPRES_DIV2)
#define RCC_SYSCLK_DIV4 (RCC_CFG_AHBPRES_DIV4)
#define RCC_SYSCLK_DIV8 (RCC_CFG_AHBPRES_DIV8)
#define RCC_SYSCLK_DIV12 (RCC_CFG_AHBPRES_DIV12)
#define RCC_SYSCLK_DIV16 (RCC_CFG_AHBPRES_DIV16)
#define RCC_SYSCLK_DIV24 (RCC_CFG_AHBPRES_DIV24)
/** APB_clock_source **/
#define RCC_APB_DIV_MASK (~RCC_CFG_APBPRES)
#define RCC_HCLK_DIV1 (RCC_CFG_APBPRES_DIV1)
#define RCC_HCLK_DIV2 (RCC_CFG_APBPRES_DIV2)
#define RCC_HCLK_DIV4 (RCC_CFG_APBPRES_DIV4)
#define RCC_HCLK_DIV8 (RCC_CFG_APBPRES_DIV8)
#define RCC_HCLK_DIV16 (RCC_CFG_APBPRES_DIV16)
/** RCC_CFGR2_Config **/
#define RCC_TIM1_CLKSRC_MASK (~RCC_CFG2_TIM1CLKSEL)
#define RCC_TIM1_CLKSRC_PCLK (RCC_CFG2_TIM1CLKSEL_PCLK)
#define RCC_TIM1_CLKSRC_SYSCLK (RCC_CFG2_TIM1CLKSEL_SYSCLK)
#define RCC_ADC1MCLK_DIV_MASK (~RCC_CFG2_ADC1MPRES)
#define RCC_ADC1MCLK_DIV6 (RCC_CFG2_ADC1MPRES_DIV6)
#define RCC_ADC1MCLK_DIV12 (RCC_CFG2_ADC1MPRES_DIV12)
#define RCC_ADC1MCLK_DIV24 (RCC_CFG2_ADC1MPRES_DIV24)
#define RCC_ADC1MCLK_DIV40 (RCC_CFG2_ADC1MPRES_DIV40)
#define RCC_ADC1MCLK_DIV48 (RCC_CFG2_ADC1MPRES_DIV48)
#define RCC_ADC_DIV_MASK (~RCC_CFG2_ADCPRES)
#define RCC_ADC_DIV1 (RCC_CFG2_ADCPRES_DIV1)
#define RCC_ADC_DIV2 (RCC_CFG2_ADCPRES_DIV2)
#define RCC_ADC_DIV3 (RCC_CFG2_ADCPRES_DIV3)
#define RCC_ADC_DIV4 (RCC_CFG2_ADCPRES_DIV4)
#define RCC_ADC_DIV6 (RCC_CFG2_ADCPRES_DIV6)
#define RCC_ADC_DIV8 (RCC_CFG2_ADCPRES_DIV8)
#define RCC_ADC_DIV10 (RCC_CFG2_ADCPRES_DIV10)
#define RCC_ADC_DIV12 (RCC_CFG2_ADCPRES_DIV12)
#define RCC_ADC_DIV24 (RCC_CFG2_ADCPRES_DIV24)
#define RCC_ADC_DIV32 (RCC_CFG2_ADCPRES_DIV32)
#define RCC_ADC_DIV_OTHERS (RCC_CFG2_ADCPRES_OTHERS)
#define RCC_TIM6_CLKSRC_MASK (~RCC_CFG2_TIM6CLKSEL)
#define RCC_TIM6_CLKSRC_PCLK (RCC_CFG2_TIM6CLKSEL_PCLK)
#define RCC_TIM6_CLKSRC_LSI (RCC_CFG2_TIM6CLKSEL_LSI)
/** Peripheral Reset**/
#define RCC_RST_AFIORST (RCC_PRST_AFIORST)
#define RCC_RST_BEEPRST (RCC_PRST_BEEPRST)
#define RCC_RST_GPIOARST (RCC_PRST_GPIOARST)
#define RCC_RST_GPIOBRST (RCC_PRST_GPIOBRST)
#define RCC_RST_UART1RST (RCC_PRST_UART1RST)
#define RCC_RST_UART2RST (RCC_PRST_UART2RST)
#define RCC_RST_I2CRST (RCC_PRST_I2CRST)
#define RCC_RST_PWRRST (RCC_PRST_PWRRST)
#define RCC_RST_ADCRST (RCC_PRST_ADCRST)
#define RCC_RST_SPIRST (RCC_PRST_SPIRST)
#define RCC_RST_TIM1RST (RCC_PRST_TIM1RST)
#define RCC_RST_TIM3RST (RCC_PRST_TIM3RST)
#define RCC_RST_TIM6RST (RCC_PRST_TIM6RST)
#define RCC_RST_COMPRST (RCC_PRST_COMPRST)
/** Peripheral Enable **/
/** AHB_peripheral **/
#define RCC_AHB_PERIPH_CRC (RCC_AHBPCLKEN_CRCEN)
#define RCC_AHB_PERIPH_ADC (RCC_AHBPCLKEN_ADCEN)
/** APB_peripheral **/
#define RCC_APB_PERIPH_AFIO (RCC_APBPCLKEN_AFIOEN)
#define RCC_APB_PERIPH_BEEPER (RCC_APBPCLKEN_BEEPEREN)
#define RCC_APB_PERIPH_IOPA (RCC_APBPCLKEN_IOPAEN)
#define RCC_APB_PERIPH_IOPB (RCC_APBPCLKEN_IOPBEN)
#define RCC_APB_PERIPH_COMP (RCC_APBPCLKEN_COMPEN)
#define RCC_APB_PERIPH_COMP_FILT (RCC_APBPCLKEN_COMPFILTEN)
#define RCC_APB_PERIPH_UART1 (RCC_APBPCLKEN_UART1EN)
#define RCC_APB_PERIPH_UART2 (RCC_APBPCLKEN_UART2EN)
#define RCC_APB_PERIPH_I2C (RCC_APBPCLKEN_I2CEN)
#define RCC_APB_PERIPH_PWR (RCC_APBPCLKEN_PWREN)
#define RCC_APB_PERIPH_SPI (RCC_APBPCLKEN_SPIEN)
#define RCC_APB_PERIPH_TIM1 (RCC_APBPCLKEN_TIM1EN)
#define RCC_APB_PERIPH_TIM3 (RCC_APBPCLKEN_TIM3EN)
#define RCC_APB_PERIPH_TIM6 (RCC_APBPCLKEN_TIM6EN)
#define RCC_APB_PERIPH_IWDG (RCC_APBPCLKEN_IWDGEN)
/** RCC_Exported_Constants **/
/** Register shift macro definition **/
#define RCC_FLAG_OFFSET (REG_BIT5_OFFSET)
#define RCC_CTRL_HSITRIM_OFFSET (REG_BIT4_OFFSET)
#define RCC_CTRL_LSITRIM_OFFSET (REG_BIT2_OFFSET)
/** Clock_source_to_output_on_MCO_pin **/
#define RCC_MCO_MASK (~RCC_CFG_MCO)
#define RCC_MCO_NOCLK (RCC_CFG_MCO_NOCLK)
#define RCC_MCO_LSI (RCC_CFG_MCO_LSI)
#define RCC_MCO_HSI (RCC_CFG_MCO_HSI)
#define RCC_MCO_CLK_DIV_MASK (~RCC_CFG_MCOPRES)
#define RCC_MCO_CLK_DIV1 (RCC_CFG_MCOPRES_DIV1)
#define RCC_MCO_CLK_DIV2 (RCC_CFG_MCOPRES_DIV2)
#define RCC_MCO_CLK_DIV3 (RCC_CFG_MCOPRES_DIV3)
#define RCC_MCO_CLK_DIV4 (RCC_CFG_MCOPRES_DIV4)
#define RCC_MCO_CLK_DIV5 (RCC_CFG_MCOPRES_DIV5)
#define RCC_MCO_CLK_DIV6 (RCC_CFG_MCOPRES_DIV6)
#define RCC_MCO_CLK_DIV7 (RCC_CFG_MCOPRES_DIV7)
#define RCC_MCO_CLK_DIV8 (RCC_CFG_MCOPRES_DIV8)
#define RCC_MCO_CLK_DIV9 (RCC_CFG_MCOPRES_DIV9)
#define RCC_MCO_CLK_DIV10 (RCC_CFG_MCOPRES_DIV10)
#define RCC_MCO_CLK_DIV11 (RCC_CFG_MCOPRES_DIV11)
#define RCC_MCO_CLK_DIV12 (RCC_CFG_MCOPRES_DIV12)
#define RCC_MCO_CLK_DIV13 (RCC_CFG_MCOPRES_DIV13)
#define RCC_MCO_CLK_DIV14 (RCC_CFG_MCOPRES_DIV14)
#define RCC_MCO_CLK_DIV15 (RCC_CFG_MCOPRES_DIV15)
#define RCC_MCO_CLK_DIV32 (RCC_CFG_MCOPRES_DIV32)
/** RCC_Flag **/
#define RCC_FLAG_HSI40MRDF ((uint8_t)0x20)
#define RCC_FLAG_HSI48MRDF ((uint8_t)0x21)
#define RCC_FLAG_LSIRDF ((uint8_t)0x41)
#define RCC_FLAG_LSIDETFF ((uint8_t)0x58)
#define RCC_FLAG_PINRST ((uint8_t)0x63)
#define RCC_FLAG_PORRST ((uint8_t)0x64)
#define RCC_FLAG_SFTRST ((uint8_t)0x65)
#define RCC_FLAG_IWDGRST ((uint8_t)0x66)
#define RCC_FLAG_LVRRST ((uint8_t)0x67)
#define RCC_FLAG_LPWRRST ((uint8_t)0x68)
#define RCC_FLAG_EMCCLAMPF ((uint8_t)0x6B)
/** RCC Reset Flag clear**/
#define RCC_REMOVE_RESET_FLAG (RCC_CTRLSTS_RMRSTF)
void RCC_Reset(void);
void RCC_HSI_Calibration_Value_Set(uint8_t calibration_value);
void RCC_LSI_Calibration_Value_Set(uint8_t calibration_value);
void RCC_Sysclk_Config(uint32_t HSI_div);
void RCC_Hclk_Config(uint32_t sysclk_div);
void RCC_Pclk_Config(uint32_t hclk_div);
void RCC_TIM1_Clock_Config(uint32_t timer_clksrc);
void RCC_ADC_1M_Clock_Config(uint32_t ADC1M_prescaler);
void RCC_ADC_Clock_Config(uint32_t ADC_prescaler);
void RCC_TIM6_Clock_Config(uint32_t timer_clksrc);
void RCC_Clocks_Frequencies_Value_Get(RCC_ClocksType* RCC_clocks);
void RCC_AHB_Peripheral_Clock_Enable(uint32_t AHB_periph);
void RCC_AHB_Peripheral_Clock_Disable(uint32_t AHB_periph);
void RCC_APB_Peripheral_Clock_Enable(uint32_t APB_periph);
void RCC_APB_Peripheral_Clock_Disable(uint32_t APB_periph);
void RCC_Peripheral_Reset(uint32_t Periph);
void RCC_MCO_Prescaler_Config(uint32_t MCO_prescaler);
void RCC_MCO_Source_Config(uint32_t MCO_source);
FlagStatus RCC_Flag_Status_Get(uint8_t RCC_flag);
void RCC_Reset_Flag_Clear(void);
void RCC_EMC_Reset_Disable(void);
void RCC_EMC_Reset_Enable(void);
void RCC_EMC_Detect_Disable(void);
void RCC_EMC_Detect_Enable(void);
void RCC_LSI_Detect_Disable(void);
void RCC_LSI_Detect_Enable(void);
uint16_t RCC_LSI_Clocks_Frequencies_Get(void);
#ifdef __cplusplus
}
#endif
#endif /* __N32G003_RCC_H__ */

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/**
* Copyright (c) 2022, Nations Technologies Inc.
*
* All rights reserved.
*
* This software is the exclusive property of Nations Technologies Inc. (Hereinafter
* referred to as NATIONS). This software, and the product of NATIONS described herein
* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties
* of the People's Republic of China and other applicable jurisdictions worldwide.
*
* NATIONS does not grant any license under its patents, copyrights, trademarks, or other
* intellectual property rights. Names and brands of third party may be mentioned or referred
* thereto (if any) for identification purposes only.
*
* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and
* improvements to this software at any time without notice. Please contact NATIONS and obtain
* the latest version of this software before placing orders.
* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes
* no responsibility for the accuracy and reliability of this software.
*
* It is the responsibility of the user of this software to properly design, program, and test
* the functionality and safety of any application made of this information and any resulting product.
* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or
* consequential damages arising in any way out of the use of this software or the Product.
*
* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any
* malfunction or failure of which may cause loss of human life, bodily injury or severe property
* damage. Such applications are deemed, "Insecure Usage".
*
* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS
* harmless from and against all claims, costs, damages, and other liabilities, arising from or related
* to any customer's Insecure Usage.
* Any express or implied warranty with regard to this software or the Product, including,but not
* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement
* are disclaimed to the fullest extent permitted by law.
* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe
* or otherwise distribute this software for any purposes, in whole or in part.
*
* NATIONS products and technologies shall not be used for or incorporated into any products or systems
* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations.
* User shall comply with any applicable export control laws and regulations promulgated and administered by
* the governments of any countries asserting jurisdiction over the parties or transactions.
**/
/**
*\*\file n32g003_spi.h
*\*\author Nations
*\*\version v1.0.0
*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
**/
#ifndef __N32G003_SPI_H__
#define __N32G003_SPI_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "n32g003.h"
/** SPI Init structure definition **/
typedef struct
{
uint16_t DataDirection; /* Specifies the SPI unidirectional or bidirectional data mode */
uint16_t SpiMode; /* Specifies the SPI operating mode */
uint16_t DataLen; /* Specifies the SPI data size */
uint16_t CLKPOL; /* Specifies the serial clock steady state */
uint16_t CLKPHA; /* Specifies the clock active edge for the bit capture */
uint16_t NSS; /* Specifies whether the NSS signal is managed by
hardware (NSS pin) or by software using the SSI bit */
uint16_t BaudRatePres; /* Specifies the Baud Rate prescaler value which will be
used to configure the transmit and receive SCK clock */
uint16_t FirstBit; /* Specifies whether data transfers start from MSB or LSB bit */
} SPI_InitType;
/** SPI_data_direction **/
#define SPI_DATADIRECTION_MASK (~(SPI_CTRL1_RONLY | SPI_CTRL1_BIDIROEN | SPI_CTRL1_BIDIRMODE)) /* direction [15:14] and [10] bits Mask */
#define SPI_DIR_DOUBLELINE_FULLDUPLEX ((uint16_t)0x0000)
#define SPI_DIR_DOUBLELINE_RONLY_TX ((uint16_t)0x0000)
#define SPI_DIR_DOUBLELINE_RONLY_RX (SPI_CTRL1_RONLY)
#define SPI_DIR_SINGLELINE_RX (SPI_CTRL1_BIDIRMODE)
#define SPI_DIR_SINGLELINE_TX (SPI_CTRL1_BIDIRMODE | SPI_CTRL1_BIDIROEN)
/** SPI mode **/
#define SPI_MODE_MASK (~SPI_CTRL1_MSEL) /* MSEL bits Mask */
#define SPI_MODE_MASTER (SPI_CTRL1_MSEL)
#define SPI_MODE_SLAVE ((uint16_t)0x0000)
/** SPI_data_size **/
#define SPI_DATALEN_MASK (~SPI_CTRL1_DATFF) /* DATFF bits Mask */
#define SPI_DATA_SIZE_16BITS (SPI_CTRL1_DATFF)
#define SPI_DATA_SIZE_8BITS ((uint16_t)0x0000)
/** SPI_Clock_Polarity **/
#define SPI_CLKPOL_MASK (~SPI_CTRL1_CLKPOL) /* CLKPOL bits Mask */
#define SPI_CLKPOL_LOW ((uint16_t)0x0000)
#define SPI_CLKPOL_HIGH (SPI_CTRL1_CLKPOL)
/** SPI_Clock_Phase **/
#define SPI_CLKPHA_MASK (~SPI_CTRL1_CLKPHA) /* CLKPHA bits Mask */
#define SPI_CLKPHA_FIRST_EDGE ((uint16_t)0x0000)
#define SPI_CLKPHA_SECOND_EDGE (SPI_CTRL1_CLKPHA)
/** SPI_Slave_Select_management **/
#define SPI_NSS_MASK (~SPI_CTRL1_SSMEN) /* SSMEN bits Mask */
#define SPI_NSS_SOFT (SPI_CTRL1_SSMEN)
#define SPI_NSS_HARD ((uint16_t)0x0000)
#define SPI_NSS_OUTPUT_ENABLE SPI_CTRL2_SSOEN
#define SPI_NSS_OUTPUT_DISABLE (~SPI_CTRL2_SSOEN)
/** SPI_BaudRate_Prescaler **/
#define SPI_BAUDRATEPRES_MASK (~SPI_CTRL1_BR) /* BR[2:0] bits Mask */
#define SPI_BR_PRESCALER_2 ((uint16_t)0x0000)
#define SPI_BR_PRESCALER_4 (SPI_CTRL1_BR0)
#define SPI_BR_PRESCALER_8 (SPI_CTRL1_BR1)
#define SPI_BR_PRESCALER_16 (SPI_CTRL1_BR1 | SPI_CTRL1_BR0)
#define SPI_BR_PRESCALER_32 (SPI_CTRL1_BR2)
#define SPI_BR_PRESCALER_64 (SPI_CTRL1_BR2 | SPI_CTRL1_BR0)
#define SPI_BR_PRESCALER_128 (SPI_CTRL1_BR2 | SPI_CTRL1_BR1)
#define SPI_BR_PRESCALER_256 (SPI_CTRL1_BR2 | SPI_CTRL1_BR1 | SPI_CTRL1_BR0)
/** SPI_MSB_LSB_transmission **/
#define SPI_FIRSTBIT_MASK (~SPI_CTRL1_LSBFF) /* LSBFF bits Mask */
#define SPI_FB_MSB ((uint16_t)0x0000)
#define SPI_FB_LSB (SPI_CTRL1_LSBFF)
/** SPI Converter **/
#define SPI_TURN_ON (SPI_CTRL1_SPIEN) /* SPIEN ON bit */
#define SPI_TURN_OFF (~SPI_CTRL1_SPIEN) /* SPIEN ON bit Mask */
/** SPI_NSS_internal_software_management **/
#define SPI_NSS_HIGH (SPI_CTRL1_SSEL)
#define SPI_NSS_LOW (~SPI_CTRL1_SSEL)
/** SPI_flags_definition **/
#define SPI_FLAG_RNE (SPI_STS_RNE)
#define SPI_FLAG_TE (SPI_STS_TE)
#define SPI_FLAG_MODERR (SPI_STS_MODERR)
#define SPI_FLAG_OVER (SPI_STS_OVER)
#define SPI_FLAG_BUSY (SPI_STS_BUSY)
#define SPI_INT_RNE (SPI_CTRL2_RNEINTEN)
#define SPI_INT_TE (SPI_CTRL2_TEINTEN)
#define SPI_INT_ERR (SPI_CTRL2_ERRINTEN)
#define SPI_INT_FLAG_RNE (SPI_STS_RNE)
#define SPI_INT_FLAG_TE (SPI_STS_TE)
#define SPI_INT_FLAG_MODERR (SPI_STS_MODERR)
#define SPI_INT_FLAG_OVER (SPI_STS_OVER)
#define SPI_INT_FLAG_ERR (SPI_STS_MODERR | SPI_STS_OVER)
/** SPI Macro Definition End **/
/** SPI Driving Functions Declaration **/
void SPI_Reset(void);
void SPI_ON(void);
void SPI_OFF(void);
void SPI_Initializes_Structure(SPI_InitType* SPI_InitStruct);
void SPI_DataDirection_Config(uint16_t DataDirection);
void SPI_SpiMode_Config(uint16_t SpiMode);
void SPI_DataLen_Config(uint16_t DataLen);
void SPI_CLKPOL_Config(uint16_t CLKPOL);
void SPI_CLKPHA_Config(uint16_t CLKPHA);
void SPI_NSS_Config(uint16_t NSS);
void SPI_BaudRatePres_Config(uint16_t BaudRatePres);
void SPI_FirstBit_Config(uint16_t FirstBit);
void SPI_Initializes(SPI_InitType* SPI_InitStruct);
void SPI_Set_Nss_Level(uint16_t SPI_NSS_Internal_Soft);
void SPI_NSS_Output_Enable(void);
void SPI_NSS_Output_Disable(void);
void SPI_Data_Transmit(uint16_t Data);
uint16_t SPI_Data_Get(void);
void SPI_Interrupts_Enable(uint8_t spi_interrupt);
void SPI_Interrupts_Disable(uint8_t spi_interrupt);
FlagStatus SPI_Flag_Status_Get(uint8_t spi_flag);
FlagStatus SPI_Interrupt_Flag_Status_Get(uint16_t spi_flag);
void SPI_OVER_Flag_Clear(void);
#ifdef __cplusplus
}
#endif
#endif /*__N32G003_SPI_H__ */

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/**
* Copyright (c) 2022, Nations Technologies Inc.
*
* All rights reserved.
*
* This software is the exclusive property of Nations Technologies Inc. (Hereinafter
* referred to as NATIONS). This software, and the product of NATIONS described herein
* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties
* of the People's Republic of China and other applicable jurisdictions worldwide.
*
* NATIONS does not grant any license under its patents, copyrights, trademarks, or other
* intellectual property rights. Names and brands of third party may be mentioned or referred
* thereto (if any) for identification purposes only.
*
* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and
* improvements to this software at any time without notice. Please contact NATIONS and obtain
* the latest version of this software before placing orders.
* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes
* no responsibility for the accuracy and reliability of this software.
*
* It is the responsibility of the user of this software to properly design, program, and test
* the functionality and safety of any application made of this information and any resulting product.
* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or
* consequential damages arising in any way out of the use of this software or the Product.
*
* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any
* malfunction or failure of which may cause loss of human life, bodily injury or severe property
* damage. Such applications are deemed, "Insecure Usage".
*
* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS
* harmless from and against all claims, costs, damages, and other liabilities, arising from or related
* to any customer's Insecure Usage.
* Any express or implied warranty with regard to this software or the Product, including,but not
* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement
* are disclaimed to the fullest extent permitted by law.
* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe
* or otherwise distribute this software for any purposes, in whole or in part.
*
* NATIONS products and technologies shall not be used for or incorporated into any products or systems
* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations.
* User shall comply with any applicable export control laws and regulations promulgated and administered by
* the governments of any countries asserting jurisdiction over the parties or transactions.
**/
/**
*\*\file n32g003_tim.h
*\*\author Nations
*\*\version v1.0.0
*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
**/
#ifndef __N32G003_TIM_H__
#define __N32G003_TIM_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "n32g003.h"
#include "stdbool.h"
/**
*\*\brief TIM Time Base Init structure definition
*\*\note This structure is used with all TIMx except for TIM6 and TIM7.
**/
typedef struct
{
uint16_t Prescaler; /* Specifies the prescaler value used to divide the TIM clock.
This parameter can be a number between 0x0000 and 0xFFFF */
uint16_t CntMode; /* Specifies the counter mode.
This parameter can be a value of TIM_Counter_Mode */
uint16_t Period; /* Specifies the period value to be loaded into the active
Auto-Reload Register at the next update event.
This parameter must be a number between 0x0000 and 0xFFFF. */
uint16_t ClkDiv; /* Specifies the clock division.
This parameter can be a value of TIM_Clock_Division_CKD */
uint8_t RepetCnt; /* Specifies the repetition counter value. Each time the REPCNT downcounter
reaches zero, an update event is generated and counting restarts
from the REPCNT value (N).
This means in PWM mode that (N+1) corresponds to:
- the number of PWM periods in edge-aligned mode
- the number of half PWM period in center-aligned mode
This parameter must be a number between 0x00 and 0xFF.
@note This parameter is valid only for TIM1 and TIM8. */
bool CapCh1Sel; /* channel 1 select capture in from comp if 1, from IOM if 0
Tim1,Tim3 valid*/
bool CapEtrClrFromCompEn; /* etr clearref select from comp if 1, from ETR IOM if 0
Tim1,Tim3 valid*/
bool CapEtrSelFromTscEn;
} TIM_TimeBaseInitType;
/**
*\*\brief TIM Output Compare Init structure definition
**/
typedef struct
{
uint16_t OcMode; /* Specifies the TIM mode.
This parameter can be a value of TIM_Output_Compare_and_PWM_modes */
uint16_t OutputState; /* Specifies the TIM Output Compare state.
This parameter can be a value of TIM_Output_Compare_state */
uint16_t OutputNState; /* Specifies the TIM complementary Output Compare state.
This parameter can be a value of TIM_Output_Compare_N_state
- note This parameter is valid only for TIM1. */
uint16_t Pulse; /* Specifies the pulse value to be loaded into the Capture Compare Register.
This parameter can be a number between 0x0000 and 0xFFFF */
uint16_t OcPolarity; /* Specifies the output polarity.
This parameter can be a value of TIM_Output_Compare_Polarity */
uint16_t OcNPolarity; /* Specifies the complementary output polarity.
This parameter can be a value of TIM_Output_Compare_N_Polarity
- note This parameter is valid only for TIM1. */
uint16_t OcIdleState; /* Specifies the TIM Output Compare pin state during Idle state.
This parameter can be a value of TIM_Output_Compare_Idle_State
- note This parameter is valid only for TIM1. */
uint16_t OcNIdleState; /* Specifies the TIM Output Compare pin state during Idle state.
This parameter can be a value of TIM_Output_Compare_N_Idle_State
- note This parameter is valid only for TIM1. */
} OCInitType;
/**
*\*\brief TIM Input Capture Init structure definition
**/
typedef struct
{
uint16_t Channel; /*! Specifies the TIM channel.This parameter can be a value of Channel */
uint16_t IcPolarity; /* Specifies the active edge of the input signal. */
uint16_t IcSelection; /* Specifies the input. */
uint16_t IcPrescaler; /* Specifies the Input Capture Prescaler. */
uint16_t IcFilter; /* Specifies the input capture filter. */
} TIM_ICInitType;
/**
*\*\brief BKDT structure definition
*\*\note This structure is used only with TIM1 and TIM8.
**/
typedef struct
{
uint16_t OssrState; /* Specifies the Off-State selection used in Run mode.
This parameter can be a value of OSSR_Off_State_Selection_for_Run_mode_state */
uint16_t OssiState; /* Specifies the Off-State used in Idle state.
This parameter can be a value of OSSI_Off_State_Selection_for_Idle_mode_state */
uint16_t LockLevel; /* Specifies the LOCK level parameters.
This parameter can be a value of Lock_level */
uint16_t DeadTime; /* Specifies the delay time between the switching-off and the
switching-on of the outputs.
This parameter can be a number between 0x00 and 0xFF */
uint16_t Break; /* Specifies whether the TIM Break input is enabled or not.
This parameter can be a value of Break_Input_enable_disable */
uint16_t BreakPolarity; /* Specifies the TIM Break Input pin polarity.
This parameter can be a value of Break_Polarity */
uint16_t AutomaticOutput; /* Specifies whether the TIM Automatic Output feature is enabled or not.
This parameter can be a value of TIM_AOE_Bit_Set_Reset */
bool IomBreakEn; /* EXTENDMODE valid, open iom as break in*/
bool LockUpBreakEn; /* EXTENDMODE valid, open lockup(hardfault) as break in*/
bool PvdBreakEn; /* EXTENDMODE valid, open pvd(sys voltage too high or too low) as break in*/
} TIM_BDTRInitType;
#define TIM_REG16_BIT_ZERO ((uint16_t)0x0000)
#define TIM_REG32_BIT_ZERO ((uint32_t)0x00000000)
#define TIM_AR_PRELOAD_MASK (TIM_CTRL1_ARPEN)
/** TIM_AR_PRELOAD **/
#define TIM_AR_PRELOAD_ENABLE (TIM_CTRL1_ARPEN)
#define TIM_AR_PRELOAD_DISABLE (TIM_REG32_BIT_ZERO)
#define TIM_UPRS_MASK (TIM_CTRL1_UPRS)
/** TIM_Update_Source **/
#define TIM_UPRS_GLOBAL (TIM_REG32_BIT_ZERO)
#define TIM_UPRS_REGULAR (TIM_CTRL1_UPRS)
#define TIM_UPDATE_SRC_GLOBAL (TIM_REG16_BIT_ZERO) /* Source of update is the counter overflow/underflow \
or the setting of UG bit, or an update generation \
through the slave mode controller. */
#define TIM_UPDATE_SRC_REGULAR ((uint16_t)0x0001) /* Source of update is counter overflow/underflow. */
#define TIM_UPDIS_MASK (TIM_CTRL1_UPDIS)
/** TIM_Update_Disable **/
#define TIM_UPDATE_EVENT_DISABLE (TIM_CTRL1_UPDIS)
#define TIM_UPDATE_EVENT_ENABLE (TIM_REG32_BIT_ZERO)
#define TIM_ON_MASK (TIM_CTRL1_CNTEN)
/** TIM_On **/
#define TIM_ON (TIM_CTRL1_CNTEN)
/* TIM_Break_In_Source */
#define TIM_LOCKUP_AS_BREAK_IN (TIM_CTRL1_LBKPEN)
#define TIM_PVD_AS_BREAK_IN (TIM_CTRL1_PBKPEN)
#define TIM_COMP_AS_BREAK_IN (TIM_CTRL1_IOMBKPEN)
#define TIM_CCUSEL_MASK (TIM_CTRL2_CCUSEL)
/** TIM_CCUSEL **/
#define TIM_CCUSEL_COM_AND_TRIG (TIM_CTRL2_CCUSEL)
#define TIM_CCUSEL_COM (TIM_REG32_BIT_ZERO)
/** TIM_CCPCTL **/
#define TIM_CCPCTL_MASK (TIM_CTRL2_CCPCTL)
#define TIM_CCPCTL_PRELOAD (TIM_CTRL2_CCPCTL)
#define TIM_CCPCTL_NOT_PRELOAD (TIM_REG32_BIT_ZERO)
/** TIM_REPCNT MASK**/
#define TIM_REPCNT_MASK (TIM_REPCNT_REPCNT)
#define TIM_OC1MODE_MASK (TIM_CCMOD1_OC1MD)
#define TIM_OC2MODE_MASK (TIM_CCMOD1_OC2MD)
#define TIM_OC3MODE_MASK (TIM_CCMOD2_OC3MD)
#define TIM_OC4MODE_MASK (TIM_CCMOD2_OC4MD)
#define TIM_OC5MODE_MASK (TIM_CCMOD3_OC5MD)
/** TIM_Output_Compare_and_PWM_modes**/
#define TIM_OCMODE_TIMING (TIM_REG16_BIT_ZERO)
#define TIM_OCMODE_ACTIVE (TIM_CCMOD1_OC1MD_0)
#define TIM_OCMODE_INACTIVE (TIM_CCMOD1_OC1MD_1)
#define TIM_OCMODE_TOGGLE (TIM_CCMOD1_OC1MD_0 | TIM_CCMOD1_OC1MD_1)
#define TIM_OCMODE_PWM1 (TIM_CCMOD1_OC1MD_2 | TIM_CCMOD1_OC1MD_1)
#define TIM_OCMODE_PWM2 (TIM_CCMOD1_OC1MD_2 | TIM_CCMOD1_OC1MD_1 | TIM_CCMOD1_OC1MD_2 | TIM_CCMOD1_OC1MD_0)
#define TIM_FORCED_ACTION_ACTIVE (TIM_CCMOD1_OC1MD_2 | TIM_CCMOD1_OC1MD_0)
#define TIM_FORCED_ACTION_INACTIVE (TIM_CCMOD1_OC1MD_2)
#define TIM_OPMODE_MASK (TIM_CTRL1_ONEPM)
/** TIM_One_Pulse_Mode **/
#define TIM_OPMODE_SINGLE (TIM_CTRL1_ONEPM)
#define TIM_OPMODE_REPET (TIM_REG16_BIT_ZERO)
/** Channel **/
#define TIM_CH_1 ((uint16_t)0x0000)
#define TIM_CH_2 ((uint16_t)0x0004)
#define TIM_CH_3 ((uint16_t)0x0008)
#define TIM_CH_4 ((uint16_t)0x000C)
#define TIM_CH_5 ((uint16_t)0x0010)
#define TIM_CLK_DIV_MASK (TIM_CTRL1_CLKD)
/** TIM_Clock_Division_CKD **/
#define TIM_CLK_DIV1 (TIM_REG16_BIT_ZERO)
#define TIM_CLK_DIV2 (TIM_CTRL1_CLKD_0)
#define TIM_CLK_DIV4 (TIM_CTRL1_CLKD_1)
#define TIM_CNT_MODE_MASK (TIM_CTRL1_DIR | TIM_CTRL1_CAMSEL)
/** TIM_Counter_Mode **/
#define TIM_CNT_MODE_UP (TIM_REG16_BIT_ZERO)
#define TIM_CNT_MODE_DOWN (TIM_CTRL1_DIR)
#define TIM_CNT_MODE_CENTER_ALIGN1 (TIM_CTRL1_CAMSEL_0)
#define TIM_CNT_MODE_CENTER_ALIGN2 (TIM_CTRL1_CAMSEL_1)
#define TIM_CNT_MODE_CENTER_ALIGN3 (TIM_CTRL1_CAMSEL_1 | TIM_CTRL1_CAMSEL_0)
/** TIM_CHxSEL **/
#define TIM_CH1_SEL (TIM_CTRL1_C1SEL)
/** TIM_OCREF_CLEAR_SEL **/
#define TIM_OCREF_CLEAR_SEL (TIM_CTRL1_CLRSEL)
/** TIM_TI1_SEL **/
#define TIM_TI1_SEL (TIM_CTRL2_TI1SEL)
/** TIM_ETR_Selection **/
#define TIM_ETR_SEL (TIM_CTRL2_TSCSEL)
#define TIM_OC_POLARITY_MASK (TIM_CCEN_CC1P)
/** TIM_Output_Compare_Polarity **/
#define TIM_OC_POLARITY_HIGH (TIM_REG16_BIT_ZERO)
#define TIM_OC_POLARITY_LOW (TIM_CCEN_CC1P)
#define TIM_OCN_POLARITY_MASK (TIM_CCEN_CC1NP)
/** TIM_Output_Compare_N_Polarity **/
#define TIM_OCN_POLARITY_HIGH (TIM_REG16_BIT_ZERO)
#define TIM_OCN_POLARITY_LOW (TIM_CCEN_CC1NP)
/** TIM_Output_Compare_state **/
#define TIM_OUTPUT_STATE_DISABLE (TIM_REG16_BIT_ZERO)
#define TIM_OUTPUT_STATE_ENABLE (TIM_CCEN_CC1EN)
/** TIM_Output_Compare_N_state **/
#define TIM_OUTPUT_NSTATE_DISABLE (TIM_REG16_BIT_ZERO)
#define TIM_OUTPUT_NSTATE_ENABLE (TIM_CCEN_CC1NEN)
/** TIM_Capture_Compare_state **/
#define TIM_CAP_CMP_ENABLE (TIM_CCEN_CC1EN)
#define TIM_CAP_CMP_DISABLE (TIM_REG16_BIT_ZERO)
/** TIM_Capture_Compare_N_state **/
#define TIM_CAP_CMP_N_ENABLE (TIM_CCEN_CC1NEN)
#define TIM_CAP_CMP_N_DISABLE (TIM_REG16_BIT_ZERO)
/** Break_Input_enable_disable **/
#define TIM_BREAK_IN_ENABLE (TIM_BKDT_BKEN)
#define TIM_BREAK_IN_DISABLE (TIM_REG16_BIT_ZERO)
/** Break_Polarity **/
#define TIM_BREAK_POLARITY_LOW (TIM_REG16_BIT_ZERO)
#define TIM_BREAK_POLARITY_HIGH (TIM_BKDT_BKP)
/** TIM_AOEN_Bit_Set_Reset **/
#define TIM_AUTO_OUTPUT_ENABLE (TIM_BKDT_AOEN)
#define TIM_AUTO_OUTPUT_DISABLE (TIM_REG16_BIT_ZERO)
/** TIM_MOEN_Bit_Set_Reset **/
#define TIM_MAIN_OUTPUT_ENABLE (TIM_BKDT_MOEN)
#define TIM_MAIN_OUTPUT_DISABLE (TIM_REG16_BIT_ZERO)
/** Lock_level **/
#define TIM_LOCK_LEVEL_OFF (TIM_REG16_BIT_ZERO)
#define TIM_LOCK_LEVEL_1 (TIM_BKDT_LCKCFG_0)
#define TIM_LOCK_LEVEL_2 (TIM_BKDT_LCKCFG_1)
#define TIM_LOCK_LEVEL_3 (TIM_BKDT_LCKCFG_1 | TIM_BKDT_LCKCFG_0)
/** OSSI_Off_State_Selection_for_Idle_mode_state **/
#define TIM_OSSI_STATE_ENABLE (TIM_BKDT_OSSI)
#define TIM_OSSI_STATE_DISABLE (TIM_REG16_BIT_ZERO)
/** OSSR_Off_State_Selection_for_Run_mode_state **/
#define TIM_OSSR_STATE_ENABLE (TIM_BKDT_OSSR)
#define TIM_OSSR_STATE_DISABLE (TIM_REG16_BIT_ZERO)
#define TIM_OC1_IDLE_STATE_MASK (TIM_CTRL2_OI1)
#define TIM_OC2_IDLE_STATE_MASK (TIM_CTRL2_OI2)
#define TIM_OC3_IDLE_STATE_MASK (TIM_CTRL2_OI3)
#define TIM_OC4_IDLE_STATE_MASK (TIM_CTRL2_OI4)
#define TIM_OC5_IDLE_STATE_MASK (TIM_CTRL2_OI5)
/** TIM_Output_Compare_Idle_State **/
#define TIM_OC_IDLE_STATE_SET (TIM_CTRL2_OI1)
#define TIM_OC_IDLE_STATE_RESET (TIM_REG16_BIT_ZERO)
#define TIM_OC1N_IDLE_STATE_MASK (TIM_CTRL2_OI1N)
#define TIM_OC2N_IDLE_STATE_MASK (TIM_CTRL2_OI2N)
#define TIM_OC3N_IDLE_STATE_MASK (TIM_CTRL2_OI3N)
/** TIM_Output_Compare_N_Idle_State **/
#define TIM_OCN_IDLE_STATE_SET (TIM_CTRL2_OI1N)
#define TIM_OCN_IDLE_STATE_RESET (TIM_REG16_BIT_ZERO)
/** TIM_Input_Capture_Polarity **/
#define TIM_IC_POLARITY_RISING (TIM_REG16_BIT_ZERO)
#define TIM_IC_POLARITY_FALLING (TIM_CCEN_CC1P)
#define TIM_IC_POLARITY_BOTHEDGE (TIM_CCEN_CC1P | TIM_CCEN_CC1NP)
#define TIM_IC1_SELECTION_MASK (TIM_CCMOD1_CC1SEL)
#define TIM_IC2_SELECTION_MASK (TIM_CCMOD1_CC2SEL)
#define TIM_IC3_SELECTION_MASK (TIM_CCMOD2_CC3SEL)
#define TIM_IC4_SELECTION_MASK (TIM_CCMOD2_CC4SEL)
/** TIM_Input_Capture_Selection **/
#define TIM_IC_SELECTION_DIRECTTI (TIM_CCMOD1_CC1SEL_0) /* TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */
#define TIM_IC_SELECTION_INDIRECTTI (TIM_CCMOD1_CC1SEL_1) /* TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively. */
#define TIM_IC_SELECTION_TRC (TIM_CCMOD1_CC1SEL_1 | TIM_CCMOD1_CC1SEL_0) /* TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
/** TIM_Input_Capture1_Filter **/
#define TIM_IC1_FILTER_MASK (TIM_CCMOD1_IC1F)
/** TIM_Input_Capture2_Filter **/
#define TIM_IC2_FILTER_MASK (TIM_CCMOD1_IC2F)
/** TIM_Input_Capture3_Filter **/
#define TIM_IC3_FILTER_MASK (TIM_CCMOD2_IC3F)
/** TIM_Input_Capture4_Filter **/
#define TIM_IC4_FILTER_MASK (TIM_CCMOD2_IC4F)
#define TIM_IC1_PSC_MASK (TIM_CCMOD1_IC1PSC)
#define TIM_IC2_PSC_MASK (TIM_CCMOD1_IC2PSC)
#define TIM_IC3_PSC_MASK (TIM_CCMOD2_IC3PSC)
#define TIM_IC4_PSC_MASK (TIM_CCMOD2_IC4PSC)
/** TIM_Input_Capture_Prescaler **/
#define TIM_IC_PSC_DIV1 (TIM_REG16_BIT_ZERO)
#define TIM_IC_PSC_DIV2 (TIM_CCMOD1_IC1PSC_0) /* Capture performed once every 2 events. */
#define TIM_IC_PSC_DIV4 (TIM_CCMOD1_IC1PSC_1) /* Capture performed once every 4 events. */
#define TIM_IC_PSC_DIV8 (TIM_CCMOD1_IC1PSC_1 | TIM_CCMOD1_IC1PSC_0) /* Capture performed once every 8 events. */
/** TIM_interrupt_sources **/
#define TIM_INT_UPDATE (TIM_STS_UDITF)
#define TIM_INT_CC1 (TIM_STS_CC1ITF)
#define TIM_INT_CC2 (TIM_STS_CC2ITF)
#define TIM_INT_CC3 (TIM_STS_CC3ITF)
#define TIM_INT_CC4 (TIM_STS_CC4ITF)
#define TIM_INT_COM (TIM_STS_COMITF)
#define TIM_INT_TRIG (TIM_STS_TITF)
#define TIM_INT_BREAK (TIM_STS_BITF)
/** TIM_External_Trigger_Prescaler **/
#define TIM_EXT_TRG_PSC_MASK (TIM_SMCTRL_EXTPS)
#define TIM_EXT_TRG_PSC_OFF (TIM_REG16_BIT_ZERO)
#define TIM_EXT_TRG_PSC_DIV2 (TIM_SMCTRL_EXTPS_0)
#define TIM_EXT_TRG_PSC_DIV4 (TIM_SMCTRL_EXTPS_1)
#define TIM_EXT_TRG_PSC_DIV8 (TIM_SMCTRL_EXTPS_1 | TIM_SMCTRL_EXTPS_0)
#define TIM_TRIG_SEL_MASK (TIM_SMCTRL_TSEL)
/** TIM_Internal_Trigger_Selection **/
#define TIM_TRIG_SEL_IN_TR0 (TIM_REG16_BIT_ZERO)
#define TIM_TRIG_SEL_IN_TR1 (TIM_SMCTRL_TSEL_0)
#define TIM_TRIG_SEL_IN_TR2 (TIM_SMCTRL_TSEL_1)
#define TIM_TRIG_SEL_IN_TR3 (TIM_SMCTRL_TSEL_1 | TIM_SMCTRL_TSEL_0)
#define TIM_TRIG_SEL_TI1F_ED (TIM_SMCTRL_TSEL_2)
#define TIM_TRIG_SEL_TI1FP1 (TIM_SMCTRL_TSEL_2 | TIM_SMCTRL_TSEL_0)
#define TIM_TRIG_SEL_TI2FP2 (TIM_SMCTRL_TSEL_2 | TIM_SMCTRL_TSEL_1)
#define TIM_TRIG_SEL_ETRF (TIM_SMCTRL_TSEL_2 | TIM_SMCTRL_TSEL_1 | TIM_SMCTRL_TSEL_0)
/** TIM_TIx_External_Clock_Source **/
#define TIM_EXT_CLK_SRC_TI1 (TIM_SMCTRL_TSEL_2 | TIM_SMCTRL_TSEL_0)
#define TIM_EXT_CLK_SRC_TI2 (TIM_SMCTRL_TSEL_2 | TIM_SMCTRL_TSEL_1)
#define TIM_EXT_CLK_SRC_TI1ED (TIM_SMCTRL_TSEL_2)
/** TIM_External_Trigger_Polarity **/
#define TIM_EXT_TRIG_POLARITY_INVERTED (TIM_SMCTRL_EXTP)
#define TIM_EXT_TRIG_POLARITY_NONINVERTED (TIM_REG16_BIT_ZERO)
/** TIM_TIx_External_Clock_Filter **/
#define TIM_EXT_TRIG_FILTER_MASK (TIM_SMCTRL_EXTF)
/** TIM_External_Clock_Mode2 **/
#define TIM_EXT_CLOCK_MODE2_ENABLE (TIM_SMCTRL_EXCEN)
#define TIM_PSC_RELOAD_MODE_MASK (TIM_EVTGEN_UDGN)
/** TIM_Prescaler_Reload_Mode **/
#define TIM_PSC_RELOAD_MODE_UPDATE (TIM_REG16_BIT_ZERO)
#define TIM_PSC_RELOAD_MODE_IMMEDIATE (TIM_EVTGEN_UDGN)
/** TIM_Event_Source **/
#define TIM_EVT_SRC_UPDATE (TIM_EVTGEN_UDGN)
#define TIM_EVT_SRC_CC1 (TIM_EVTGEN_CC1GN)
#define TIM_EVT_SRC_CC2 (TIM_EVTGEN_CC2GN)
#define TIM_EVT_SRC_CC3 (TIM_EVTGEN_CC3GN)
#define TIM_EVT_SRC_CC4 (TIM_EVTGEN_CC4GN)
#define TIM_EVT_SRC_COM (TIM_EVTGEN_CCUDGN)
#define TIM_EVT_SRC_TRIG (TIM_EVTGEN_TGN)
#define TIM_EVT_SRC_BREAK (TIM_EVTGEN_BGN)
#define TIM_OC1_PRELOAD_MASK (TIM_CCMOD1_OC1PEN)
#define TIM_OC2_PRELOAD_MASK (TIM_CCMOD1_OC2PEN)
#define TIM_OC3_PRELOAD_MASK (TIM_CCMOD2_OC3PEN)
#define TIM_OC4_PRELOAD_MASK (TIM_CCMOD2_OC4PEN)
#define TIM_OC5_PRELOAD_MASK (TIM_CCMOD3_OC5PEN)
/** TIM_Output_Compare_Preload_State **/
#define TIM_OC_PRELOAD_ENABLE (TIM_CCMOD1_OC1PEN)
#define TIM_OC_PRELOAD_DISABLE (TIM_REG16_BIT_ZERO)
#define TIM_OC1_FAST_MASK (TIM_CCMOD1_OC1FEN)
#define TIM_OC2_FAST_MASK (TIM_CCMOD1_OC2FEN)
#define TIM_OC3_FAST_MASK (TIM_CCMOD2_OC3FEN)
#define TIM_OC4_FAST_MASK (TIM_CCMOD2_OC4FEN)
#define TIM_OC5_FAST_MASK (TIM_CCMOD3_OC5FEN)
/** TIM_Output_Compare_Fast_State **/
#define TIM_OC_FAST_ENABLE (TIM_CCMOD1_OC1FEN)
#define TIM_OC_FAST_DISABLE (TIM_REG16_BIT_ZERO)
#define TIM_OC1_CLEAR_MASK (TIM_CCMOD1_OC1CEN)
#define TIM_OC2_CLEAR_MASK (TIM_CCMOD1_OC2CEN)
#define TIM_OC3_CLEAR_MASK (TIM_CCMOD2_OC3CEN)
#define TIM_OC4_CLEAR_MASK (TIM_CCMOD2_OC4CEN)
#define TIM_OC5_CLEAR_MASK (TIM_CCMOD3_OC5CEN)
/** TIM_Output_Compare_Clear_State **/
#define TIM_OC_CLEAR_ENABLE (TIM_CCMOD1_OC1CEN)
#define TIM_OC_CLEAR_DISABLE (TIM_REG16_BIT_ZERO)
#define TIM_TRGO_SRC_MASK (TIM_CTRL2_MMSEL)
/** TIM_Trigger_Output_Source **/
#define TIM_TRGO_SRC_RESET (TIM_REG16_BIT_ZERO)
#define TIM_TRGO_SRC_ENABLE (TIM_CTRL2_MMSEL_0)
#define TIM_TRGO_SRC_UPDATE (TIM_CTRL2_MMSEL_1)
#define TIM_TRGO_SRC_OC1 (TIM_CTRL2_MMSEL_1 | TIM_CTRL2_MMSEL_0)
#define TIM_TRGO_SRC_OC1REF (TIM_CTRL2_MMSEL_2)
#define TIM_TRGO_SRC_OC2REF (TIM_CTRL2_MMSEL_2 | TIM_CTRL2_MMSEL_0)
#define TIM_TRGO_SRC_OC3REF (TIM_CTRL2_MMSEL_2 | TIM_CTRL2_MMSEL_1)
#define TIM_TRGO_SRC_OC4REF (TIM_CTRL2_MMSEL_2 | TIM_CTRL2_MMSEL_1 | TIM_CTRL2_MMSEL_0)
/** ETR selection **/
#define TIM_ETR_Seletct_ExtGpio (TIM_REG16_BIT_ZERO)
#define TIM_ETR_Seletct_innerTsc (TIM_CTRL2_TSCSEL)
#define TIM_SLAVE_MODE_MASK (TIM_SMCTRL_SMSEL)
/** TIM_Slave_Mode **/
#define TIM_SLAVE_MODE_RESET (TIM_SMCTRL_SMSEL_2)
#define TIM_SLAVE_MODE_GATED (TIM_SMCTRL_SMSEL_2 | TIM_SMCTRL_SMSEL_0)
#define TIM_SLAVE_MODE_TRIG (TIM_SMCTRL_SMSEL_2 | TIM_SMCTRL_SMSEL_1)
#define TIM_SLAVE_MODE_EXT1 (TIM_SMCTRL_SMSEL_2 | TIM_SMCTRL_SMSEL_1 | TIM_SMCTRL_SMSEL_0)
#define TIM_MASTER_SLAVE_MODE_MASK (TIM_SMCTRL_MSMD)
/** TIM_Master_Slave_Mode **/
#define TIM_MASTER_SLAVE_MODE_ENABLE (TIM_SMCTRL_MSMD)
#define TIM_MASTER_SLAVE_MODE_DISABLE (TIM_REG16_BIT_ZERO)
/** TIM_Flags **/
#define TIM_FLAG_UPDATE (TIM_STS_UDITF)
#define TIM_FLAG_CC1 (TIM_STS_CC1ITF)
#define TIM_FLAG_CC2 (TIM_STS_CC2ITF)
#define TIM_FLAG_CC3 (TIM_STS_CC3ITF)
#define TIM_FLAG_CC4 (TIM_STS_CC4ITF)
#define TIM_FLAG_COM (TIM_STS_COMITF)
#define TIM_FLAG_TRIG (TIM_STS_TITF)
#define TIM_FLAG_BREAK (TIM_STS_BITF)
#define TIM_FLAG_CC1OF (TIM_STS_CC1OCF)
#define TIM_FLAG_CC2OF (TIM_STS_CC2OCF)
#define TIM_FLAG_CC3OF (TIM_STS_CC3OCF)
#define TIM_FLAG_CC4OF (TIM_STS_CC4OCF)
#define TIM_FLAG_CC5 (TIM_STS_CC5ITF)
/** TIM_CCxEN **/
#define TIM_CC1EN (TIM_CCEN_CC1EN)
#define TIM_CC1NEN (TIM_CCEN_CC1NEN)
#define TIM_CC2EN (TIM_CCEN_CC2EN)
#define TIM_CC2NEN (TIM_CCEN_CC2NEN)
#define TIM_CC3EN (TIM_CCEN_CC3EN)
#define TIM_CC3NEN (TIM_CCEN_CC3NEN)
#define TIM_CC4EN (TIM_CCEN_CC4EN)
#define TIM_CC5EN (TIM_CCEN_CC5EN)
/** TIM_CCxP **/
#define TIM_CC1P (TIM_CCEN_CC1P)
#define TIM_CC1NP (TIM_CCEN_CC1NP)
#define TIM_CC2P (TIM_CCEN_CC2P)
#define TIM_CC2NP (TIM_CCEN_CC2NP)
#define TIM_CC3P (TIM_CCEN_CC3P)
#define TIM_CC3NP (TIM_CCEN_CC3NP)
#define TIM_CC4P (TIM_CCEN_CC4P)
#define TIM_CC5P (TIM_CCEN_CC5P)
/* TIM_CCDATx*/
#define TIM_CCDAT1_MASK (TIM_CCDAT1_CCDAT1)
#define TIM_CCDAT2_MASK (TIM_CCDAT2_CCDAT2)
#define TIM_CCDAT3_MASK (TIM_CCDAT3_CCDAT3)
#define TIM_CCDAT4_MASK (TIM_CCDAT4_CCDAT4)
/* ---------------------- TIM registers bit mask ------------------------ */
#define SMCTRL_ETRP_MASK ((uint16_t)0x8000)
#define SMCTRL_ETRCEN_MASK ((uint16_t)0x4000)
#define SMCTRL_ETRPSC_MASK ((uint16_t)0x3000)
#define SMCTRL_ETRFIL_MASK ((uint16_t)0x0f00)
#define CAPCMPMOD_OFFSET ((uint16_t)0x0018)
#define CAPCMPEN_CCE_SET ((uint16_t)0x0001)
#define CAPCMPEN_CCNE_SET ((uint16_t)0x0004)
void TIM_Reset(TIM_Module* TIMx);
/** TIM_Base functions **/
void TIM_Base_Count_Mode_Set(TIM_Module* TIMx, uint32_t cnt_mode);
/* function in N32G003 */
void TIM_Base_Auto_Reload_Set(TIM_Module* TIMx, uint16_t auto_reload);
void TIM_Base_Prescaler_Set(TIM_Module* TIMx, uint16_t prescaler);
void TIM_Base_Reload_Mode_Set(TIM_Module* TIMx, uint16_t reload_mode);
void TIM_Base_Count_Set(TIM_Module* TIMx, uint16_t count);
uint16_t TIM_Base_Count_Get(TIM_Module* TIMx);
uint16_t TIM_Auto_Reload_Get(TIM_Module* TIMx);
uint16_t TIM_Base_Prescaler_Get(TIM_Module* TIMx);
void TIM_Base_Repeat_Count_Set(TIM_Module* TIMx, uint8_t repeat_cnt);
void TIM_Base_Channel1(TIM_Module* TIMx, bool channel_selection);
void TIM_Base_OCrefClear(TIM_Module* TIMx, bool OCrefClear_selection);
void TIM_Base_Initialize(TIM_Module* TIMx, TIM_TimeBaseInitType* TIM_TimeBaseInitStruct);
void TIM_Base_Struct_Initialize(TIM_TimeBaseInitType* TIM_TimeBaseInitStruct);
void TIM_On(TIM_Module* TIMx);
void TIM_Off(TIM_Module* TIMx);
/** Preload functions **/
void TIM_Output_Channel1_Preload_Set(TIM_Module* TIMx, uint16_t TIM_output_channel_preload);
void TIM_Output_Channel2_Preload_Set(TIM_Module* TIMx, uint16_t TIM_output_channel_preload);
void TIM_Output_Channel3_Preload_Set(TIM_Module* TIMx, uint16_t TIM_output_channel_preload);
void TIM_Output_Channel4_Preload_Set(TIM_Module* TIMx, uint16_t TIM_output_channel_preload);
void TIM_Output_Channel5_Preload_Set(TIM_Module* TIMx, uint16_t TIM_output_channel_preload);
void TIM_Auto_Reload_Preload_Enable(TIM_Module* TIMx);
void TIM_Auto_Reload_Preload_Disable(TIM_Module* TIMx);
void TIM_Update_Event_Enable(TIM_Module* TIMx);
void TIM_Update_Event_Disable(TIM_Module* TIMx);
void TIM_Update_Request_Source_Set(TIM_Module* TIMx, uint16_t TIM_update_source);
void TIM_Event_Generate(TIM_Module* TIMx, uint16_t TIM_event_source);
void TIM_Commutation_Event_Enable(TIM_Module* TIMx);
void TIM_Commutation_Event_Disable(TIM_Module* TIMx);
void TIM_Capture_Compare_Control_Preload_Enable(TIM_Module* TIMx);
void TIM_Capture_Compare_Control_Preload_Disable(TIM_Module* TIMx);
/** Channel functions **/
void TIM_Compare1_Set(TIM_Module* TIMx, uint16_t compare1);
void TIM_Compare2_Set(TIM_Module* TIMx, uint16_t compare2);
void TIM_Compare3_Set(TIM_Module* TIMx, uint16_t compare3);
void TIM_Compare4_Set(TIM_Module* TIMx, uint16_t compare4);
void TIM_Compare5_Set(TIM_Module* TIMx, uint16_t compare5);
uint16_t TIM_Compare_Capture1_Get(TIM_Module* TIMx);
uint16_t TIM_Compare_Capture2_Get(TIM_Module* TIMx);
uint16_t TIM_Compare_Capture3_Get(TIM_Module* TIMx);
uint16_t TIM_Compare_Capture4_Get(TIM_Module* TIMx);
uint16_t TIM_Compare_Capture5_Get(TIM_Module* TIMx);
FlagStatus TIM_CCEN_Status_Get(TIM_Module* TIMx, uint32_t TIM_CCEN);
/** Chanel input&Cascade functions **/
void TIM_Trigger_Source_Select(TIM_Module* TIMx, uint16_t TIM_trigger_source);
void Input_Channel1_Config(TIM_Module* TIMx, uint16_t input_channel_polarity,
uint16_t input_channel_selection, uint16_t input_channel_filter);
void Input_Channel2_Config(TIM_Module* TIMx, uint16_t input_channel_polarity,
uint16_t input_channel_selection, uint16_t input_channel_filter);
void Input_Channel3_Config(TIM_Module* TIMx, uint16_t input_channel_polarity,
uint16_t input_channel_selection, uint16_t input_channel_filter);
void Input_Channel4_Config(TIM_Module* TIMx, uint16_t input_channel_polarity,
uint16_t input_channel_selection, uint16_t input_channel_filter);
void TIM_External_Trigger_Polarity_Set(TIM_Module* TIMx,
uint16_t external_trigger_polarity);
void TIM_External_Trigger_Filter_Set(TIM_Module* TIMx,
uint16_t external_trigger_filter);
void TIM_External_Trigger_Prescaler_Set(TIM_Module* TIMx,
uint16_t external_trigger_prescaler);
void TIM_Clock_Division_Set(TIM_Module* TIMx, uint16_t clock_division);
void TIM_Internal_Clock_Set(TIM_Module* TIMx);
void TIM_Input_Capture1_Prescaler_Set(TIM_Module* TIMx, uint16_t TIM_input_capture_prescaler);
void TIM_Input_Capture2_Prescaler_Set(TIM_Module* TIMx, uint16_t TIM_input_capture_prescaler);
void TIM_Input_Capture3_Prescaler_Set(TIM_Module* TIMx, uint16_t TIM_input_capture_prescaler);
void TIM_Input_Capture4_Prescaler_Set(TIM_Module* TIMx, uint16_t TIM_input_capture_prescaler);
void TIM_Internal_Trig_To_Ext_Set(TIM_Module* TIMx, uint16_t input_trigger_source);
void TIM_Trigger_As_External_Clock(TIM_Module* TIMx, uint16_t external_clock_source, uint16_t input_channel_polarity, uint16_t input_channel_filter);
void TIM_External_Clock_Mode1_Set(TIM_Module* TIMx, uint16_t external_trigger_prescaler, uint16_t external_trigger_polarity, uint16_t external_trigger_filter);
void TIM_External_Clock_Mode2_Set(TIM_Module* TIMx, uint16_t external_trigger_prescaler, uint16_t external_trigger_polarity, uint16_t external_trigger_filter);
void TIM_Slave_Mode_Select(TIM_Module* TIMx, uint16_t TIM_slave_mode);
void TIM_Master_Slave_Mode_Set(TIM_Module* TIMx, uint16_t TIM_master_slave_mode);
void TIM_Output_Trigger_Select(TIM_Module* TIMx, uint16_t TIM_trigger_output_source);
void TIM_One_Pulse_Mode_Select(TIM_Module* TIMx, uint16_t TIM_one_pulse_mode);
void TIM_Input_Channel_Initialize(TIM_Module* TIMx, TIM_ICInitType* TIM_ICInitStruct);
void TIM_PWM_Input_Channel_Config(TIM_Module* TIMx, TIM_ICInitType* TIM_ICInitStruct);
void TIM_Input_Struct_Initialize(TIM_ICInitType* TIM_ICInitStruct);
/** Channel output functions **/
void TIM_Output_Channel_Polarity_Set(TIM_Module* TIMx, uint32_t output_channel_polarity, uint16_t channel);
void TIM_Output_Channel_N_Polarity_Set(TIM_Module* TIMx, uint32_t output_channel_N_polarity, uint16_t channel);
void TIM_Capture_Compare_Ch_Enable(TIM_Module* TIMx, uint16_t channel);
void TIM_Capture_Compare_Ch_Disable(TIM_Module* TIMx, uint16_t channel);
void TIM_Capture_Compare_Ch_N_Enable(TIM_Module* TIMx, uint16_t channel);
void TIM_Capture_Compare_Ch_N_Disable(TIM_Module* TIMx, uint16_t channel);
void TIM_Output_Channel_Mode_Set(TIM_Module* TIMx, uint32_t output_channel_mode, uint16_t channel);
void TIM_Forced_Output_Channel1_Set(TIM_Module* TIMx, uint16_t TIM_ForcedAction);
void TIM_Forced_Output_Channel2_Set(TIM_Module* TIMx, uint16_t TIM_ForcedAction);
void TIM_Forced_Output_Channel3_Set(TIM_Module* TIMx, uint16_t TIM_ForcedAction);
void TIM_Forced_Output_Channel4_Set(TIM_Module* TIMx, uint16_t TIM_ForcedAction);
void TIM_Forced_Output_Channel5_Set(TIM_Module* TIMx, uint16_t TIM_ForcedAction);
void TIM_Output_Channel1_Fast_Set(TIM_Module* TIMx, uint16_t TIM_output_channel_fast);
void TIM_Output_Channel2_Fast_Set(TIM_Module* TIMx, uint16_t TIM_output_channel_fast);
void TIM_Output_Channel3_Fast_Set(TIM_Module* TIMx, uint16_t TIM_output_channel_fast);
void TIM_Output_Channel4_Fast_Set(TIM_Module* TIMx, uint16_t TIM_output_channel_fast);
void TIM_Output_Channel5_Fast_Set(TIM_Module* TIMx, uint16_t TIM_output_channel_fast);
void TIM_Output_Channel1_Reference_Clear(TIM_Module* TIMx, uint16_t TIM_output_chanenl_clear);
void TIM_Output_Channel2_Reference_Clear(TIM_Module* TIMx, uint16_t TIM_output_chanenl_clear);
void TIM_Output_Channel3_Reference_Clear(TIM_Module* TIMx, uint16_t TIM_output_chanenl_clear);
void TIM_Output_Channel4_Reference_Clear(TIM_Module* TIMx, uint16_t TIM_output_chanenl_clear);
void TIM_Output_Channel5_Reference_Clear(TIM_Module* TIMx, uint16_t TIM_output_chanenl_clear);
void TIM_PWM_Output_Enable(TIM_Module* TIMx);
void TIM_PWM_Output_Disable(TIM_Module* TIMx);
void TIM_Output_Channel1_Initialize(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct);
void TIM_Output_Channel2_Initialize(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct);
void TIM_Output_Channel3_Initialize(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct);
void TIM_Output_Channel4_Initialize(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct);
void TIM_Output_Channel5_Initialize(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct);
void TIM_Output_Channel_Struct_Initialize(OCInitType* TIM_OCInitStruct);
/** Brake functions **/
void TIM_Lock_Up_Break_Enable(TIM_Module* TIMx);
void TIM_Lock_Up_Break_Disable(TIM_Module* TIMx);
void TIM_Pvd_Break_Enable(TIM_Module* TIMx);
void TIM_Pvd_Break_Disable(TIM_Module* TIMx);
void TIM_IOM_Comp_Break(TIM_Module* TIMx, bool IOM_Comp_Selection);
void TIM_Break_And_Dead_Time_Set(TIM_Module* TIMx, TIM_BDTRInitType* TIM_BDTRInitStruct);
void TIM_Break_And_Dead_Time_Struct_Initialize(TIM_BDTRInitType* TIM_BDTRInitStruct);
/** Interrupt functions **/
void TIM_Interrupt_Enable(TIM_Module* TIMx, uint16_t TIM_IT);
void TIM_Interrupt_Disable(TIM_Module* TIMx, uint16_t TIM_IT);
FlagStatus TIM_Flag_Status_Get(TIM_Module* TIMx, uint32_t TIM_FLAG);
ITStatus TIM_Interrupt_Status_Get(TIM_Module* TIMx, uint32_t TIM_IT);
void TIM_Flag_Clear(TIM_Module* TIMx, uint32_t TIM_FLAG);
void TIM_Interrupt_Status_Clear(TIM_Module* TIMx, uint32_t TIM_IT);
#ifdef __cplusplus
}
#endif
#endif /* _N32G003_TIM_H__ */

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/**
* Copyright (c) 2022, Nations Technologies Inc.
*
* All rights reserved.
*
* This software is the exclusive property of Nations Technologies Inc. (Hereinafter
* referred to as NATIONS). This software, and the product of NATIONS described herein
* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties
* of the People's Republic of China and other applicable jurisdictions worldwide.
*
* NATIONS does not grant any license under its patents, copyrights, trademarks, or other
* intellectual property rights. Names and brands of third party may be mentioned or referred
* thereto (if any) for identification purposes only.
*
* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and
* improvements to this software at any time without notice. Please contact NATIONS and obtain
* the latest version of this software before placing orders.
* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes
* no responsibility for the accuracy and reliability of this software.
*
* It is the responsibility of the user of this software to properly design, program, and test
* the functionality and safety of any application made of this information and any resulting product.
* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or
* consequential damages arising in any way out of the use of this software or the Product.
*
* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any
* malfunction or failure of which may cause loss of human life, bodily injury or severe property
* damage. Such applications are deemed, "Insecure Usage".
*
* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS
* harmless from and against all claims, costs, damages, and other liabilities, arising from or related
* to any customer's Insecure Usage.
* Any express or implied warranty with regard to this software or the Product, including,but not
* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement
* are disclaimed to the fullest extent permitted by law.
* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe
* or otherwise distribute this software for any purposes, in whole or in part.
*
* NATIONS products and technologies shall not be used for or incorporated into any products or systems
* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations.
* User shall comply with any applicable export control laws and regulations promulgated and administered by
* the governments of any countries asserting jurisdiction over the parties or transactions.
**/
/**
*\*\file n32g003_uart.h
*\*\author Nations
*\*\version v1.0.0
*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
**/
#ifndef __N32G003_UART_H
#define __N32G003_UART_H
#ifdef __cplusplus
extern "C" {
#endif
#include "n32g003.h"
/*** UART Structure Definition Start ***/
/** UART Init structure definition **/
typedef struct
{
uint32_t BaudRate; /* Configures the UART communication baud rate. */
uint16_t WordLength; /* Specifies the number of data bits transmitted or received in a frame. */
uint16_t StopBits; /* Specifies the number of stop bits transmitted. */
uint16_t Parity; /* Specifies the parity mode. */
uint16_t Mode; /* Specifies wether the Receive or Transmit mode is enabled or disabled. */
} UART_InitType;
/*** UART Macro Definition Start ***/
/** All register bits are configure to 0 **/
#define UART_REG_BIT_MASK ((uint16_t)0x0000)
/** Configures the word length of UART **/
#define UART_WL_MASK (~UART_CTRL1_WL) /* word length Mask */
#define UART_WL_8B (UART_REG_BIT_MASK) /* 8 bits */
#define UART_WL_9B (UART_CTRL1_WL) /* 9 bits */
/** UART STOP bits **/
#define CTRL2_STPB_CLR_MASK (~UART_CTRL2_STPB) /* UART CTRL2 STOP Bits Mask */
#define UART_STPB_1 (UART_REG_BIT_MASK) /* 1 STOP bit */
#define UART_STPB_2 (UART_CTRL2_STPB_1) /* 2 STOP bits */
/** UART parity selection **/
#define UART_PE_MASK (~(UART_CTRL1_PCEN | UART_CTRL1_PSEL)) /* UART parity Mask */
#define UART_PE_NO (UART_REG_BIT_MASK) /* UART parity disable */
#define UART_PE_EVEN (UART_CTRL1_PCEN) /* Even parity */
#define UART_PE_ODD (UART_CTRL1_PCEN | UART_CTRL1_PSEL) /* Odd parity */
/** UART is configured as RX or TX **/
#define UART_MODE_MASK (~(UART_CTRL1_RXEN | UART_CTRL1_TXEN)) /* UART mode Mask */
#define UART_MODE_RX (UART_CTRL1_RXEN) /* Transmitter enable */
#define UART_MODE_TX (UART_CTRL1_TXEN) /* Receiver enable */
/** UART enable or disable **/
#define CTRL1_UEN_SET (UART_CTRL1_UEN) /* UART Enable */
#define CTRL1_UEN_RESET (~UART_CTRL1_UEN) /* UART Disable */
/** Configure interrupt **/
#define INT_MASK ((uint16_t)0x001F) /* UART Interrupt Mask */
#define UART_INT_PEF ((uint16_t)0x0028) /* Parity error interrupt */
#define UART_INT_TXDE ((uint16_t)0x0727) /* TXDE interrupt */
#define UART_INT_TXC ((uint16_t)0x0626) /* Transmission complete interrupt */
#define UART_INT_RXDNE ((uint16_t)0x0525) /* RXDEN interrupt */
#define UART_INT_IDLEF ((uint16_t)0x0424) /* IDLE interrupt */
#define UART_INT_OREF ((uint16_t)0x0325) /* ORE interrupt */
/** UART address Mask **/
#define CTRL2_ADDR_MASK (~UART_CTRL2_ADDR)
/** Wake up methods **/
#define CTRL1_WUM_MASK (~UART_CTRL1_WUM) /* UART WakeUp Method Mask */
#define UART_WUM_IDLELINE (UART_REG_BIT_MASK) /* Idle frame wake up */
#define UART_WUM_ADDRMASK (UART_CTRL1_WUM) /* Address mark wake up */
/** Receiver wakeup **/
#define CTRL1_RCVWU_SET (UART_CTRL1_RCVWU) /* UART mute mode Enable */
#define CTRL1_RCVWU_RESET (~UART_CTRL1_RCVWU) /* UART mute mode Disable */
/** UART Break Character send Mask **/
#define CTRL1_SDBRK_SET (UART_CTRL1_SDBRK)
/** UART Half-Duplex Enable or Disable **/
#define CTRL3_HDMEN_SET (UART_CTRL3_HDMEN) /* UART Half-Duplex Enable */
#define CTRL3_HDMEN_RESET (~UART_CTRL3_HDMEN) /* UART Half-Duplex Disable */
/* Specifies the flag to check */
#define UART_FLAG_TXDE (UART_STS_TXDE) /* Transmit data register empty flag */
#define UART_FLAG_TXC (UART_STS_TXC) /* Transmission complete flag*/
#define UART_FLAG_RXDNE (UART_STS_RXDNE) /* Read data register not empty flag*/
#define UART_FLAG_IDLEF (UART_STS_IDLEF) /* IDLE line detected flag */
#define UART_FLAG_OREF (UART_STS_OREF) /* OverRun error flag */
#define UART_FLAG_NEF (UART_STS_NEF) /* Noise error flag */
#define UART_FLAG_FEF (UART_STS_FEF) /* Framing error flag*/
#define UART_FLAG_PEF (UART_STS_PEF) /* Parity error flag */
void UART_Reset(UART_Module* UARTx);
void UART_Initializes(UART_Module* UARTx, UART_InitType* UART_InitStruct);
void UART_Baud_Rate_Config(UART_Module* UARTx,uint32_t buad_rate);
void UART_Word_Length_Config(UART_Module* UARTx,uint16_t word_length);
void UART_Stop_Bits_Config(UART_Module* UARTx,uint16_t stop_bits);
void UART_Parity_Config(UART_Module* UARTx,uint16_t parity);
void UART_Mode_Config(UART_Module* UARTx,uint16_t mode);
void UART_Structure_Initializes(UART_InitType* UART_InitStruct);
void UART_Enable(UART_Module* UARTx);
void UART_Disable(UART_Module* UARTx);
void UART_Interrput_Enable(UART_Module* UARTx, uint16_t UART_interrupt);
void UART_Interrput_Disable(UART_Module* UARTx, uint16_t UART_interrupt);
void UART_Address_Set(UART_Module* UARTx, uint8_t UART_address);
void UART_WakeUp_Mode_Set(UART_Module* UARTx, uint16_t UART_wake_up_mode);
void UART_Receiver_Wakeup_Enable(UART_Module* UARTx);
void UART_Receiver_Wakeup_Disable(UART_Module* UARTx);
void UART_Data_Send(UART_Module* UARTx, uint16_t data);
uint16_t UART_Data_Receive(UART_Module* UARTx);
void UART_Break_Frame_Send(UART_Module* UARTx);
void UART_Half_Duplex_Enable(UART_Module* UARTx);
void UART_Half_Duplex_Disable(UART_Module* UARTx);
FlagStatus UART_Flag_Status_Get(UART_Module* UARTx, uint16_t UART_flag);
void UART_Flag_Clear(UART_Module* UARTx, uint16_t UART_flag);
ITStatus UART_Interrupt_Status_Get(UART_Module* UARTx, uint16_t UART_interrupt);
void UART_Interrupt_Status_Clear(UART_Module* UARTx, uint16_t UART_Interrupt);
#ifdef __cplusplus
}
#endif
#endif /* __N32G003_UART_H */
/******************* (C) COPYRIGHT 2022 NATIONZ *****END OF FILE****/

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/**
* Copyright (c) 2022, Nations Technologies Inc.
*
* All rights reserved.
*
* This software is the exclusive property of Nations Technologies Inc. (Hereinafter
* referred to as NATIONS). This software, and the product of NATIONS described herein
* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties
* of the People's Republic of China and other applicable jurisdictions worldwide.
*
* NATIONS does not grant any license under its patents, copyrights, trademarks, or other
* intellectual property rights. Names and brands of third party may be mentioned or referred
* thereto (if any) for identification purposes only.
*
* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and
* improvements to this software at any time without notice. Please contact NATIONS and obtain
* the latest version of this software before placing orders.
* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes
* no responsibility for the accuracy and reliability of this software.
*
* It is the responsibility of the user of this software to properly design, program, and test
* the functionality and safety of any application made of this information and any resulting product.
* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or
* consequential damages arising in any way out of the use of this software or the Product.
*
* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any
* malfunction or failure of which may cause loss of human life, bodily injury or severe property
* damage. Such applications are deemed, "Insecure Usage".
*
* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS
* harmless from and against all claims, costs, damages, and other liabilities, arising from or related
* to any customer's Insecure Usage.
* Any express or implied warranty with regard to this software or the Product, including,but not
* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement
* are disclaimed to the fullest extent permitted by law.
* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe
* or otherwise distribute this software for any purposes, in whole or in part.
*
* NATIONS products and technologies shall not be used for or incorporated into any products or systems
* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations.
* User shall comply with any applicable export control laws and regulations promulgated and administered by
* the governments of any countries asserting jurisdiction over the parties or transactions.
**/
/**
*\*\file misc.c
*\*\author Nations
*\*\version v1.0.0
*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
**/
#include "misc.h"
/** MISC Driving Functions Declaration **/
/**
*\*\name NVIC_Initializes
*\*\fun Initializes the NVIC peripheral according to the specified parameters in the NVIC_structure_initializes.
*\*\param NVIC_structure_initializes :
*\*\ - NVIC_IRQChannel :
*\*\ - IRQn_Type N32G003 Interrupt Number Definition
*\*\ - NVIC_IRQChannelPriority :
*\*\ - NVIC_PRIORITY_0
*\*\ - NVIC_PRIORITY_1
*\*\ - NVIC_PRIORITY_2
*\*\ - NVIC_PRIORITY_3
*\*\ - NVIC_IRQChannelCmd :
*\*\ - ENABLE
*\*\ - DISABLE
*\*\return none
**/
void NVIC_Initializes(NVIC_InitType* NVIC_structure_initializes)
{
/* Set Interrupt Priority */
NVIC_SetPriority(NVIC_structure_initializes->NVIC_IRQChannel, NVIC_structure_initializes->NVIC_IRQChannelPriority);
if (NVIC_structure_initializes->NVIC_IRQChannelCmd != DISABLE)
{
/* Enable the Selected IRQ Channels */
NVIC_EnableIRQ(NVIC_structure_initializes->NVIC_IRQChannel);
}
else
{
/* Disable the Selected IRQ Channels */
NVIC_DisableIRQ(NVIC_structure_initializes->NVIC_IRQChannel);
}
}
/**
*\*\name NVIC_System_Low_Power_Enable
*\*\fun Selects the condition for the system to enter low power mode.
*\*\param low_power_mode Specifies the new mode for the system to enter low power mode.
*\*\ This parameter can be one of the following values:
*\*\ - NVIC_LP_SEVONPEND
*\*\ - NVIC_LP_SLEEPDEEP
*\*\ - NVIC_LP_SLEEPONEXIT
*\*\return none
**/
void NVIC_System_LowPower_Enable(uint8_t low_power_mode)
{
SCB->SCR |= low_power_mode;
}
/**
*\*\name NVIC_System_Low_Power_Disable
*\*\fun Selects the condition for the system to enter low power mode.
*\*\param low_power_mode :
*\*\ - NVIC_LP_SEVONPEND
*\*\ - NVIC_LP_SLEEPDEEP
*\*\ - NVIC_LP_SLEEPONEXIT
*\*\return none
**/
void NVIC_System_Low_Power_Disable(uint8_t low_power_mode)
{
SCB->SCR &= (uint32_t)(~(uint32_t)low_power_mode);
}
/**
*\*\name SysTick_Clock_Source_Set
*\*\fun Configures the SysTick clock source.
*\*\param systick_clock_source :
*\*\ - SYSTICK_CLKSOURCE_HCLK_DIV8 External clock selected as SysTick clock source.
*\*\ - SYSTICK_CLKSOURCE_HCLK AHB clock selected as SysTick clock source.
*\*\return none
**/
void SysTick_Clock_Source_Set(uint32_t systick_clock_source)
{
if (systick_clock_source == SYSTICK_CLKSOURCE_HCLK)
{
SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
}
else
{
SysTick->CTRL &= SYSTICK_CLKSOURCE_HCLK_DIV8;
}
}

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/**
* Copyright (c) 2022, Nations Technologies Inc.
*
* All rights reserved.
*
* This software is the exclusive property of Nations Technologies Inc. (Hereinafter
* referred to as NATIONS). This software, and the product of NATIONS described herein
* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties
* of the People's Republic of China and other applicable jurisdictions worldwide.
*
* NATIONS does not grant any license under its patents, copyrights, trademarks, or other
* intellectual property rights. Names and brands of third party may be mentioned or referred
* thereto (if any) for identification purposes only.
*
* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and
* improvements to this software at any time without notice. Please contact NATIONS and obtain
* the latest version of this software before placing orders.
* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes
* no responsibility for the accuracy and reliability of this software.
*
* It is the responsibility of the user of this software to properly design, program, and test
* the functionality and safety of any application made of this information and any resulting product.
* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or
* consequential damages arising in any way out of the use of this software or the Product.
*
* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any
* malfunction or failure of which may cause loss of human life, bodily injury or severe property
* damage. Such applications are deemed, "Insecure Usage".
*
* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS
* harmless from and against all claims, costs, damages, and other liabilities, arising from or related
* to any customer's Insecure Usage.
* Any express or implied warranty with regard to this software or the Product, including,but not
* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement
* are disclaimed to the fullest extent permitted by law.
* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe
* or otherwise distribute this software for any purposes, in whole or in part.
*
* NATIONS products and technologies shall not be used for or incorporated into any products or systems
* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations.
* User shall comply with any applicable export control laws and regulations promulgated and administered by
* the governments of any countries asserting jurisdiction over the parties or transactions.
**/
/**
*\*\file n32g003_adc.c
*\*\author Nations
*\*\version v1.0.0
*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
**/
#include "n32g003_adc.h"
#include "n32g003_rcc.h"
/**
*\*\name ADC_Reset.
*\*\fun Reset the ADC registers.
*\*\return none
**/
void ADC_Reset(void)
{
RCC_Peripheral_Reset(RCC_RST_ADCRST);
}
/**
*\*\name ADC_Multichannels_Enable.
*\*\fun Configures the ADC according conversion is performed in
*\*\ Scan (multichannels) mode.
*\*\return none
**/
void ADC_Multichannels_Enable(void)
{
/* Set ADC_CTRL1 SCANMD bit */
ADC->CTRL2 |= ADC_MULTCH_ENABLE;
}
/**
*\*\name ADC_Multichannels_Disable.
*\*\fun Configures the ADC according conversion is performed in
*\*\ Single (one channel) mode.
*\*\return none
**/
void ADC_Multichannels_Disable(void)
{
/* Clear ADC_CTRL1 SCANMD bit */
ADC->CTRL2 &= ADC_MULTCH_DISABLE;
}
/**
*\*\name ADC_Continue_Conversion_Enable.
*\*\fun Configures the ADC according conversion is performed in
*\*\ Continuous mode.
*\*\return none
**/
void ADC_Continue_Conversion_Enable(void)
{
/* Set ADC_CTRL2 CTU bit */
ADC->CTRL2 |= ADC_CTU_ENABLE;
}
/**
*\*\name ADC_Continue_Conversion_Disable.
*\*\fun Configures the ADC according conversion is performed in
*\*\ Single mode.
*\*\return none
**/
void ADC_Continue_Conversion_Disable(void)
{
/* Clear ADC_CTRL2 CTU bit */
ADC->CTRL2 &= ADC_CTU_DISABLE;
}
/**
*\*\name ADC_Regular_Group_External_Trigger_Source_Config.
*\*\fun Configures the ADC external trigger source for regular group channels.
*\*\param external_trigger_sources :
*\*\ - ADC_EXT_TRIGCONV_REGULAR_T1_CC1
*\*\ - ADC_EXT_TRIGCONV_REGULAR_T1_CC2
*\*\ - ADC_EXT_TRIGCONV_REGULAR_T1_CC3
*\*\ - ADC_EXT_TRIGCONV_REGULAR_T1_CC4
*\*\ - ADC_EXT_TRIGCONV_REGULAR_T1_TRGO
*\*\ - ADC_EXT_TRIGCONV_REGULAR_T3_TRGO
*\*\ - ADC_EXT_TRIGCONV_REGULAR_T3_CC1
*\*\ - ADC_EXT_TRIGCONV_REGULAR_T3_CC2
*\*\ - ADC_EXT_TRIGCONV_REGULAR_EXT_INT11
*\*\ - ADC_EXT_TRIGCONV_REGULAR_SWSTRRCH
*\*\return none
**/
void ADC_Regular_Group_External_Trigger_Source_Config(uint32_t external_trigger_sources)
{
/* Clear ADC_CTRL2 EXTRSEL[3:0] and EXTRTRIG bit */
ADC->CTRL2 &= ADC_EXT_TRIGCONV_REGULAR_MASK;
/* Set ADC_CTRL2 EXTRSEL[3:0] and EXTRTRIG bit */
ADC->CTRL2 |= external_trigger_sources;
}
/**
*\*\name ADC_Data_Alignment_Config.
*\*\fun Configures the ADC data alignment is left or right.
*\*\param data_alignment :
*\*\ - ADC_DAT_ALIGN_R
*\*\ - ADC_DAT_ALIGN_L
*\*\return none
**/
void ADC_Data_Alignment_Config(uint32_t data_alignment)
{
/* Clear ADC_CTRL2 ALIG bit */
ADC->CTRL2 &= ADC_ALIG_MASK;
/* Set ADC_CTRL2 ALIG bit */
ADC->CTRL2 |= data_alignment;
}
/**
*\*\name ADC_Regular_Channels_Number_Config.
*\*\fun Configures the ADC total number of conversion channels.
*\*\param channels_number :
*\*\ - ADC_REGULAR_LEN_1
*\*\ - ADC_REGULAR_LEN_2
*\*\ - ADC_REGULAR_LEN_3
*\*\ - ADC_REGULAR_LEN_4
*\*\ - ADC_REGULAR_LEN_5
*\*\return none
**/
void ADC_Regular_Channels_Number_Config(uint32_t channels_number)
{
/* Clear ADC_RSEQ1 LEN[3:0] bit */
ADC->CTRL2 &= ADC_REGULAR_LEN_MSAK;
/* Set ADC_RSEQ1 LEN[3:0] bit */
ADC->CTRL2 |= channels_number;
}
/**
*\*\name ADC_Initializes.
*\*\fun Initializes the ADC according to ADC_initstruct.
*\*\param ADC_initstruct :
*\*\ - MultiChEn
*\*\ - DISABLE
*\*\ - ENABLE
*\*\ - ContinueConvEn
*\*\ - DISABLE
*\*\ - ENABLE
*\*\ - ExtTrigSelect
*\*\ - ADC_EXT_TRIGCONV_REGULAR_T1_CC1
*\*\ - ADC_EXT_TRIGCONV_REGULAR_T1_CC2
*\*\ - ADC_EXT_TRIGCONV_REGULAR_T1_CC3
*\*\ - ADC_EXT_TRIGCONV_REGULAR_T1_CC4
*\*\ - ADC_EXT_TRIGCONV_REGULAR_T1_TRGO
*\*\ - ADC_EXT_TRIGCONV_REGULAR_T3_TRGO
*\*\ - ADC_EXT_TRIGCONV_REGULAR_T3_CC1
*\*\ - ADC_EXT_TRIGCONV_REGULAR_T3_CC2
*\*\ - ADC_EXT_TRIGCONV_REGULAR_EXT_INT11
*\*\ - ADC_EXT_TRIGCONV_REGULAR_SWSTRRCH
*\*\ - DatAlign
*\*\ - ADC_DAT_ALIGN_R
*\*\ - ADC_DAT_ALIGN_L
*\*\ - ChsNumber
*\*\ - ADC_REGULAR_LEN_1
*\*\ - ADC_REGULAR_LEN_2
*\*\ - ADC_REGULAR_LEN_3
*\*\ - ADC_REGULAR_LEN_4
*\*\ - ADC_REGULAR_LEN_5
*\*\return none
**/
void ADC_Initializes(ADC_InitType* ADC_initstruct)
{
if(ADC_initstruct->MultiChEn)
{
ADC_Multichannels_Enable();
}
else
{
ADC_Multichannels_Disable();
}
if(ADC_initstruct->ContinueConvEn)
{
ADC_Continue_Conversion_Enable();
}
else
{
ADC_Continue_Conversion_Disable();
}
ADC_Regular_Group_External_Trigger_Source_Config(ADC_initstruct->ExtTrigSelect);
ADC_Data_Alignment_Config(ADC_initstruct->DatAlign);
ADC_Regular_Channels_Number_Config(ADC_initstruct->ChsNumber);
}
/**
*\*\name ADC_Initializes_Structure.
*\*\fun Fills each ADC_initstruct member with its default value.
*\*\param ADC_initstruct :
*\*\ - MultiChEn
*\*\ - ContinueConvEn
*\*\ - ExtTrigSelect
*\*\ - DatAlign
*\*\ - ChsNumber
*\*\return none
**/
void ADC_Initializes_Structure(ADC_InitType* ADC_initstruct)
{
/* Reset ADC init structure parameters values */
/* initialize the MultiChEn member */
ADC_initstruct->MultiChEn = DISABLE;
/* Initialize the ContinueConvEn member */
ADC_initstruct->ContinueConvEn = DISABLE;
/* Initialize the ExtTrigSelect member */
ADC_initstruct->ExtTrigSelect = ADC_EXT_TRIGCONV_REGULAR_T1_CC1;
/* Initialize the DatAlign member */
ADC_initstruct->DatAlign = ADC_DAT_ALIGN_R;
/* Initialize the ChsNumber member */
ADC_initstruct->ChsNumber = ADC_REGULAR_LEN_1;
}
/**
*\*\name ADC_ON.
*\*\fun ADC turn ON.
*\*\return none
**/
void ADC_ON(void)
{
/* Set the ADC_CTRL2 ON bit to wake up the ADC from power down mode */
ADC->CTRL2 |= ADC_TURN_ON;
}
/**
*\*\name ADC_OFF.
*\*\fun ADC turn OFF.
*\*\return none
**/
void ADC_OFF(void)
{
/* Clear the ADC_CTRL2 ON bit, then ADC go to power down mode */
ADC->CTRL2 &= ADC_TURN_OFF;
}
/**
*\*\name ADC_Interrupts_Enable.
*\*\fun Enable ADC interrupts.
*\*\param eoc_any :
*\*\ - ADC_SET_INT_TYPE_ENDCA
*\*\ - ADC_SET_INT_TYPE_OTHER
*\*\param ADC_SET_INT_TYPE_ENDCA:
*\*\ - ADC_INT_ENDCA ADC_CTRL3
*\*\param ADC_SET_INT_TYPE_OTHER:
*\*\ - ADC_INT_ENDC ADC_CTRL1
*\*\ - ADC_INT_AWD ADC_CTRL1
*\*\return none
**/
void ADC_Interrupts_Enable(u8 eoc_any, uint32_t adc_interrupt)
{
if(eoc_any == ADC_SET_INT_TYPE_ENDCA)
{
/* Set the ADC_CTRL3 ADC_INT_ENDCA bit to enable ADC interrupts */
ADC->CTRL3 |= adc_interrupt;
}
else
{
/* Set the ADC_CTRL1 ADC_INT_ENDC/ADC_INT_AWD bit to enable ADC interrupts */
ADC->CTRL1 |= adc_interrupt;
}
}
/**
*\*\name ADC_Interrupts_Disable.
*\*\fun Disable ADC interrupts.
*\*\param eoc_any :
*\*\ - ADC_SET_INT_TYPE_ENDCA
*\*\ - ADC_SET_INT_TYPE_OTHER
*\*\param ADC_SET_INT_TYPE_ENDCA:
*\*\ - ADC_INT_ENDCA ADC_CTRL3
*\*\param ADC_SET_INT_TYPE_OTHER:
*\*\ - ADC_INT_ENDC ADC_CTRL1
*\*\ - ADC_INT_AWD ADC_CTRL1
*\*\return none
**/
void ADC_Interrupts_Disable(u8 eoc_any, uint32_t adc_interrupt)
{
if(eoc_any == ADC_SET_INT_TYPE_ENDCA)
{
/* Clear the ADC_CTRL3 ADC_INT_ENDCA bit to disable ADC interrupts */
ADC->CTRL3 &= (~adc_interrupt);
}
else
{
/* Clear the ADC_CTRL1 ADC_INT_ENDC/ADC_INT_AWD bit to disable ADC interrupts */
ADC->CTRL1 &= (~adc_interrupt);
}
}
/**
*\*\name ADC_Regular_Channels_Software_Conversion_Operation.
*\*\fun ADC regular channels software conversion operation.
*\*\param conversion_operation :
*\*\ - ADC_EXTRTRIG_SWSTRRCH_ENABLE
*\*\ - ADC_EXTRTRIG_SWSTRRCH_DISABLE
*\*\ - ADC_EXTRTRIG_SWSTRRCH_GET_STS
*\*\return FlagStatus:
*\*\ - SET
*\*\ - RESET
**/
FlagStatus ADC_Regular_Channels_Software_Conversion_Operation(uint32_t conversion_operation)
{
if(conversion_operation == ADC_EXTRTRIG_SWSTRRCH_ENABLE)
{
/* Enable the ADC external trigger conversion mode for regular channels */
ADC->CTRL2 |= conversion_operation;
}
else if(conversion_operation == ADC_EXTRTRIG_SWSTRRCH_DISABLE)
{
/* Disable the ADC external trigger conversion mode for regular channels */
ADC->CTRL2 &= conversion_operation;
}
else if(conversion_operation == ADC_EXTRTRIG_SWSTRRCH_GET_STS)
{
/* Get ADC_CTRL2 SWSTRRCH bit */
if ((ADC->CTRL2 & conversion_operation) != (uint32_t)RESET)
{
return SET;
}
else
{
return RESET;
}
}
return RESET;
}
/**
*\*\name ADC_Channel_Sample_Time_Config.
*\*\fun Configures ADC channel sample time.
*\*\param sample_time :
*\*\ - ADC_SAMP_TIME_8CYCLES
*\*\ - ADC_SAMP_TIME_12CYCLES
*\*\ - ADC_SAMP_TIME_14CYCLES
*\*\ - ADC_SAMP_TIME_20CYCLES
*\*\ - ADC_SAMP_TIME_26CYCLES
*\*\ - ADC_SAMP_TIME_30CYCLES
*\*\ - ADC_SAMP_TIME_42CYCLES
*\*\ - ADC_SAMP_TIME_56CYCLES
*\*\ - ADC_SAMP_TIME_72CYCLES
*\*\ - ADC_SAMP_TIME_88CYCLES
*\*\ - ADC_SAMP_TIME_120CYCLES
*\*\ - ADC_SAMP_TIME_182CYCLES
*\*\ - ADC_SAMP_TIME_240CYCLES
*\*\ - ADC_SAMP_TIME_380CYCLES
*\*\ - ADC_SAMP_TIME_760CYCLES
*\*\ - ADC_SAMP_TIME_1520CYCLES
*\*\ - ADC_SAMP_TIME_3040CYCLES
*\*\return none
**/
void ADC_Channel_Sample_Time_Config(uint8_t sample_time)
{
ADC->SAMPT &= (uint32_t)(ADC_SAMP_TIME_MASK);
ADC->SAMPT |= (uint32_t)(sample_time);
}
/**
*\*\name ADC_External_Trigger_Conversion_Config.
*\*\fun ADC conversion through external trigger enable.
*\*\param group_operation :
*\*\ - ADC_EXTTRIGCONV_REGULAR_ENABLE
*\*\ - ADC_EXTTRIGCONV_REGULAR_DISABLE
*\*\return none
**/
void ADC_External_Trigger_Conversion_Config(uint32_t group_operation)
{
if(group_operation == ADC_EXTTRIGCONV_REGULAR_ENABLE)
{
/* Enable ADC regular group channels conversion on external event */
ADC->CTRL2 |= group_operation;
}
else if(group_operation == ADC_EXTTRIGCONV_REGULAR_DISABLE)
{
/* Disables ADC regular group channels conversion on external event */
ADC->CTRL2 &= group_operation;
}
}
/**
*\*\name ADC_Regular_Conversion_Data_Get.
*\*\fun Get ADC regular conversion data.
*\*\return ADC regular group conversion data.
**/
uint16_t ADC_Regular_Conversion_Data_Get(void)
{
/* Return the conversion value */
return (uint16_t)ADC->DAT0;
}
/**
*\*\name ADC_Regular_Group_Conversion_Data_Get.
*\*\fun Get ADC regular group conversion data.
*\*\param number :
*\*\ - 0~4
*\*\return ADC regular group conversion data.
**/
uint16_t ADC_Regular_Group_Conversion_Data_Get(uint8_t number)
{
/* Return the conversion value */
return ADC_DATA_REG_READ(ADC->DAT0,number);
}
/**
*\*\name ADC_Analog_Watchdog_Mode_Channel_Config.
*\*\fun Configures ADC analog watchdog single mode or scan mode,
*\*\ and single mode channel operation.
*\*\param mode :
*\*\ - ADC_ANALOG_WTDG_SINGLE_MODE
*\*\ - ADC_ANALOG_WTDG_SCAN_MODE
*\*\param channel :
*\*\ - ADC_ANALOG_WTDG_SINGLE_CH0
*\*\ - ADC_ANALOG_WTDG_SINGLE_CH1
*\*\ - ADC_ANALOG_WTDG_SINGLE_CH2
*\*\ - ADC_ANALOG_WTDG_SINGLE_CH3
*\*\ - ADC_ANALOG_WTDG_SINGLE_CH4
*\*\ - ADC_ANALOG_WTDG_SINGLE_CH5
*\*\ - ADC_ANALOG_WTDG_SINGLE_CH6
*\*\ - ADC_ANALOG_WTDG_SINGLE_CH7
*\*\ - ADC_ANALOG_WTDG_SINGLE_CH8
*\*\ - ADC_ANALOG_WTDG_SINGLE_CH9
*\*\ - ADC_ANALOG_WTDG_SINGLE_CH10
*\*\return none
**/
void ADC_Analog_Watchdog_Mode_Channel_Config(uint32_t mode, uint8_t channel)
{
/* ADC analog watchdog single mode */
if(mode == ADC_ANALOG_WTDG_SINGLE_MODE)
{
ADC->CTRL1 |= mode;
/* Clear ADC analog watchdog single mode channel */
ADC->CTRL1 &= ADC_ANALOG_WTDG_SINGLE_CH_MASK;
/* Select ADC analog watchdog single mode channel */
ADC->CTRL1 |= (uint32_t)channel;
}
/* ADC analog watchdog scan mode */
else
{
ADC->CTRL1 &= ADC_ANALOG_WTDG_MODE_MASK;
}
}
/**
*\*\name ADC_Analog_Watchdog_Enable.
*\*\fun Enable ADC Analog watchdog.
*\*\param wcdg_mode :
*\*\ - ADC_ANALOG_WTDG_REGULAR
*\*\return none
**/
void ADC_Analog_Watchdog_Enable(uint32_t wcdg_mode)
{
/* Set the ADC_CTRL1 AWDGERCH bit */
ADC->CTRL1 |= wcdg_mode;
}
/**
*\*\name ADC_Analog_Watchdog_Disable.
*\*\fun Disable ADC Analog watchdog.
*\*\param wcdg_mode :
*\*\ - ADC_ANALOG_WTDG_REGULAR
*\*\return none
**/
void ADC_Analog_Watchdog_Disable(uint32_t wcdg_mode)
{
/* Clean the ADC_CTRL1 AWDGERCH bit */
ADC->CTRL1 &= (~wcdg_mode);
}
/**
*\*\name ADC_Analog_Watchdog_HighThresholds_Config.
*\*\fun Configures the high thresholds of the analog watchdog.
*\*\param high_thresholds : 12bit high thresholds value(0 ~ 0xFFF)
*\*\return none
**/
void ADC_Analog_Watchdog_HighThresholds_Config(uint16_t high_thresholds)
{
/* Set the ADC high thresholds */
ADC->WDGHIGH = high_thresholds;
}
/**
*\*\name ADC_Analog_Watchdog_LowThresholds_Config.
*\*\fun Configures the low thresholds of the analog watchdog.
*\*\param low_thresholds : 12bit low thresholds value(0 ~ 0xFFF)
*\*\return none
**/
void ADC_Analog_Watchdog_LowThresholds_Config(uint16_t low_thresholds)
{
/* Set the ADC low thresholds */
ADC->WDGLOW = low_thresholds;
}
/**
*\*\name ADC_INTFlag_Status_Get.
*\*\fun Get ADC flag Status.
*\*\param adc_flag :
*\*\ - ADC_INT_FLAG_AWDG
*\*\ - ADC_INT_FLAG_ENDC
*\*\ - ADC_INT_FLAG_ENDCA
*\*\return SET or RESET
**/
FlagStatus ADC_INTFlag_Status_Get(uint8_t adc_flag)
{
/* Check the status of ADC flag */
if ((ADC->STS & adc_flag) != (uint8_t)RESET)
{
/* ADC_FLAG is set */
return SET;
}
else
{
/* ADC_FLAG is reset */
return RESET;
}
}
/**
*\*\name ADC_Flag_Status_Get.
*\*\fun Get ADC flag Status.
*\*\param selflag :
*\*\ - ADC_RUN_FLAG
*\*\ - ADC_RD_FLAG
*\*\param adc_runflag :
*\*\ - ADC_FLAG_AWDG
*\*\ - ADC_FLAG_ENDC
*\*\ - ADC_FLAG_STR
*\*\ - ADC_FLAG_ENDCA
*\*\param adc_rdflag :
*\*\ - ADC_FLAG_BUF_RDY
*\*\ - ADC_FLAG_RDY
*\*\ - ADC_FLAG_PD_RDY
*\*\return SET or RESET
**/
FlagStatus ADC_Flag_Status_Get(uint8_t selflag, uint8_t adc_runflag, uint8_t adc_rdflag)
{
if(selflag == ADC_RUN_FLAG)
{
/* Check the status of ADC flag */
if ((ADC->STS & adc_runflag) != (uint8_t)RESET)
{
/* ADC_FLAG is set */
return SET;
}
else
{
/* ADC_FLAG is reset */
return RESET;
}
}
else
{
if ((ADC->CTRL3 & adc_rdflag) != (uint8_t)RESET)
{
/* ADC_FLAG is set */
return SET;
}
else
{
/* ADC_FLAG is reset */
return RESET;
}
}
}
/**
*\*\name ADC_INTFlag_Status_Clear.
*\*\fun Clear ADC flag Status.
*\*\param adc_flag :
*\*\ - ADC_INT_FLAG_AWDG
*\*\ - ADC_INT_FLAG_ENDC
*\*\ - ADC_INT_FLAG_ENDCA
*\*\return SET or RESET
**/
void ADC_INTFlag_Status_Clear(uint8_t adc_flag)
{
/* Clear the selected ADC flag Status */
ADC->STS &= ~(uint32_t)adc_flag;
}
/**
*\*\name ADC_Flag_Status_Clear.
*\*\fun Clear ADC flag Status.
*\*\param adc_flag :
*\*\ - ADC_FLAG_AWDG
*\*\ - ADC_FLAG_ENDC
*\*\ - ADC_FLAG_STR
*\*\ - ADC_FLAG_ENDCA
*\*\return SET or RESET
**/
void ADC_Flag_Status_Clear(uint8_t adc_flag)
{
/* Clear the selected ADC flag Status */
ADC->STS &= ~(uint32_t)adc_flag;
}
/**
*\*\name ADC_Regular_Sequence_Single_Config.
*\*\fun Configures ADC channel Single in regular sequence.
*\*\param channel :
*\*\ - ADC_CH_0
*\*\ - ADC_CH_1
*\*\ - ADC_CH_2
*\*\ - ADC_CH_3
*\*\ - ADC_CH_4
*\*\ - ADC_CH_5
*\*\ - ADC_CH_6
*\*\ - ADC_CH_7
*\*\ - ADC_CH_8
*\*\ - ADC_CH_9
*\*\ - ADC_CH_10
*\*\return none
**/
void ADC_Regular_Sequence_Single_Config(uint8_t channel)
{
/* ADC regular sequence register configures channelx */
ADC->DAT0 &= ADC_SQR_MASK;
ADC->DAT0 |= (channel<<ADC_SQR_OFFSET);
}
/**
*\*\name ADC_Regular_Sequence_Multi_Config.
*\*\fun Configures ADC channel Multi in regular sequence.
*\*\param channel :
*\*\ - ADC_CH_0
*\*\ - ADC_CH_1
*\*\ - ADC_CH_2
*\*\ - ADC_CH_3
*\*\ - ADC_CH_4
*\*\ - ADC_CH_5
*\*\ - ADC_CH_6
*\*\ - ADC_CH_7
*\*\ - ADC_CH_8
*\*\ - ADC_CH_9
*\*\ - ADC_CH_10
*\*\param number :
*\*\ - ADC_DATA_OFFSET0
*\*\ - ADC_DATA_OFFSET1
*\*\ - ADC_DATA_OFFSET2
*\*\ - ADC_DATA_OFFSET3
*\*\ - ADC_DATA_OFFSET4
*\*\return none
**/
void ADC_Regular_Sequence_Multi_Config(uint8_t channel,uint8_t number)
{
/* ADC regular sequence register configures channelx */
if(number == ADC_DATA_OFFSET0)
{
ADC->DAT0 &= ADC_SQR_MASK;
ADC->DAT0 |= (channel<<ADC_SQR_OFFSET);
}
else if(number == ADC_DATA_OFFSET1)
{
ADC->DAT1 &= ADC_SQR_MASK;
ADC->DAT1 |= (channel<<ADC_SQR_OFFSET);
}
else if(number == ADC_DATA_OFFSET2)
{
ADC->DAT2 &= ADC_SQR_MASK;
ADC->DAT2 |= (channel<<ADC_SQR_OFFSET);
}
else if(number == ADC_DATA_OFFSET3)
{
ADC->DAT3 &= ADC_SQR_MASK;
ADC->DAT3 |= (channel<<ADC_SQR_OFFSET);
}
else if(number == ADC_DATA_OFFSET4)
{
ADC->DAT4 &= ADC_SQR_MASK;
ADC->DAT4 |= (channel<<ADC_SQR_OFFSET);
}
}
/**
*\*\name ADC_Internal_Input_Buffer_Enable.
*\*\fun ADC internal input buffer enable
*\*\return none
**/
void ADC_Internal_Input_Buffer_Enable(void)
{
/* Enable Vbat monitor */
ADC->CTRL3 |= ADC_IN_BUFFER_ENABLE;
}
/**
*\*\name ADC_Vbat_Monitor_Disable.
*\*\fun ADC internal input buffer disable
*\*\return none
**/
void ADC_Internal_Input_Buffer_Disable(void)
{
/* Disable Vbat monitor */
ADC->CTRL3 &= ADC_IN_BUFFER_DISABLE;
}

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/**
* Copyright (c) 2022, Nations Technologies Inc.
*
* All rights reserved.
*
* This software is the exclusive property of Nations Technologies Inc. (Hereinafter
* referred to as NATIONS). This software, and the product of NATIONS described herein
* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties
* of the People's Republic of China and other applicable jurisdictions worldwide.
*
* NATIONS does not grant any license under its patents, copyrights, trademarks, or other
* intellectual property rights. Names and brands of third party may be mentioned or referred
* thereto (if any) for identification purposes only.
*
* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and
* improvements to this software at any time without notice. Please contact NATIONS and obtain
* the latest version of this software before placing orders.
* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes
* no responsibility for the accuracy and reliability of this software.
*
* It is the responsibility of the user of this software to properly design, program, and test
* the functionality and safety of any application made of this information and any resulting product.
* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or
* consequential damages arising in any way out of the use of this software or the Product.
*
* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any
* malfunction or failure of which may cause loss of human life, bodily injury or severe property
* damage. Such applications are deemed, "Insecure Usage".
*
* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS
* harmless from and against all claims, costs, damages, and other liabilities, arising from or related
* to any customer's Insecure Usage.
* Any express or implied warranty with regard to this software or the Product, including,but not
* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement
* are disclaimed to the fullest extent permitted by law.
* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe
* or otherwise distribute this software for any purposes, in whole or in part.
*
* NATIONS products and technologies shall not be used for or incorporated into any products or systems
* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations.
* User shall comply with any applicable export control laws and regulations promulgated and administered by
* the governments of any countries asserting jurisdiction over the parties or transactions.
**/
/**
*\*\file n32g003_beeper.c
*\*\author Nations
*\*\version v1.0.0
*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
**/
#include "n32g003_beeper.h"
/**
*\*\name BEEPER_Reset.
*\*\fun Reset the BEEPER register to it's default reset values.
*\*\param none.
*\*\return none.
**/
void BEEPER_Reset(void)
{
RCC_Peripheral_Reset(RCC_RST_BEEPRST);
}
/**
*\*\name BEEPER_Frequency_Select.
*\*\fun Beeper output frequency selection.
*\*\param freq_selection:
-BEEPER_FREQ_8KHZ
-BEEPER_FREQ_4KHZ
-BEEPER_FREQ_2KHZ
-BEEPER_FREQ_1KHZ
*\*\return none.
**/
void BEEPER_Frequency_Select(uint32_t freq_selection)
{
BEEPER->CTRL &= BEEPER_FREQ_SEL_MASK;
BEEPER->CTRL |= freq_selection;
}
/**
*\*\name BEEPER_Inverted_Enable.
*\*\fun Beeper complementary output enable.
*\*\param none.
*\*\return none.
**/
void BEEPER_Inverted_Enable(void)
{
BEEPER->CTRL |= BEEPER_INV_ENABLE;
}
/**
*\*\name BEEPER_Inverted_Disable.
*\*\fun Beeper complementary output disable.
*\*\param none.
*\*\return none.
**/
void BEEPER_Inverted_Disable(void)
{
BEEPER->CTRL &= BEEPER_INV_DISABLE;
}
/**
*\*\name BEEPER_Enable.
*\*\fun Enable beeper.
*\*\param none.
*\*\return none.
**/
void BEEPER_Enable(void)
{
BEEPER->CTRL |= BEEPER_ENABLE;
}
/**
*\*\name BEEPER_Disable.
*\*\fun Disable beeper.
*\*\param none.
*\*\return none.
**/
void BEEPER_Disable(void)
{
BEEPER->CTRL &= BEEPER_DISABLE;
}

508
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/**
* Copyright (c) 2022, Nations Technologies Inc.
*
* All rights reserved.
*
* This software is the exclusive property of Nations Technologies Inc. (Hereinafter
* referred to as NATIONS). This software, and the product of NATIONS described herein
* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties
* of the People's Republic of China and other applicable jurisdictions worldwide.
*
* NATIONS does not grant any license under its patents, copyrights, trademarks, or other
* intellectual property rights. Names and brands of third party may be mentioned or referred
* thereto (if any) for identification purposes only.
*
* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and
* improvements to this software at any time without notice. Please contact NATIONS and obtain
* the latest version of this software before placing orders.
* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes
* no responsibility for the accuracy and reliability of this software.
*
* It is the responsibility of the user of this software to properly design, program, and test
* the functionality and safety of any application made of this information and any resulting product.
* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or
* consequential damages arising in any way out of the use of this software or the Product.
*
* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any
* malfunction or failure of which may cause loss of human life, bodily injury or severe property
* damage. Such applications are deemed, "Insecure Usage".
*
* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS
* harmless from and against all claims, costs, damages, and other liabilities, arising from or related
* to any customer's Insecure Usage.
* Any express or implied warranty with regard to this software or the Product, including,but not
* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement
* are disclaimed to the fullest extent permitted by law.
* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe
* or otherwise distribute this software for any purposes, in whole or in part.
*
* NATIONS products and technologies shall not be used for or incorporated into any products or systems
* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations.
* User shall comply with any applicable export control laws and regulations promulgated and administered by
* the governments of any countries asserting jurisdiction over the parties or transactions.
**/
/**
*\*\file n32g003_comp.c
*\*\author Nations
*\*\version v1.0.0
*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
**/
#include "n32g003_comp.h"
#include "n32g003_rcc.h"
/** COMP Driving Functions Declaration**/
/**
*\*\name COMP_Reset.
*\*\fun Reset the COMP registers.
*\*\return none
**/
void COMP_Reset(void)
{
RCC_Peripheral_Reset(RCC_RST_COMPRST);
}
/**
*\*\name COMP_Initializes_Structure.
*\*\fun Fills all COMP_initstruct member with default value.
*\*\param COMP_initstruct :
*\*\ - Blking
*\*\ - Hyst
*\*\ - PolRev
*\*\ - OutSel
*\*\ - SubSel
*\*\ - InpSel
*\*\ - InmSel
*\*\ - FilterEn
*\*\ - ClkPsc
*\*\ - SampWindow
*\*\ - Threshold
*\*\ - En
*\*\return none
**/
void COMP_Initializes_Structure(COMP_InitType* COMP_initstruct)
{
/* Reset COMP init structure parameters values */
/* Initialize the Blking */
COMP_initstruct->Blking = COMP_BLANKING_NO;
/* Initialize the Hyst */
COMP_initstruct->Hyst = COMP_HYST_NO;
/* Initialize the PolRev */
COMP_initstruct->PolRev = COMP_OUTPOL_NFLIP;
/* Initialize the OutSel */
COMP_initstruct->OutSel = COMP_OUTSEL_RES;
/* Initialize the SubSel */
COMP_initstruct->SubSel = COMP_SUB_NO;
/* Initialize the InpSel */
COMP_initstruct->InpSel = COMP_INPSEL_RES;
/* Initialize the InmSel */
COMP_initstruct->InmSel = COMP_INMSEL_RES;
/* Initialize the FilterEn */
COMP_initstruct->FilterEn = DISABLE;
/* Initialize the ClkPsc */
COMP_initstruct->ClkPsc = 0;
/* Initialize the SampWindow */
COMP_initstruct->SampWindow = 0;
/* Initialize the Threshold */
COMP_initstruct->Threshold = 0;
/* Initialize the En */
COMP_initstruct->En = DISABLE;
}
/**
*\*\name COMP_Filter_SampWindow_Config.
*\*\fun Configures the COMP filter sampwindow with a correct value.
*\*\param sampwin;_value:
*\*\ - from 0 to 31.
*\*\return none
**/
void COMP_Filter_SampWindow_Config(uint8_t sampwin_value)
{
/* Clear COMP_FILC SAMPW[4:0] bits */
COMP->FILC &= COMP_FILTER_SAMPW_MASK;
/* Set COMP_FILC SAMPW[4:0] bits */
COMP->FILC |= sampwin_value << REG_BIT6_OFFSET;
}
/**
*\*\name COMP_Filter_Threshold_Config.
*\*\fun Configures the COMP filter Threshold with a correct value.
*\*\param Threshold_value:
*\*\ - Value must be greater than SAMPW / 2 .
*\*\return none
**/
void COMP_Filter_Threshold_Config(uint8_t Threshold_value)
{
/* Clear COMP_FILC THRESH[4:0] bits */
COMP->FILC &= COMP_FILTER_THRESHOLD_MASK;
/* Set COMP_FILC THRESH[4:0] bits */
COMP->FILC |= Threshold_value << REG_BIT1_OFFSET;
}
/**
*\*\name COMP_Filter_Enable.
*\*\fun Configures COMP filter enable.
*\*\ - Before the COMP filter is enabled, the clock of the COMP filter must be turned on.
*\*\ - Configure RCC_APB1PCLKEN. COMPFILTEN = 1 to enable COMP filter, the RCC driver function can configure this.
*\*\return none
**/
void COMP_Filter_Enable(void)
{
/* Set COMP_FILC FILTER bits */
COMP->FILC |= COMP_FILTER_ENABLE;
}
/**
*\*\name COMP_Filter_Disable.
*\*\fun Configures COMP filter disable.
*\*\return none
**/
void COMP_Filter_Disable(void)
{
/* Clear COMP_FILC FILTER bits */
COMP->FILC &= COMP_FILTER_DISABLE;
}
/**
*\*\name COMP_Filter_Clock_Prescale_Config.
*\*\fun Configures The COMP low filter prescale .
*\*\param clkpsc_value:
*\*\ Value can be set from 0 to 65535.
*\*\return none
**/
void COMP_Filter_Clock_Prescale_Config(uint16_t clkpsc_value)
{
/* Clear COMP_FILP CLKPSC[15:0] bits */
COMP->FILP &= COMP_FILTER_CLKPSC_MASK;
/* Set COMP_FILP CLKPSC[15:0] bits */
COMP->FILP |= clkpsc_value;
}
/**
*\*\name COMP_Blking_Soucre_Config.
*\*\fun Configures TIM1 output signal to control COMP Blking.
*\*\param blking_mode :
*\*\ - COMP_BLANKING_NO
*\*\ - COMP_BLANKING_TIM1_OC5
*\*\return none
**/
void COMP_Blking_Soucre_Config(uint32_t blking_mode)
{
/* Clear COMP_CTRL BLKING bit */
COMP->CTRL &= COMP_BLANKING_MASK;
/* Set COMP_CTRL BLKING bit */
COMP->CTRL |= blking_mode;
}
/**
*\*\name COMP_Subtract_Level_Config.
*\*\fun Configures COMP Subtract level.
*\*\param sub_mode :
*\*\ - COMP_SUB_NO
*\*\ - COMP_SUB_100mV
*\*\ - COMP_SUB_200mV
*\*\ - COMP_SUB_300mV
*\*\return none
**/
void COMP_Subtract_Level_Config(uint32_t sub_mode)
{
/* Clear COMP_CTRL CMPVOS[1:0] bits */
COMP->CTRL &= COMP_SUB_MASK;
/* Set COMP_CTRL CMPVOS[1:0] bits */
COMP->CTRL |= sub_mode;
}
/**
*\*\name COMP_Hysteresis_Level_Config.
*\*\fun Configures COMP hysteresis level.
*\*\param hyst_mode :
*\*\ - COMP_HYST_NO
*\*\ - COMP_HYST_LOW 5.1mV-level
*\*\ - COMP_HYST_MID 15mV-level
*\*\ - COMP_HYST_HIGH 25mV-level
*\*\return none
**/
void COMP_Hysteresis_Level_Config(uint32_t hyst_mode)
{
/* Clear COMP_CTRL HYST[1:0] bits */
COMP->CTRL &= COMP_HYST_MASK;
/* Set COMP_CTRL HYST[1:0] bits */
COMP->CTRL |= hyst_mode;
}
/**
*\*\name COMP_Output_Polarity_Config.
*\*\fun Configures COMP output signal polarity overturn or not.
*\*\param output_pol :
*\*\ - COMP_OUTPOL_FLIP
*\*\ - COMP_OUTPOL_NFLIP
*\*\return none
**/
void COMP_Output_Polarity_Config(uint32_t output_pol)
{
/* Clear COMP_CTRL POL bits */
COMP->CTRL &= COMP_OUTPOL_MASK;
/* Set COMP_CTRL POL bits */
COMP->CTRL |= output_pol;
}
/**
*\*\name COMP_InpSel_Config.
*\*\fun Configures COMP inpsel.
*\*\param vpsel :
*\*\ comp inp sel
*\*\ - COMP_INPSEL_PB0
*\*\ - COMP_INPSEL_PA5
*\*\return none
**/
void COMP_InpSel_Config(uint32_t vpsel)
{
/* Clear COMP_CTRL INPSEL bit */
COMP->CTRL &= COMP_INPSEL_MASK;
/* Set COMP_CTRL INPSEL bit */
COMP->CTRL |= vpsel;
}
/**
*\*\name COMP_InmSel_Config.
*\*\fun Configures COMP inmsel.
*\*\param vpsel :
*\*\ comp inm sel
*\*\ - COMP_INMSEL_PB1
*\*\ - COMP_INMSEL_PA4
*\*\return none
**/
void COMP_InmSel_Config(uint32_t vpsel)
{
/* Clear COMP_CTRL INMSEL bit */
COMP->CTRL &= COMP_INMSEL_MASK;
/* Set COMP_CTRL INMSEL bit */
COMP->CTRL |= vpsel;
}
/**
*\*\name COMP_Output_Trigger_Config.
*\*\fun Configures which Timer input must be connected with the comparator output.
*\*\param outtrgsel :
*\*\ comp out trig
*\*\ - COMP_OUTSEL_NO
*\*\ - COMP_OUTSEL_TIM1_BKIN
*\*\ - COMP_OUTSEL_TIM1_IC1
*\*\ - COMP_OUTSEL_TIM1_OCREFCLEAR
*\*\ - COMP_OUTSEL_TIM3_IC1
*\*\ - COMP_OUTSEL_TIM3_OCREFCLEAR
*\*\return none
**/
void COMP_Output_Trigger_Config(uint32_t outtrgsel)
{
/* Clear COMP_CSR OUTSEL[3:0] bits */
COMP->CTRL &= COMP_OUTSEL_MASK;
/* Set COMP_CSR OUTSEL[3:0] bits */
COMP->CTRL |= outtrgsel;
}
/**
*\*\name COMP_ON.
*\*\fun Enable COMP.
*\*\return none
**/
void COMP_ON(void)
{
/* Set the COMP_CTRL EN bit to wake up the COMP from power down mode */
COMP->CTRL |= COMP_ENABLE;
}
/**
*\*\name COMP_OFF.
*\*\fun Disable COMP.
*\*\return none
**/
void COMP_OFF(void)
{
/* Clear the COMP_CTRL EN bit, The COMP go to power down mode */
COMP->CTRL &= COMP_DISABLE;
}
/**
*\*\name COMP_Lock_Config.
*\*\fun Configures COMP will be Locked.
*\*\return none
**/
void COMP_Lock_Config(void)
{
COMP->LOCK |= COMP_LOCK ;
}
/**
*\*\name COMP_Interrupt_Enable.
*\*\fun Configures COMP interrupt enable.
*\*\param IntEn :
*\*\ - COMP_INTEN
*\*\return none
**/
void COMP_Interrupt_Enable(uint32_t inten)
{
COMP->INTEN |= inten;
}
/**
*\*\name COMP_Interrupt_Disable.
*\*\fun Configures COMP interrupt disable.
*\*\param IntEn :
*\*\ - COMP_INTEN
*\*\return none
**/
void COMP_Interrupt_Disable(uint32_t inten)
{
COMP->INTEN &= ~inten;
}
/**
*\*\name COMP_Interrupt_Status_Get.
*\*\fun Get COMP interrupt Status.
*\*\return
*\*\ - COMP_INTSTS
**/
uint8_t COMP_Interrupt_Status_Get(void)
{
return COMP->INTSTS;
}
/**
*\*\name COMP_Interrupt_Status_Clear.
*\*\fun Clear COMP interrupt flag.
*\*\return none
**/
void COMP_Interrupt_Status_Clear(void)
{
COMP->INTSTS &= COMP_INTS_CLEAR;
}
/**
*\*\name COMP_Output_Status_Get.
*\*\fun Get COMP Output Status.
*\*\return FlagStatus:
*\*\ - SET
*\*\ - RESET
**/
FlagStatus COMP_Output_Status_Get(void)
{
return (COMP->CTRL & COMP_OUT) ? SET : RESET;
}
/**
*\*\name COMP_Filter_Control_Config.
*\*\fun Configures the COMP filter control value.
*\*\param sw :
*\*\ - ENABLE
*\*\ - DISABLE
*\*\param threshnum :
*\*\ - Threshold Value need > SampWindow/2.
*\*\param sampwindow :
*\*\ - Value can be set from 0 to 31.
*\*\return none
**/
void COMP_Filter_Control_Config(uint32_t sw, uint8_t threshold , uint8_t sampwindow)
{
COMP_Filter_SampWindow_Config(sampwindow);
COMP_Filter_Threshold_Config(threshold);
if(sw == ENABLE)
{
COMP_Filter_Enable();
}
else
{
COMP_Filter_Disable();
}
}
/**
*\*\name COMP_Initializes.
*\*\fun Initializes the COMP according to COMP_initstruct.
*\*\param COMP_initstruct :
*\*\ - Blking
*\*\ - COMP_BLANKING_NO
*\*\ - COMP_BLANKING_TIM1_OC5
*\*\ - Hyst
*\*\ - COMP_HYST_NO
*\*\ - COMP_HYST_LOW
*\*\ - COMP_HYST_MID
*\*\ - COMP_HYST_HIGH
*\*\ - PolRev
*\*\ - COMP_OUTPOL_FLIP
*\*\ - COMP_OUTPOL_NFLIP
*\*\ - OutSel
*\*\ comp out trig
*\*\ - COMP_OUTSEL_NO
*\*\ - COMP_OUTSEL_TIM1_BKIN
*\*\ - COMP_OUTSEL_TIM1_IC1
*\*\ - COMP_OUTSEL_TIM1_OCREFCLEAR
*\*\ - COMP_OUTSEL_TIM3_IC1
*\*\ - COMP_OUTSEL_TIM3_OCREFCLEAR
*\*\ - SubSel
*\*\ - COMP_SUB_NO
*\*\ - COMP_SUB_100mV
*\*\ - COMP_SUB_200mV
*\*\ - COMP_SUB_300mV
*\*\ - InpSel
*\*\ comp inp sel
*\*\ - COMP_INPSEL_PB0
*\*\ - COMP_INPSEL_PA5
*\*\ - InmSel
*\*\ comp inm sel
*\*\ - COMP_INMSEL_PB1
*\*\ - COMP_INMSEL_PA4
*\*\ - En
*\*\ - ENABLE
*\*\ - DISABLE
*\*\ - SampWindow
*\*\ - SampWindow Value ranges from 0~31.
*\*\ - Threshold
*\*\ - Threshold Value need > SampWindow/2.
*\*\ - FilterEn
*\*\ - ENABLE
*\*\ - DISABLE
*\*\ - ClkPsc
*\*\ - ClkPsc Value ranges from 0~36635.
*\*\return none
**/
void COMP_Initializes(COMP_InitType* COMP_initstruct)
{
/** filter configures **/
COMP_Filter_SampWindow_Config(COMP_initstruct->SampWindow);
COMP_Filter_Threshold_Config( COMP_initstruct->Threshold);
if(COMP_initstruct->FilterEn == ENABLE)
{
COMP_Filter_Enable();
}
else
{
COMP_Filter_Disable();
}
/** filter clock Prescale configures **/
COMP_Filter_Clock_Prescale_Config(COMP_initstruct->ClkPsc);
/** ctrl configures**/
COMP_Blking_Soucre_Config(COMP_initstruct->Blking);
COMP_Hysteresis_Level_Config(COMP_initstruct->Hyst);
COMP_Output_Polarity_Config(COMP_initstruct->PolRev);
COMP_Subtract_Level_Config(COMP_initstruct->SubSel);
COMP_InpSel_Config(COMP_initstruct->InpSel);
COMP_InmSel_Config(COMP_initstruct->InmSel);
COMP_Output_Trigger_Config(COMP_initstruct->OutSel);
/** comp enable or disable configures*/
if (COMP_initstruct->En == ENABLE)
COMP_ON();
else
COMP_OFF();
}

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/**
* Copyright (c) 2022, Nations Technologies Inc.
*
* All rights reserved.
*
* This software is the exclusive property of Nations Technologies Inc. (Hereinafter
* referred to as NATIONS). This software, and the product of NATIONS described herein
* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties
* of the People's Republic of China and other applicable jurisdictions worldwide.
*
* NATIONS does not grant any license under its patents, copyrights, trademarks, or other
* intellectual property rights. Names and brands of third party may be mentioned or referred
* thereto (if any) for identification purposes only.
*
* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and
* improvements to this software at any time without notice. Please contact NATIONS and obtain
* the latest version of this software before placing orders.
* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes
* no responsibility for the accuracy and reliability of this software.
*
* It is the responsibility of the user of this software to properly design, program, and test
* the functionality and safety of any application made of this information and any resulting product.
* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or
* consequential damages arising in any way out of the use of this software or the Product.
*
* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any
* malfunction or failure of which may cause loss of human life, bodily injury or severe property
* damage. Such applications are deemed, "Insecure Usage".
*
* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS
* harmless from and against all claims, costs, damages, and other liabilities, arising from or related
* to any customer's Insecure Usage.
* Any express or implied warranty with regard to this software or the Product, including,but not
* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement
* are disclaimed to the fullest extent permitted by law.
* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe
* or otherwise distribute this software for any purposes, in whole or in part.
*
* NATIONS products and technologies shall not be used for or incorporated into any products or systems
* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations.
* User shall comply with any applicable export control laws and regulations promulgated and administered by
* the governments of any countries asserting jurisdiction over the parties or transactions.
**/
/**
*\*\file n32g003_crc.c
*\*\author Nations
*\*\version v1.0.0
*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
*/
#include "n32g003_crc.h"
/** CRC Private Defines **/
/** CRC Driving Functions Declaration **/
/**
*\*\name CRC16_Calculate.
*\*\fun Computes the 16-bit CRC of a given data word(8-bit).
*\*\param data :
*\*\ - data word(8-bit) to compute its CRC
*\*\return 16-bit CRC
**/
uint16_t CRC16_Calculate(uint8_t data)
{
/* Write data to the CRC16DAT register */
CRC->CRC16DAT = data;
/* Returns the computed CRC16 result */
return (CRC->CRC16D);
}
/**
*\*\name CRC16_Buffer_Calculate.
*\*\fun Computes the 16-bit CRC of a given buffer of data word(8-bit).
*\*\param p_buf :
*\*\ - pointer to the buffer containing the data to be computed
*\*\param buf_len :
*\*\ - length of the buffer to be computed
*\*\return 16-bit CRC
**/
uint16_t CRC16_Buffer_Calculate(uint8_t p_buf[], uint32_t buf_len)
{
uint32_t index = 0;
CRC->CRC16D = 0x00;
for (index = 0; index < buf_len; index++)
{
/* Write data to the CRC16DAT register */
CRC->CRC16DAT = p_buf[index];
}
/* Returns the computed CRC16 result */
return (CRC->CRC16D);
}
/**
*\*\name CRC16_Set.
*\*\fun write a 8-bit data in the 16-bit CRC Data register.
*\*\param data :
*\*\ - 8-bit data value to be writed in the 16-bit CRC Data register
*\*\return none
**/
void CRC16_Set(uint8_t data)
{
/* Writes 8-bit data to the CRC16DAT register */
CRC->CRC16DAT = data;
}
/**
*\*\name CRC16_Get.
*\*\fun Returns the current CRC value.
*\*\param none
*\*\return 16-bit CRC
**/
uint16_t CRC16_Get(void)
{
/* Returns the CRC16 calculation result */
return (CRC->CRC16D);
}
/**
*\*\name CRC16_Little_Endian_Format_Set.
*\*\fun Set the calculate data to little endian format.
*\*\param none
*\*\return none
**/
void CRC16_Little_Endian_Format_Set(void)
{
CRC->CRC16CTRL |= CRC_LITTLE_ENDIAN_ENABLE;
}
/**
*\*\name CRC16_Big_Endian_Format_Set.
*\*\fun Set the calculate data to big endian format.
*\*\param none
*\*\return none
**/
void CRC16_Big_Endian_Format_Set(void)
{
CRC->CRC16CTRL &= CRC_BIG_ENDIAN_ENABLE;
}
/**
*\*\name CRC16_Value_Clean_Enable.
*\*\fun Enable Clean CRC16 value.
*\*\param none
*\*\return none
**/
void CRC16_Value_Clean_Enable(void)
{
CRC->CRC16CTRL |= CRC_CRC16_VALUE_CLEAR;
}
/**
*\*\name CRC16_Value_Clean_Disable.
*\*\fun Disable Clean CRC16 value.
*\*\param none
*\*\return none
**/
void CRC16_Value_Clean_Disable(void)
{
CRC->CRC16CTRL &= CRC_CRC16_VALUE_NO_CLEAR;
}
/**
*\*\name CRC_LRC_Set.
*\*\fun Write LRC initial value.
*\*\param data :
*\*\ - 8-bit data
*\*\return none
**/
void CRC_LRC_Set(uint8_t data)
{
/* Write LRC to verify the initial value */
CRC->LRC = data;
}
/**
*\*\name CRC_LRC_Get.
*\*\fun Returns the current LRC value.
*\*\param none
*\*\return 8-bit LRC
**/
uint8_t CRC_LRC_Get(void)
{
/* Returns the LRC check value */
return (CRC->LRC);
}

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/**
* Copyright (c) 2022, Nations Technologies Inc.
*
* All rights reserved.
*
* This software is the exclusive property of Nations Technologies Inc. (Hereinafter
* referred to as NATIONS). This software, and the product of NATIONS described herein
* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties
* of the People's Republic of China and other applicable jurisdictions worldwide.
*
* NATIONS does not grant any license under its patents, copyrights, trademarks, or other
* intellectual property rights. Names and brands of third party may be mentioned or referred
* thereto (if any) for identification purposes only.
*
* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and
* improvements to this software at any time without notice. Please contact NATIONS and obtain
* the latest version of this software before placing orders.
* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes
* no responsibility for the accuracy and reliability of this software.
*
* It is the responsibility of the user of this software to properly design, program, and test
* the functionality and safety of any application made of this information and any resulting product.
* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or
* consequential damages arising in any way out of the use of this software or the Product.
*
* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any
* malfunction or failure of which may cause loss of human life, bodily injury or severe property
* damage. Such applications are deemed, "Insecure Usage".
*
* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS
* harmless from and against all claims, costs, damages, and other liabilities, arising from or related
* to any customer's Insecure Usage.
* Any express or implied warranty with regard to this software or the Product, including,but not
* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement
* are disclaimed to the fullest extent permitted by law.
* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe
* or otherwise distribute this software for any purposes, in whole or in part.
*
* NATIONS products and technologies shall not be used for or incorporated into any products or systems
* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations.
* User shall comply with any applicable export control laws and regulations promulgated and administered by
* the governments of any countries asserting jurisdiction over the parties or transactions.
**/
/**
*\*\file n32g003_dbg.c
*\*\author Nations
*\*\version v1.0.0
*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
**/
#ifndef __N32G003_DBG_H__
#define __N32G003_DBG_H__
#ifdef __cplusplus
extern "C" {
#endif
#include "n32g003.h"
#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
/**
*\*\name UCID_Get.
*\*\fun get unique customer id.
*\*\param UCIDbuf
*\*\return none
**/
void UCID_Get(uint8_t *UCIDbuf)
{
uint8_t num = 0;
uint32_t* ucid_addr = (void*)0;
uint32_t temp = 0;
ucid_addr = (uint32_t*)UCID_BASE;
for (num = 0; num < UCID_LENGTH;)
{
temp = *(__IO uint32_t*)(ucid_addr++);
UCIDbuf[num++] = (temp & 0xFF);
UCIDbuf[num++] = (temp & 0xFF00) >> 8;
UCIDbuf[num++] = (temp & 0xFF0000) >> 16;
UCIDbuf[num++] = (temp & 0xFF000000) >> 24;
}
}
/**
*\*\name UID_Get.
*\*\fun get unique device id.
*\*\param UIDbuf
*\*\return none
**/
void UID_Get(uint8_t *UIDbuf)
{
uint8_t num = 0;
uint32_t* uid_addr = (void*)0;
uint32_t temp = 0;
uid_addr = (uint32_t*)UID_BASE;
for (num = 0; num < UID_LENGTH;)
{
temp = *(__IO uint32_t*)(uid_addr++);
UIDbuf[num++] = (temp & 0xFF);
UIDbuf[num++] = (temp & 0xFF00) >> 8;
UIDbuf[num++] = (temp & 0xFF0000) >> 16;
UIDbuf[num++] = (temp & 0xFF000000) >> 24;
}
}
/**
*\*\name DBGMCU_ID_Get.
*\*\fun get debug MCU id.
*\*\param DBGIDbuf
*\*\return none
**/
void DBGMCU_ID_Get(uint8_t *DBGIDbuf)
{
uint8_t num = 0;
uint32_t* dbgid_addr = (void*)0;
uint32_t temp = 0;
dbgid_addr = (uint32_t*)DBGMCU_ID_BASE;
for (num = 0; num < DBGMCU_ID_LENGTH;)
{
temp = *(__IO uint32_t*)(dbgid_addr++);
DBGIDbuf[num++] = (temp & 0xFF);
DBGIDbuf[num++] = (temp & 0xFF00) >> 8;
DBGIDbuf[num++] = (temp & 0xFF0000) >> 16;
DBGIDbuf[num++] = (temp & 0xFF000000) >> 24;
}
}
#ifdef __cplusplus
}
#endif
#endif /*__N32G003_DBG_H__ */

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/**
* Copyright (c) 2022, Nations Technologies Inc.
*
* All rights reserved.
*
* This software is the exclusive property of Nations Technologies Inc. (Hereinafter
* referred to as NATIONS). This software, and the product of NATIONS described herein
* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties
* of the People's Republic of China and other applicable jurisdictions worldwide.
*
* NATIONS does not grant any license under its patents, copyrights, trademarks, or other
* intellectual property rights. Names and brands of third party may be mentioned or referred
* thereto (if any) for identification purposes only.
*
* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and
* improvements to this software at any time without notice. Please contact NATIONS and obtain
* the latest version of this software before placing orders.
* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes
* no responsibility for the accuracy and reliability of this software.
*
* It is the responsibility of the user of this software to properly design, program, and test
* the functionality and safety of any application made of this information and any resulting product.
* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or
* consequential damages arising in any way out of the use of this software or the Product.
*
* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any
* malfunction or failure of which may cause loss of human life, bodily injury or severe property
* damage. Such applications are deemed, "Insecure Usage".
*
* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS
* harmless from and against all claims, costs, damages, and other liabilities, arising from or related
* to any customer's Insecure Usage.
* Any express or implied warranty with regard to this software or the Product, including,but not
* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement
* are disclaimed to the fullest extent permitted by law.
* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe
* or otherwise distribute this software for any purposes, in whole or in part.
*
* NATIONS products and technologies shall not be used for or incorporated into any products or systems
* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations.
* User shall comply with any applicable export control laws and regulations promulgated and administered by
* the governments of any countries asserting jurisdiction over the parties or transactions.
**/
/**
*\*\file n32g003_exti.c
*\*\author Nations
*\*\version v1.0.0
*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
**/
#include "n32g003_exti.h"
/**
*\*\name EXTI_Reset.
*\*\fun Reset the EXTI registers.
*\*\return none
**/
void EXTI_Reset(void)
{
EXTI->IMASK = 0x00000000;
EXTI->EMASK = 0x00000000;
EXTI->RT_CFG = 0x00000000;
EXTI->FT_CFG = 0x00000000;
EXTI->PEND = 0x000FFFFF;
}
/**
*\*\name EXTI_Peripheral_Initializes.
*\*\fun Initializes the EXTI according to EXTI_InitStruct.
*\*\param EXTI_InitStruct :
*\*\ - EXTI_Mode
*\*\ - EXTI_Mode_Interrupt
*\*\ - EXTI_Mode_Event
*\*\ - EXTI_Trigger
*\*\ - EXTI_Trigger_Rising
*\*\ - EXTI_Trigger_Falling
*\*\ - EXTI_Trigger_Rising_Falling
*\*\ - EXTI_Line
*\*\ - EXTI_LINE0
*\*\ - EXTI_LINE1
*\*\ - EXTI_LINE2
*\*\ - EXTI_LINE3
*\*\ - EXTI_LINE4
*\*\ - EXTI_LINE5
*\*\ - EXTI_LINE6
*\*\ - EXTI_LINE7
*\*\ - EXTI_LINE8
*\*\ - EXTI_LINE9
*\*\ - EXTI_LINE10
*\*\ - EXTI_LINE11
*\*\ - EXTI_LINE12
*\*\ - EXTI_LINE13
*\*\ - EXTI_LINE14
*\*\ - EXTI_LINE15
*\*\ - EXTI_LINE16
*\*\ - EXTI_LINE17
*\*\ - EXTI_LINE18
*\*\ - EXTI_LINE19
*\*\ - EXTI_LineCmd
*\*\ - ENABLE
*\*\ - DISABLE
*\*\return none
**/
void EXTI_Peripheral_Initializes(EXTI_InitType* EXTI_InitStruct)
{
EXTI_Work_Mode_Config(EXTI_InitStruct->EXTI_Line,EXTI_InitStruct->EXTI_Mode);
EXTI_Trigger_Config(EXTI_InitStruct->EXTI_Line,EXTI_InitStruct->EXTI_Trigger);
EXTI_LineCmd_Disable(EXTI_InitStruct->EXTI_Line,EXTI_InitStruct->EXTI_LineCmd,EXTI_InitStruct->EXTI_Mode);
}
/**
*\*\name EXTI_Work_Mode_Config.
*\*\fun Config the EXTI according to EXTI_Mode.
*\*\param exti_mode :
*\*\ - EXTI_Mode_Interrupt
*\*\ - EXTI_Mode_Event
*\*\param exti_line :
*\*\ - EXTI_LINE0
*\*\ - EXTI_LINE1
*\*\ - EXTI_LINE2
*\*\ - EXTI_LINE3
*\*\ - EXTI_LINE4
*\*\ - EXTI_LINE5
*\*\ - EXTI_LINE6
*\*\ - EXTI_LINE7
*\*\ - EXTI_LINE8
*\*\ - EXTI_LINE9
*\*\ - EXTI_LINE10
*\*\ - EXTI_LINE11
*\*\ - EXTI_LINE12
*\*\ - EXTI_LINE13
*\*\ - EXTI_LINE14
*\*\ - EXTI_LINE15
*\*\ - EXTI_LINE16
*\*\ - EXTI_LINE17
*\*\ - EXTI_LINE18
*\*\ - EXTI_LINE19
*\*\return none
**/
void EXTI_Work_Mode_Config(uint32_t exti_line,uint32_t exti_mode)
{
uint32_t temp_value = 0;
temp_value = (uint32_t)EXTI_BASE;
/* Clear EXTI line configuration */
EXTI->IMASK &= ~exti_line;
EXTI->EMASK &= ~exti_line;
/* Select the work mode */
temp_value += exti_mode;
*(__IO uint32_t*)temp_value |= exti_line;
}
/**
*\*\name EXTI_EXTI_Trigger_Config.
*\*\fun Config the EXTI according to EXTI_Trigger.
*\*\param exti_trigger :
*\*\ - EXTI_Trigger_Rising
*\*\ - EXTI_Trigger_Falling
*\*\ - EXTI_Trigger_Rising_Falling
*\*\param exti_line :
*\*\ - EXTI_LINE0
*\*\ - EXTI_LINE1
*\*\ - EXTI_LINE2
*\*\ - EXTI_LINE3
*\*\ - EXTI_LINE4
*\*\ - EXTI_LINE5
*\*\ - EXTI_LINE6
*\*\ - EXTI_LINE7
*\*\ - EXTI_LINE8
*\*\ - EXTI_LINE9
*\*\ - EXTI_LINE10
*\*\ - EXTI_LINE11
*\*\ - EXTI_LINE12
*\*\ - EXTI_LINE13
*\*\ - EXTI_LINE14
*\*\ - EXTI_LINE15
*\*\ - EXTI_LINE16
*\*\ - EXTI_LINE17
*\*\ - EXTI_LINE18
*\*\ - EXTI_LINE19
*\*\return none
**/
void EXTI_Trigger_Config(uint32_t exti_line,uint32_t exti_trigger)
{
uint32_t temp_value = 0;//
temp_value = (uint32_t)EXTI_BASE; //
/* Clear Rising Falling edge configuration */
EXTI->RT_CFG &= ~exti_line;
EXTI->FT_CFG &= ~exti_line;
/* Select the trigger for the selected external interrupts */
if(exti_trigger == EXTI_Trigger_Rising_Falling)
{
/* Rising Falling edge */
EXTI->RT_CFG |= exti_line;
EXTI->FT_CFG |= exti_line;
}
else
{
temp_value = (uint32_t)EXTI_BASE;
temp_value += exti_trigger;
*(__IO uint32_t*)temp_value |= exti_line;
}
}
/**
*\*\name EXTI_EXTI_LineCmd_Disable.
*\*\fun Config the EXTI according to EXTI_LineCmd.
*\*\param exti_linecmd :
*\*\ - ENABLE
*\*\ - DISABLE
*\*\param exti_mode :
*\*\ - EXTI_Mode_Interrupt
*\*\ - EXTI_Mode_Event
*\*\param exti_line :
*\*\ - EXTI_LINE0
*\*\ - EXTI_LINE1
*\*\ - EXTI_LINE2
*\*\ - EXTI_LINE3
*\*\ - EXTI_LINE4
*\*\ - EXTI_LINE5
*\*\ - EXTI_LINE6
*\*\ - EXTI_LINE7
*\*\ - EXTI_LINE8
*\*\ - EXTI_LINE9
*\*\ - EXTI_LINE10
*\*\ - EXTI_LINE11
*\*\ - EXTI_LINE12
*\*\ - EXTI_LINE13
*\*\ - EXTI_LINE14
*\*\ - EXTI_LINE15
*\*\ - EXTI_LINE16
*\*\ - EXTI_LINE17
*\*\ - EXTI_LINE18
*\*\ - EXTI_LINE19
*\*\return none
**/
void EXTI_LineCmd_Disable(uint32_t exti_line,uint32_t exti_linecmd,uint32_t exti_mode)
{
uint32_t temp_value = 0;
temp_value = (uint32_t)EXTI_BASE;
/* Disable the selected external lines */
if(exti_linecmd == DISABLE)
{
temp_value += exti_mode;
/* Disable the selected external lines */
*(__IO uint32_t*)temp_value &= ~exti_line;
}
}
/**
*\*\name EXTI_Structure_Initializes.
*\*\fun Fills each EXTI_InitStruct member with its default value.
*\*\param EXTI_InitStruct :
*\*\ - EXTI_Line
*\*\ - EXTI_Mode
*\*\ - EXTI_Trigger
*\*\ - EXTI_LineCmd
*\*\return none
**/
void EXTI_Structure_Initializes(EXTI_InitType* EXTI_InitStruct)
{
EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
EXTI_InitStruct->EXTI_LineCmd = DISABLE;
}
/**
*\*\name EXTI_Software_Interrupt_Trigger.
*\*\fun Generates a Software interrupt.
*\*\param exti_line :
*\*\ - EXTI_LINE0
*\*\ - EXTI_LINE1
*\*\ - EXTI_LINE2
*\*\ - EXTI_LINE3
*\*\ - EXTI_LINE4
*\*\ - EXTI_LINE5
*\*\ - EXTI_LINE6
*\*\ - EXTI_LINE7
*\*\ - EXTI_LINE8
*\*\ - EXTI_LINE9
*\*\ - EXTI_LINE10
*\*\ - EXTI_LINE11
*\*\ - EXTI_LINE12
*\*\ - EXTI_LINE13
*\*\ - EXTI_LINE14
*\*\ - EXTI_LINE15
*\*\ - EXTI_LINE16
*\*\ - EXTI_LINE17
*\*\ - EXTI_LINE18
*\*\ - EXTI_LINE19
*\*\return none
**/
void EXTI_Software_Interrupt_Trigger(uint32_t exti_line)
{
/* Set the EXTI_SWIE ON bit, The EXTI generates a Software interrupt */
EXTI->SWIE |= exti_line;
}
/**
*\*\name EXTI_Flag_Status_Get.
*\*\fun Get EXTI line flag status.
*\*\param exti_line :
*\*\ - EXTI_LINE0
*\*\ - EXTI_LINE1
*\*\ - EXTI_LINE2
*\*\ - EXTI_LINE3
*\*\ - EXTI_LINE4
*\*\ - EXTI_LINE5
*\*\ - EXTI_LINE6
*\*\ - EXTI_LINE7
*\*\ - EXTI_LINE8
*\*\ - EXTI_LINE9
*\*\ - EXTI_LINE10
*\*\ - EXTI_LINE11
*\*\ - EXTI_LINE12
*\*\ - EXTI_LINE13
*\*\ - EXTI_LINE14
*\*\ - EXTI_LINE15
*\*\ - EXTI_LINE16
*\*\ - EXTI_LINE17
*\*\ - EXTI_LINE18
*\*\ - EXTI_LINE19
*\*\return SET or RESET
**/
FlagStatus EXTI_Flag_Status_Get(uint32_t exti_line)
{
if ((EXTI->PEND & exti_line) != (uint32_t)RESET)
{
/* EXTI line flag status is set */
return SET;
}
else
{
/* EXTI line flag status is reset */
return RESET;
}
}
/**
*\*\name EXTI_Flag_Status_Clear.
*\*\fun Clear EXTI line flag status.
*\*\param exti_line :
*\*\ - EXTI_LINE0
*\*\ - EXTI_LINE1
*\*\ - EXTI_LINE2
*\*\ - EXTI_LINE3
*\*\ - EXTI_LINE4
*\*\ - EXTI_LINE5
*\*\ - EXTI_LINE6
*\*\ - EXTI_LINE7
*\*\ - EXTI_LINE8
*\*\ - EXTI_LINE9
*\*\ - EXTI_LINE10
*\*\ - EXTI_LINE11
*\*\ - EXTI_LINE12
*\*\ - EXTI_LINE13
*\*\ - EXTI_LINE14
*\*\ - EXTI_LINE15
*\*\ - EXTI_LINE16
*\*\ - EXTI_LINE17
*\*\ - EXTI_LINE18
*\*\ - EXTI_LINE19
*\*\return none
**/
void EXTI_Flag_Status_Clear(uint32_t exti_line)
{
/* Clear EXTI line flag status. */
EXTI->PEND = exti_line;
}
/**
*\*\name EXTI_Interrupt_Status_Get.
*\*\fun GET EXTI line interrupt status.
*\*\param exti_line :
*\*\ - EXTI_LINE0
*\*\ - EXTI_LINE1
*\*\ - EXTI_LINE2
*\*\ - EXTI_LINE3
*\*\ - EXTI_LINE4
*\*\ - EXTI_LINE5
*\*\ - EXTI_LINE6
*\*\ - EXTI_LINE7
*\*\ - EXTI_LINE8
*\*\ - EXTI_LINE9
*\*\ - EXTI_LINE10
*\*\ - EXTI_LINE11
*\*\ - EXTI_LINE12
*\*\ - EXTI_LINE13
*\*\ - EXTI_LINE14
*\*\ - EXTI_LINE15
*\*\ - EXTI_LINE16
*\*\ - EXTI_LINE17
*\*\ - EXTI_LINE18
*\*\ - EXTI_LINE19
*\*\ - EXTI_LINE20
*\*\ - EXTI_LINE21
*\*\ - EXTI_LINE22
*\*\ - EXTI_LINE23
*\*\return SET or RESET
**/
ITStatus EXTI_Interrupt_Status_Get(uint32_t exti_line)
{
if (((EXTI->PEND & exti_line) != (uint32_t)RESET) && ((EXTI->IMASK & exti_line) != (uint32_t)RESET))//
{
/* EXTI line interrupt status is set */
return SET;
}
else
{
/* EXTI line interrupt status is reset */
return RESET;
}
}
/**
*\*\name EXTI_Interrupt_Status_Clear.
*\*\fun Clear EXTI line interrupt pend bit.
*\*\param exti_line :
*\*\ - EXTI_LINE0
*\*\ - EXTI_LINE1
*\*\ - EXTI_LINE2
*\*\ - EXTI_LINE3
*\*\ - EXTI_LINE4
*\*\ - EXTI_LINE5
*\*\ - EXTI_LINE6
*\*\ - EXTI_LINE7
*\*\ - EXTI_LINE8
*\*\ - EXTI_LINE9
*\*\ - EXTI_LINE10
*\*\ - EXTI_LINE11
*\*\ - EXTI_LINE12
*\*\ - EXTI_LINE13
*\*\ - EXTI_LINE14
*\*\ - EXTI_LINE15
*\*\ - EXTI_LINE16
*\*\ - EXTI_LINE17
*\*\ - EXTI_LINE18
*\*\ - EXTI_LINE19
*\*\return none
**/
void EXTI_Interrupt_Status_Clear(uint32_t exti_line)
{
/* Clear EXTI line interrupt pend bit. */
EXTI->PEND = exti_line;
}

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/**
* Copyright (c) 2022, Nations Technologies Inc.
*
* All rights reserved.
*
* This software is the exclusive property of Nations Technologies Inc. (Hereinafter
* referred to as NATIONS). This software, and the product of NATIONS described herein
* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties
* of the People's Republic of China and other applicable jurisdictions worldwide.
*
* NATIONS does not grant any license under its patents, copyrights, trademarks, or other
* intellectual property rights. Names and brands of third party may be mentioned or referred
* thereto (if any) for identification purposes only.
*
* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and
* improvements to this software at any time without notice. Please contact NATIONS and obtain
* the latest version of this software before placing orders.
* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes
* no responsibility for the accuracy and reliability of this software.
*
* It is the responsibility of the user of this software to properly design, program, and test
* the functionality and safety of any application made of this information and any resulting product.
* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or
* consequential damages arising in any way out of the use of this software or the Product.
*
* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any
* malfunction or failure of which may cause loss of human life, bodily injury or severe property
* damage. Such applications are deemed, "Insecure Usage".
*
* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS
* harmless from and against all claims, costs, damages, and other liabilities, arising from or related
* to any customer's Insecure Usage.
* Any express or implied warranty with regard to this software or the Product, including,but not
* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement
* are disclaimed to the fullest extent permitted by law.
* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe
* or otherwise distribute this software for any purposes, in whole or in part.
*
* NATIONS products and technologies shall not be used for or incorporated into any products or systems
* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations.
* User shall comply with any applicable export control laws and regulations promulgated and administered by
* the governments of any countries asserting jurisdiction over the parties or transactions.
**/
/**
*\*\file n32g003_gpio.c
*\*\author Nations
*\*\version v1.0.0
*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
**/
#include "n32g003_gpio.h"
/**
*\*\name GPIO_Reset.
*\*\fun Reset the GPIOx peripheral registers to their default reset values.
*\*\param GPIOx :
*\*\ - GPIOA
*\*\ - GPIOB
*\*\return none
*/
void GPIO_Reset(GPIO_Module* GPIOx)
{
if (GPIOx == GPIOA)
{
RCC_Peripheral_Reset(RCC_RST_GPIOARST);
}
else if (GPIOx == GPIOB)
{
RCC_Peripheral_Reset(RCC_RST_GPIOBRST);
}
else
{
return;
}
}
/**
*\*\name GPIO_Alternate_Function_Reset.
*\*\fun Reset the Alternate Function registers to their default reset values.
*\*\param none
*\*\return none
*/
void GPIO_Alternate_Function_Reset(void)
{
RCC_Peripheral_Reset(RCC_RST_AFIORST);
}
/**
*\*\name GPIOA_Pin_Reset.
*\*\fun Reset the GPIOA peripheral registers to it's default reset values.
*\*\param pin :
*\*\ - GPIO_PIN_0
*\*\ - GPIO_PIN_1
*\*\ - GPIO_PIN_2
*\*\ - GPIO_PIN_3
*\*\ - GPIO_PIN_4
*\*\ - GPIO_PIN_5
*\*\ - GPIO_PIN_6
*\*\ - GPIO_PIN_7
*\*\ - GPIO_PIN_8
*\*\ - GPIO_PIN_9
*\*\ - GPIO_PIN_10
*\*\ - GPIO_PIN_11
*\*\ - GPIO_PIN_12
*\*\ - GPIO_PIN_13
*\*\ - GPIO_PIN_14
*\*\ - GPIO_PIN_15
*\*\ - GPIO_PIN_ALL
*\*\return none
*/
void GPIOA_Pin_Reset(uint16_t pin)
{
uint32_t position = 0x00U;
uint32_t current_pin = 0x00U;
while((pin >> position) != 0)
{
/* Get the IO position */
current_pin = (pin) & (IO_POSITION_MASK << position);
if(current_pin)
{
if(position == GPIOA_POSITION1 || position == GPIOA_POSITION2)
{
/* Configure IO Direction in alternate Mode */
GPIOA->PMODE |= (GPIO_AF_MODE << (position * MULTIPLIER_FACTOR_2));
}
else
{
/* Configure IO Direction in analog Mode */
GPIOA->PMODE |= (GPIO_ANALOG_MODE << (position * MULTIPLIER_FACTOR_2));
}
/* Configure the default Alternate Function in current IO */
if(position & AF_SELECTION_MASK)
{
if(position == GPIOA_POSITION1 || position == GPIOA_POSITION2)
{
GPIOA->AFH &= ~(GPIO_AF_MASK << ((position & (uint32_t)AF_WRITE_POSITION_MASK) * MULTIPLIER_FACTOR_4));
}
else
{
GPIOA->AFH |= (GPIO_AF_MASK << ((position & (uint32_t)AF_WRITE_POSITION_MASK) * MULTIPLIER_FACTOR_4));
}
}
else
{
GPIOA->AFL |= (GPIO_AF_MASK << ((position & (uint32_t)AF_WRITE_POSITION_MASK) * MULTIPLIER_FACTOR_4));
}
/* Reset GPIO output type to push-pull output */
GPIOA->POTYPE &= ~(GPIO_POTYPE_MASK << position);
if(position == GPIOA_POSITION1)
{
/* Reset the GPIO pull mode to pull-up */
GPIOA->PUPD |= (GPIO_PU_MODE << (position * MULTIPLIER_FACTOR_2));
}
else if(position == GPIOA_POSITION2)
{
/* Reset the GPIO pull mode to pull-down */
GPIOA->PUPD |= (GPIO_PD_MODE << (position * MULTIPLIER_FACTOR_2));
}
else
{
/* Reset the GPIO pull mode to no-pull */
GPIOA->PUPD &= ~(GPIO_PUPD_MASK << (position * MULTIPLIER_FACTOR_2));
}
/* Reset the GPIO slew rate to slow */
GPIOA->SR |= (GPIO_SR_SLOW << position);
/* Reset the GPIO high driver capacity */
GPIOA->DS &= ~(GPIO_LOW_DRIVER << position);
}
position++;
}
}
/**
*\*\name GPIOB_Pin_Reset.
*\*\fun Reset the GPIOB peripheral registers to it's default reset values.
*\*\param pin :
*\*\ - GPIO_PIN_0
*\*\ - GPIO_PIN_1
*\*\return none
*/
void GPIOB_Pin_Reset(uint16_t pin)
{
uint32_t position = 0x00U;
uint32_t current_pin = 0x00U;
while((pin >> position) != 0)
{
/* Get the IO position */
current_pin = (pin) & (IO_POSITION_MASK << position);
if(current_pin)
{
/** Reset GPIO pin mode **/
/* Configure IO Direction in analog Mode */
GPIOB->PMODE |= (GPIO_ANALOG_MODE << (position * MULTIPLIER_FACTOR_2));
/** Configure the default Alternate Function in current IO **/
GPIOB->AFL |= (GPIO_AF_MASK << ((position & (uint32_t)AF_WRITE_POSITION_MASK) * MULTIPLIER_FACTOR_4));
/* Reset GPIO output type to push-pull output */
GPIOB->POTYPE &= ~(GPIO_POTYPE_MASK << position);
/* Reset the GPIO pull mode to no-pull */
GPIOB->PUPD &= ~(GPIO_PUPD_MASK << (position * MULTIPLIER_FACTOR_2));
/* Reset the GPIO slew rate to slow */
GPIOB->SR |= (GPIO_SR_SLOW << position);
/* Reset the GPIO high driver capacity */
GPIOB->DS &= ~(GPIO_LOW_DRIVER << position);
}
position++;
}
}
/**
*\*\name GPIO_Alternate_Set.
*\*\fun Configure GPIO alternate function.
*\*\param GPIOx :
*\*\ - GPIOA
*\*\ - GPIOB
*\*\ Note: When selects the GPIOB, Only GPIO_PIN_0 and GPIO_PIN_1 are valid
*\*\param alternate
*\*\ - Refer to the "alternate_function" parameter
*\*\ list of the GPIO_Pin_Remap_Set() function
*\*\param position
*\*\ - 0x00 ~ 0x0F 0x00 represents GPIO_PIN_0,
*\*\ 0x01 represents GPIO_PIN_1
*\*\ ...
*\*\ 0x0F represents GPIO_PIN_15
*\*\return none
*/
void GPIO_Alternate_Set(GPIO_Module* GPIOx, uint32_t alternate, uint32_t position)
{
uint32_t temp_value = 0x00U;
/* Configure Alternate function mapped with the current IO */
if(position & AF_SELECTION_MASK)
{
temp_value = GPIOx->AFH;
temp_value &= ~(GPIO_AF_MASK << ((uint32_t)(position & (uint32_t)AF_WRITE_POSITION_MASK) * MULTIPLIER_FACTOR_4));
temp_value |= ((uint32_t)alternate << ((uint32_t)(position & (uint32_t)AF_WRITE_POSITION_MASK) * MULTIPLIER_FACTOR_4));
GPIOx->AFH = temp_value;
}
else
{
temp_value = GPIOx->AFL;
temp_value &= ~(GPIO_AF_MASK << ((uint32_t)(position & (uint32_t)AF_WRITE_POSITION_MASK) * MULTIPLIER_FACTOR_4));
temp_value |= ((uint32_t)alternate << ((uint32_t)(position & (uint32_t)AF_WRITE_POSITION_MASK) * MULTIPLIER_FACTOR_4));
GPIOx->AFL = temp_value;
}
}
/**
*\*\name GPIO_Mode_Set.
*\*\fun Configure GPIO mode.
*\*\param GPIOx :
*\*\ - GPIOA
*\*\ - GPIOB
*\*\ Note: When selects the GPIOB, Only GPIO_PIN_0 and GPIO_PIN_1 are valid
*\*\param mode
*\*\ - GPIO_MODE_INPUT
*\*\ - GPIO_MODE_OUT_PP
*\*\ - GPIO_MODE_OUT_OD
*\*\ - GPIO_MODE_AF_PP
*\*\ - GPIO_MODE_AF_OD
*\*\ - GPIO_MODE_ANALOG
*\*\param position
*\*\ - 0x00 ~ 0x0F 0x00 represents GPIO_PIN_0,
*\*\ 0x01 represents GPIO_PIN_1
*\*\ ...
*\*\ 0x0F represents GPIO_PIN_15
*\*\return none
*/
void GPIO_Mode_Set(GPIO_Module* GPIOx, uint32_t mode, uint32_t position)
{
uint32_t temp_value = 0x00U;
uint32_t temp = 0x00U;
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp_value = GPIOx->PMODE;
temp = (mode & GPIO_SET_PMODE_MASK);
temp_value &= ~(GPIO_PMODE_MASK << (position * MULTIPLIER_FACTOR_2));
temp_value |= (temp << (position * MULTIPLIER_FACTOR_2));
GPIOx->PMODE = temp_value;
/* In case of Output or Alternate function mode selection */
if((mode == GPIO_MODE_OUT_PP) || (mode == GPIO_MODE_OUT_OD) ||
(mode == GPIO_MODE_AF_PP) || (mode == GPIO_MODE_AF_OD))
{
/* Configure the IO Output Type */
temp_value = GPIOx->POTYPE;
temp_value &= ~(GPIO_POTYPE_MASK << position);
temp_value |= (((mode & GPIO_OUTPUT_TYPE_MASK) >> SHIFT_POTYPE) << position);
GPIOx->POTYPE = temp_value;
}
}
/**
*\*\name GPIO_Pull_Set.
*\*\fun Configure pull mode.
*\*\param GPIOx :
*\*\ - GPIOA
*\*\ - GPIOB
*\*\ Note: When selects the GPIOB, Only GPIO_PIN_0 and GPIO_PIN_1 are valid
*\*\param pull
*\*\ - GPIO_NO_PULL
*\*\ - GPIO_PULL_UP
*\*\ - GPIO_PULL_DOWN
*\*\param position
*\*\ - 0x00 ~ 0x0F 0x00 represents GPIO_PIN_0,
*\*\ 0x01 represents GPIO_PIN_1
*\*\ ...
*\*\ 0x0F represents GPIO_PIN_15
*\*\return none
*/
void GPIO_Pull_Set(GPIO_Module* GPIOx, uint32_t pull, uint32_t position)
{
uint32_t temp_value = 0x00U;
/* Configure pull-down mode */
temp_value = GPIOx->PUPD;
temp_value &= ~(GPIO_PUPD_MASK << (position * MULTIPLIER_FACTOR_2));
temp_value |= (pull << (position * MULTIPLIER_FACTOR_2));
GPIOx->PUPD = temp_value;
}
/**
*\*\name GPIO_SlewRate_Set.
*\*\fun GPIO slew rate configuration.
*\*\param GPIOx :
*\*\ - GPIOA
*\*\ - GPIOB
*\*\ Note: When selects the GPIOB, Only GPIO_PIN_0 and GPIO_PIN_1 are valid
*\*\param slew_rate
*\*\ - GPIO_SLEW_RATE_FAST
*\*\ - GPIO_SLEW_RATE_SLOW
*\*\param position
*\*\ - 0x00 ~ 0x0F 0x00 represents GPIO_PIN_0,
*\*\ 0x01 represents GPIO_PIN_1
*\*\ ...
*\*\ 0x0F represents GPIO_PIN_15
*\*\return none
*/
void GPIO_SlewRate_Set(GPIO_Module* GPIOx, uint32_t slew_rate, uint32_t position)
{
uint32_t temp_value = 0x00U;
/* Configure slew rate */
temp_value = GPIOx->SR;
temp_value &= ~(GPIO_SR_MASK << position);
temp_value |= (slew_rate << position);
GPIOx->SR = temp_value;
}
/**
*\*\name GPIO_Driver_Set.
*\*\fun GPIO driver configuration.
*\*\param GPIOx :
*\*\ - GPIOA
*\*\ - GPIOB
*\*\ Note: When selects the GPIOB, Only GPIO_PIN_0 and GPIO_PIN_1 are valid
*\*\param current
*\*\ - GPIO_HIGH_DREIVE
*\*\ - GPIO_LOW_DREIVE
*\*\param position
*\*\ - 0x00 ~ 0x0F 0x00 represents GPIO_PIN_0,
*\*\ 0x01 represents GPIO_PIN_1
*\*\ ...
*\*\ 0x0F represents GPIO_PIN_15
*\*\return none
*/
void GPIO_Driver_Set(GPIO_Module* GPIOx, uint32_t current, uint32_t position)
{
uint32_t temp_value = 0x00U;
temp_value = GPIOx->DS;
temp_value &= ~(GPIO_DS_MASK << position);
temp_value |= (current << position);
GPIOx->DS = temp_value;
}
/**
*\*\name GPIO_Peripheral_Initialization.
*\*\fun Initialize the GPIOx peripheral with the value of the GPIO_InitStruct structure.
*\*\param GPIOx :
*\*\ - GPIOA
*\*\ - GPIOB
*\*\param GPIO_InitStructure :
*\*\ pointer to GPIO_InitType structure.
*\*\return none
*/
void GPIO_Peripheral_Initialize(GPIO_Module* GPIOx, GPIO_InitType* GPIO_InitStructure)
{
uint32_t position = 0x00U;
uint32_t current_pin = 0x00U;
while(((GPIO_InitStructure->Pin) >> position) != 0)
{
/* Get the IO position */
current_pin = (GPIO_InitStructure->Pin) & (IO_POSITION_MASK << position);
if(current_pin)
{
/* Configure GPIO alternate function */
GPIO_Alternate_Set(GPIOx, GPIO_InitStructure->GPIO_Alternate, position);
/* Configure GPIO mode */
GPIO_Mode_Set(GPIOx, GPIO_InitStructure->GPIO_Mode, position);
/* Configure pull-down or pull-up mode */
GPIO_Pull_Set(GPIOx, GPIO_InitStructure->GPIO_Pull, position);
/* Configure slew rate */
GPIO_SlewRate_Set(GPIOx, GPIO_InitStructure->GPIO_Slew_Rate, position);
/* Configuration drive capability */
GPIO_Driver_Set(GPIOx, GPIO_InitStructure->GPIO_Current, position);
}
position++;
}
}
/**
*\*\name GPIO_Struct_Initialization.
*\*\fun Assign default values to each GPIO_InitStruct member.
*\*\param GPIO_InitStructure :
*\*\ pointer to GPIO_InitType structure.
*\*\return none
*/
void GPIO_Structure_Initialize(GPIO_InitType* GPIO_InitStruct)
{
/* Reset GPIO structure member */
GPIO_InitStruct->Pin = GPIO_PIN_ALL;
GPIO_InitStruct->GPIO_Slew_Rate = GPIO_SLEW_RATE_FAST;
GPIO_InitStruct->GPIO_Mode = GPIO_MODE_INPUT;
GPIO_InitStruct->GPIO_Alternate = GPIO_NO_AF;
GPIO_InitStruct->GPIO_Pull = GPIO_NO_PULL;
GPIO_InitStruct->GPIO_Current = GPIO_HIGH_DREIVE;
}
/**
*\*\name GPIO_Input_Pin_Data_Get.
*\*\fun Get the pin status on the specified input port.
*\*\param GPIOx :
*\*\ - GPIOA
*\*\ - GPIOB
*\*\ Note: When selects the GPIOB, Only GPIO_PIN_0 and GPIO_PIN_1 are valid
*\*\param pin :
*\*\ - GPIO_PIN_0
*\*\ - GPIO_PIN_1
*\*\ - GPIO_PIN_2
*\*\ - GPIO_PIN_3
*\*\ - GPIO_PIN_4
*\*\ - GPIO_PIN_5
*\*\ - GPIO_PIN_6
*\*\ - GPIO_PIN_7
*\*\ - GPIO_PIN_8
*\*\ - GPIO_PIN_9
*\*\ - GPIO_PIN_10
*\*\ - GPIO_PIN_11
*\*\ - GPIO_PIN_12
*\*\ - GPIO_PIN_13
*\*\ - GPIO_PIN_14
*\*\ - GPIO_PIN_15
*\*\return the pin state on the input port.
*/
uint8_t GPIO_Input_Pin_Data_Get(GPIO_Module* GPIOx, uint16_t pin)
{
if ((GPIOx->PID & pin) != (uint32_t)PIN_RESET)
{
return (uint8_t)PIN_SET;
}
else
{
return (uint8_t)PIN_RESET;
}
}
/**
*\*\name GPIO_Input_Data_Get.
*\*\fun Get the input data on the designated GPIO port.
*\*\param GPIOx :
*\*\ - GPIOA
*\*\ - GPIOB
*\*\ Note: When selects the GPIOB, Only bit0 and bit1 are valid
*\*\return the data value on the GPIO input port.
*/
uint16_t GPIO_Input_Data_Get(GPIO_Module* GPIOx)
{
return ((uint16_t)GPIOx->PID);
}
/**
*\*\name GPIO_Output_Pin_Data_Get.
*\*\fun Get the pin status on the specified output port.
*\*\param GPIOx :
*\*\ - GPIOA
*\*\ - GPIOB
*\*\ Note: When selects the GPIOB, Only GPIO_PIN_0 and GPIO_PIN_1 are valid
*\*\param pin :
*\*\ - GPIO_PIN_0
*\*\ - GPIO_PIN_1
*\*\ - GPIO_PIN_2
*\*\ - GPIO_PIN_3
*\*\ - GPIO_PIN_4
*\*\ - GPIO_PIN_5
*\*\ - GPIO_PIN_6
*\*\ - GPIO_PIN_7
*\*\ - GPIO_PIN_8
*\*\ - GPIO_PIN_9
*\*\ - GPIO_PIN_10
*\*\ - GPIO_PIN_11
*\*\ - GPIO_PIN_12
*\*\ - GPIO_PIN_13
*\*\ - GPIO_PIN_14
*\*\ - GPIO_PIN_15
*\*\return the pin state on the output port.
*/
uint8_t GPIO_Output_Pin_Data_Get(GPIO_Module* GPIOx, uint16_t pin)
{
if ((GPIOx->POD & pin) != (uint32_t)PIN_RESET)
{
return (uint8_t)PIN_SET;
}
else
{
return (uint8_t)PIN_RESET;
}
}
/**
*\*\name GPIO_Output_Data_Get.
*\*\fun Get the output data on the designated GPIO port.
*\*\param GPIOx :
*\*\ - GPIOA
*\*\ - GPIOB
*\*\ Note: When selects the GPIOB, Only bit0 and bit1 are valid
*\*\return the data value on the GPIO output port.
*/
uint16_t GPIO_Output_Data_Get(GPIO_Module* GPIOx)
{
return ((uint16_t)GPIOx->POD);
}
/**
*\*\name GPIO_Pins_Set.
*\*\fun Sets the selected data port bits.
*\*\param GPIOx :
*\*\ - GPIOA
*\*\ - GPIOB
*\*\ Note: When selects the GPIOB, Only GPIO_PIN_0 and GPIO_PIN_1 are valid
*\*\param pin :
*\*\ - GPIO_PIN_0
*\*\ - GPIO_PIN_1
*\*\ - GPIO_PIN_2
*\*\ - GPIO_PIN_3
*\*\ - GPIO_PIN_4
*\*\ - GPIO_PIN_5
*\*\ - GPIO_PIN_6
*\*\ - GPIO_PIN_7
*\*\ - GPIO_PIN_8
*\*\ - GPIO_PIN_9
*\*\ - GPIO_PIN_10
*\*\ - GPIO_PIN_11
*\*\ - GPIO_PIN_12
*\*\ - GPIO_PIN_13
*\*\ - GPIO_PIN_14
*\*\ - GPIO_PIN_15
*\*\return none
*/
void GPIO_Pins_Set(GPIO_Module* GPIOx, uint16_t pin)
{
GPIOx->PBSC = pin;
}
/**
*\*\name GPIO_Pins_Reset.
*\*\fun Reset the selected data port bits.
*\*\param GPIOx :
*\*\ - GPIOA
*\*\ - GPIOB
*\*\ Note: When selects the GPIOB, Only GPIO_PIN_0 and GPIO_PIN_1 are valid
*\*\param pin :
*\*\ - GPIO_PIN_0
*\*\ - GPIO_PIN_1
*\*\ - GPIO_PIN_2
*\*\ - GPIO_PIN_3
*\*\ - GPIO_PIN_4
*\*\ - GPIO_PIN_5
*\*\ - GPIO_PIN_6
*\*\ - GPIO_PIN_7
*\*\ - GPIO_PIN_8
*\*\ - GPIO_PIN_9
*\*\ - GPIO_PIN_10
*\*\ - GPIO_PIN_11
*\*\ - GPIO_PIN_12
*\*\ - GPIO_PIN_13
*\*\ - GPIO_PIN_14
*\*\ - GPIO_PIN_15
*\*\return none
*/
void GPIO_Pins_Reset(GPIO_Module* GPIOx, uint16_t pin)
{
GPIOx->PBC = pin;
}
/**
*\*\name GPIO_PBSC_Pins_Reset.
*\*\fun Sets the selected data port bits.
*\*\param GPIOx :
*\*\ - GPIOA
*\*\ - GPIOB
*\*\ Note: When selects the GPIOB, Only GPIO_PIN_0 and GPIO_PIN_1 are valid
*\*\param pin :
*\*\ - GPIO_PIN_0
*\*\ - GPIO_PIN_1
*\*\ - GPIO_PIN_2
*\*\ - GPIO_PIN_3
*\*\ - GPIO_PIN_4
*\*\ - GPIO_PIN_5
*\*\ - GPIO_PIN_6
*\*\ - GPIO_PIN_7
*\*\ - GPIO_PIN_8
*\*\ - GPIO_PIN_9
*\*\ - GPIO_PIN_10
*\*\ - GPIO_PIN_11
*\*\ - GPIO_PIN_12
*\*\ - GPIO_PIN_13
*\*\ - GPIO_PIN_14
*\*\ - GPIO_PIN_15
*\*\return none
*/
void GPIO_PBSC_Pins_Reset(GPIO_Module* GPIOx, uint16_t pin)
{
GPIOx->PBSC = ((uint32_t)pin << SHIFT_PBSC_HIGH16);
}
/**
*\*\name GPIO_PBC_Pins_Reset.
*\*\fun Reset the selected data port bits.
*\*\param GPIOx :
*\*\ - GPIOA
*\*\ - GPIOB
*\*\ Note: When selects the GPIOB, Only GPIO_PIN_0 and GPIO_PIN_1 are valid
*\*\param pin :
*\*\ - GPIO_PIN_0
*\*\ - GPIO_PIN_1
*\*\ - GPIO_PIN_2
*\*\ - GPIO_PIN_3
*\*\ - GPIO_PIN_4
*\*\ - GPIO_PIN_5
*\*\ - GPIO_PIN_6
*\*\ - GPIO_PIN_7
*\*\ - GPIO_PIN_8
*\*\ - GPIO_PIN_9
*\*\ - GPIO_PIN_10
*\*\ - GPIO_PIN_11
*\*\ - GPIO_PIN_12
*\*\ - GPIO_PIN_13
*\*\ - GPIO_PIN_14
*\*\ - GPIO_PIN_15
*\*\return none
*/
void GPIO_PBC_Pins_Reset(GPIO_Module* GPIOx, uint16_t pin)
{
GPIOx->PBC = pin;
}
/**
*\*\name GPIO_Write_Data.
*\*\fun Write data on the designated GPIO data port.
*\*\param GPIOx :
*\*\ - GPIOA
*\*\ - GPIOB
*\*\ Note: When selects the GPIOB, Only bit0 and bit1 are valid
*\*\param data_value :
*\*\ the value to be written to the port output data register.
*\*\return none
*/
void GPIO_Write(GPIO_Module* GPIOx, uint16_t data_value)
{
GPIOx->POD = data_value;
}
/**
*\*\name GPIO_Pin_Toggle.
*\*\fun Toggle the specified port pin level.
*\*\param GPIOx :
*\*\ - GPIOA
*\*\ - GPIOB
*\*\ Note: When selects the GPIOB, Only GPIO_PIN_0 and GPIO_PIN_1 are valid
*\*\param pin :
*\*\ - GPIO_PIN_0
*\*\ - GPIO_PIN_1
*\*\ - GPIO_PIN_2
*\*\ - GPIO_PIN_3
*\*\ - GPIO_PIN_4
*\*\ - GPIO_PIN_5
*\*\ - GPIO_PIN_6
*\*\ - GPIO_PIN_7
*\*\ - GPIO_PIN_8
*\*\ - GPIO_PIN_9
*\*\ - GPIO_PIN_10
*\*\ - GPIO_PIN_11
*\*\ - GPIO_PIN_12
*\*\ - GPIO_PIN_13
*\*\ - GPIO_PIN_14
*\*\ - GPIO_PIN_15
*\*\return none
*/
void GPIO_Pin_Toggle(GPIO_Module* GPIOx, uint16_t pin)
{
GPIOx->POD ^= pin;
}
/**
*\*\name GPIO_Pin_Lock_Set.
*\*\fun GPIO port lock register configuration.
*\*\param GPIOx :
*\*\ - GPIOA
*\*\ - GPIOB
*\*\ Note: When selects the GPIOB, Only GPIO_PIN_0 and GPIO_PIN_1 are valid
*\*\param pin :
*\*\ - GPIO_PIN_0
*\*\ - GPIO_PIN_1
*\*\ - GPIO_PIN_2
*\*\ - GPIO_PIN_3
*\*\ - GPIO_PIN_4
*\*\ - GPIO_PIN_5
*\*\ - GPIO_PIN_6
*\*\ - GPIO_PIN_7
*\*\ - GPIO_PIN_8
*\*\ - GPIO_PIN_9
*\*\ - GPIO_PIN_10
*\*\ - GPIO_PIN_11
*\*\ - GPIO_PIN_12
*\*\ - GPIO_PIN_13
*\*\ - GPIO_PIN_14
*\*\ - GPIO_PIN_15
*\*\return none
*/
void GPIO_Pin_Lock_Set(GPIO_Module* GPIOx, uint16_t pin)
{
uint32_t temp_value = 0x00U;
temp_value = (GPIO_PLOCKK_MASK | pin);
/* PLOCKK and PLOCKx write 1 */
GPIOx->PLOCK = temp_value;
/* PLOCKK write 0 */
GPIOx->PLOCK = pin;
/* PLOCKK and PLOCKx write 1 */
GPIOx->PLOCK = temp_value;
/* PLOCKK read 0 */
temp_value = GPIOx->PLOCK;
/* PLOCKK read 1 */
temp_value = GPIOx->PLOCK;
}
/**
*\*\name GPIO_Pin_Remap_Set.
*\*\fun Pin remapping configuration.
*\*\param port_source :
*\*\ - GPIOA_PORT_SOURCE
*\*\ - GPIOB_PORT_SOURCE
*\*\ Note: When selects the GPIOB, Only GPIO_PIN_SOURCE0 and GPIO_PIN_SOURCE1 are valid
*\*\param pin_source :
*\*\ - GPIO_PIN_SOURCE0
*\*\ - GPIO_PIN_SOURCE1
*\*\ - GPIO_PIN_SOURCE2
*\*\ - GPIO_PIN_SOURCE3
*\*\ - GPIO_PIN_SOURCE4
*\*\ - GPIO_PIN_SOURCE5
*\*\ - GPIO_PIN_SOURCE6
*\*\ - GPIO_PIN_SOURCE7
*\*\ - GPIO_PIN_SOURCE8
*\*\ - GPIO_PIN_SOURCE9
*\*\ - GPIO_PIN_SOURCE10
*\*\ - GPIO_PIN_SOURCE11
*\*\ - GPIO_PIN_SOURCE12
*\*\ - GPIO_PIN_SOURCE13
*\*\ - GPIO_PIN_SOURCE14
*\*\ - GPIO_PIN_SOURCE15
*\*\param alternate_function :
*\*\ - GPIO_AF0_SWDIO SWDIO Alternate Function mapping
*\*\ - GPIO_AF0_SWCLK SWCLK Alternate Function mapping
*\*\ - GPIO_AF0_TIM1 TIM1 Alternate Function mapping
*\*\ - GPIO_AF0_TIM3 TIM3 Alternate Function mapping
*\*\ - GPIO_AF0_SPI SPI Alternate Function mapping
*\*\
*\*\ - GPIO_AF1_UART2 UART2 Alternate Function mapping
*\*\ - GPIO_AF1_TIM3 TIM3 Alternate Function mapping
*\*\
*\*\ - GPIO_AF2_UART1 UART1 Alternate Function mapping
*\*\ - GPIO_AF2_TIM1 TIM1 Alternate Function mapping
*\*\ - GPIO_AF2_TIM3 TIM3 Alternate Function mapping
*\*\
*\*\ - GPIO_AF3_TIM1 TIM1 Alternate Function mapping
*\*\ - GPIO_AF3_COMP COMP Alternate Function mapping
*\*\ - GPIO_AF3_EVENTOUT EVENTOUT Alternate Function mapping
*\*\
*\*\ - GPIO_AF4_TIM1 TIM1 Alternate Function mapping
*\*\
*\*\ - GPIO_AF5_UART1 UART1 Alternate Function mapping
*\*\ - GPIO_AF5_TIM1 TIM1 Alternate Function mapping
*\*\ - GPIO_AF5_SPI SPI Alternate Function mapping
*\*\
*\*\ - GPIO_AF6_SPI SPI Alternate Function mapping
*\*\ - GPIO_AF6_I2C I2C Alternate Function mapping
*\*\ - GPIO_AF6_TIM3 TIM3 Alternate Function mapping
*\*\ - GPIO_AF6_UART2 UART2 Alternate Function mapping
*\*\ - GPIO_AF6_MCO MCO Alternate Function mapping
*\*\
*\*\ - GPIO_AF7_BEEPER BEEPER Alternate Function mapping
*\*\return none
*/
void GPIO_Pin_Remap_Set(uint8_t port_source, uint8_t pin_source, uint32_t alternate_function)
{
uint32_t position = 0x00, temp_value = 0x00;
GPIO_Module *GPIOx;
/* Get Peripheral index */
GPIOx = GPIO_GET_PERIPH(port_source);
if(pin_source & (uint8_t)AF_SELECTION_MASK)
{
position = (uint32_t)(pin_source & (uint8_t)AF_WRITE_POSITION_MASK);
/* Read GPIO_AFH register */
temp_value = GPIOx->AFH;
/* Reset corresponding bits */
temp_value &= ~(GPIO_AF_MASK << (position * MULTIPLIER_FACTOR_4));
/* Set corresponding bits */
temp_value |= (alternate_function << (position * MULTIPLIER_FACTOR_4));
/* Write to the GPIO_AFH register */
GPIOx->AFH = temp_value;
}
else
{
position = (uint32_t)(pin_source & (uint8_t)AF_WRITE_POSITION_MASK);
/* Read GPIO_AFL register */
temp_value = GPIOx->AFL;
/* Reset corresponding bits */
temp_value &= ~(GPIO_AF_MASK << (position * MULTIPLIER_FACTOR_4));
/* Set corresponding bits */
temp_value |= (alternate_function << (position * MULTIPLIER_FACTOR_4));
/* Write to the GPIO_AFL register */
GPIOx->AFL = temp_value;
}
}
/**
*\*\name AFIO_ADC_External_Trigger_Set
*\*\fun Selects the GPIO pin used as EXTI Line.
*\*\param line_source:
*\*\ - AFIO_ADC_TRIG_PA0
*\*\ - AFIO_ADC_TRIG_PA1
*\*\ - AFIO_ADC_TRIG_PA2
*\*\ - AFIO_ADC_TRIG_PA3
*\*\ - AFIO_ADC_TRIG_PA4
*\*\ - AFIO_ADC_TRIG_PA5
*\*\ - AFIO_ADC_TRIG_PA6
*\*\ - AFIO_ADC_TRIG_PA7
*\*\ - AFIO_ADC_TRIG_PA8
*\*\ - AFIO_ADC_TRIG_PA9
*\*\ - AFIO_ADC_TRIG_PA10
*\*\ - AFIO_ADC_TRIG_PA11
*\*\ - AFIO_ADC_TRIG_PA12
*\*\ - AFIO_ADC_TRIG_PA13
*\*\ - AFIO_ADC_TRIG_PA14
*\*\ - AFIO_ADC_TRIG_PA15
*\*\ - AFIO_ADC_TRIG_PB0
*\*\ - AFIO_ADC_TRIG_PB1
*\*\ Note: Each EXTI line corresponds to a separate pin in this series.
*\*\return none
*/
void AFIO_ADC_External_Trigger_Set(uint8_t ADC_trigger)
{
uint32_t temp_value = 0x00;
temp_value = AFIO->CFG;
temp_value &= ~AFIO_CFG_MASK;
temp_value |= ADC_trigger;
AFIO->CFG = temp_value;
}
/**
*\*\name AFIO_SPI_NSS_Mode_Set.
*\*\fun Selects NSS mode of SPI when idle.
*\*\param SPI_nss_mode :
*\*\ specifies the SPI_NSS mode to be configured.
*\*\ - AFIO_SPI_NSS_HIGH_IMPEDANCE
*\*\ - AFIO_SPI_NSS_High_LEVEL
*\*\return none
*/
void AFIO_SPI_NSS_Mode_Set(uint32_t SPI_NSS_mode)
{
uint32_t temp_value = 0x00U;
temp_value = (AFIO->CFG & (~AFIO_CFG_SPI_NSS));
if(SPI_NSS_mode != AFIO_SPI_NSS_HIGH_IMPEDANCE)
{
temp_value |= AFIO_SPI_NSS;
}
else
{
temp_value &= ~AFIO_SPI_NSS;
}
AFIO->CFG = temp_value;
}
/**
*\*\name AFIO_TIM3CH2_Remap.
*\*\fun Controls the TIM3_CH2 internal mapping.
*\*\param TIM3CH2_remap :
*\*\ specifies the TIM3_CH2 internal mapping.
*\*\ - TIM3CH2_TO_PORT
*\*\ - TIM3CH2_TO_LSI
*\*\return none
*/
void AFIO_TIM3CH2_Remap(uint32_t TIM3CH2_remap)
{
uint32_t temp_value = 0x00U;
temp_value = (AFIO->CFG & (~AFIO_CFG_TIM3CH2_MAP));
if(TIM3CH2_remap != TIM3CH2_TO_PORT)
{
temp_value |= AFIO_TIM3CH2_MAP;
}
else
{
temp_value &= ~AFIO_TIM3CH2_MAP;
}
AFIO->CFG = temp_value;
}

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/**
* Copyright (c) 2022, Nations Technologies Inc.
*
* All rights reserved.
*
* This software is the exclusive property of Nations Technologies Inc. (Hereinafter
* referred to as NATIONS). This software, and the product of NATIONS described herein
* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties
* of the People's Republic of China and other applicable jurisdictions worldwide.
*
* NATIONS does not grant any license under its patents, copyrights, trademarks, or other
* intellectual property rights. Names and brands of third party may be mentioned or referred
* thereto (if any) for identification purposes only.
*
* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and
* improvements to this software at any time without notice. Please contact NATIONS and obtain
* the latest version of this software before placing orders.
* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes
* no responsibility for the accuracy and reliability of this software.
*
* It is the responsibility of the user of this software to properly design, program, and test
* the functionality and safety of any application made of this information and any resulting product.
* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or
* consequential damages arising in any way out of the use of this software or the Product.
*
* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any
* malfunction or failure of which may cause loss of human life, bodily injury or severe property
* damage. Such applications are deemed, "Insecure Usage".
*
* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS
* harmless from and against all claims, costs, damages, and other liabilities, arising from or related
* to any customer's Insecure Usage.
* Any express or implied warranty with regard to this software or the Product, including,but not
* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement
* are disclaimed to the fullest extent permitted by law.
* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe
* or otherwise distribute this software for any purposes, in whole or in part.
*
* NATIONS products and technologies shall not be used for or incorporated into any products or systems
* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations.
* User shall comply with any applicable export control laws and regulations promulgated and administered by
* the governments of any countries asserting jurisdiction over the parties or transactions.
**/
/**
*\*\file n32g003_iwdg.c
*\*\author Nations
*\*\version v1.0.0
*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
**/
#include "n32g003_iwdg.h"
/**
*\*\name IWDG_Write_Protection_Disable.
*\*\fun Disable write protection to IWDG_PREDIV and IWDG_RELV registers.
*\*\param none
*\*\return none
**/
void IWDG_Write_Protection_Disable(void)
{
IWDG->KEY = IWDG_WRITE_CONFIG_ENABLE;
}
/**
*\*\name IWDG_Write_Protection_Enable.
*\*\fun Enable write protection to IWDG_PREDIV and IWDG_RELV registers.
*\*\param none
*\*\return none
**/
void IWDG_Write_Protection_Enable(void)
{
IWDG->KEY = IWDG_WRITE_CONFIG_DISABLE;
}
/**
*\*\name IWDG_Prescaler_Division_Set.
*\*\fun IWDG_Prescaler specifies the IWDG prescaler value.
*\*\param IWDG_prescaler :
*\*\ - IWDG_CONFIG_PRESCALER_DIV4
*\*\ - IWDG_CONFIG_PRESCALER_DIV8
*\*\ - IWDG_CONFIG_PRESCALER_DIV16
*\*\ - IWDG_CONFIG_PRESCALER_DIV32
*\*\ - IWDG_CONFIG_PRESCALER_DIV64
*\*\ - IWDG_CONFIG_PRESCALER_DIV128
*\*\ - IWDG_CONFIG_PRESCALER_DIV256
*\*\return none
**/
void IWDG_Prescaler_Division_Set(IWDG_CONFIG_PRESCALER IWDG_prescaler)
{
IWDG->PREDIV = IWDG_prescaler;
}
/**
*\*\name IWDG_Counter_Reload.
*\*\fun Sets IWDG reload value.
*\*\param reload_value :
*\*\ -0x000 ~ 0xFFF
*\*\return none
**/
void IWDG_Counter_Reload(uint16_t reload_value)
{
IWDG->RELV= reload_value;
}
/**
*\*\name IWDG_Key_Reload.
*\*\fun Reload IWDG counter with value defined in IWDG_RELV register.
*\*\return none
**/
void IWDG_Key_Reload(void)
{
IWDG->KEY = KEY_RELOAD_COUNTER;
}
/**
*\*\name IWDG_Enable.
*\*\fun Start watch dog counter.
*\*\return none
**/
void IWDG_Enable(void)
{
IWDG->KEY = KEY_ENABLE_COUNTER;
}
/**
*\*\name IWDG_Freeze_Enable.
*\*\fun Freeze and stop IWDG while IWDG is running.
*\*\return none
**/
ErrorStatus IWDG_Freeze_Enable(void)
{
IWDG->FREEZE = IWDG_FREEZE;
if((IWDG->FREEZE & IWDG_FREEZE_FLAG) != (uint32_t)RESET)
{
return SUCCESS;
}
else
{
return ERROR;
}
}
/**
*\*\name IWDG_Restore_From_Freeze.
*\*\fun Restore from run time feeze.
*\*\return none
**/
ErrorStatus IWDG_Restore_From_Freeze(void)
{
IWDG->FREEZE = IWDG_UNFREEZE;
if((IWDG->FREEZE & IWDG_FREEZE_FLAG) == (uint32_t)RESET)
{
return SUCCESS;
}
else
{
return ERROR;
}
}
/**
*\*\name IWDG_Status_Get.
*\*\fun Checks whether the specified IWDG flag is set or not.
*\*\param IWDG_flag :
*\*\ - IWDG_PVU_FLAG
*\*\ - IWDG_CRVU_FLAG
*\*\return FlagStatus :
*\*\ - RESET
*\*\ - SET
**/
FlagStatus IWDG_Status_Get(IWDG_STATUS_FLAG IWDG_flag)
{
if((IWDG->STS & IWDG_flag) != (uint32_t)RESET)
{
return SET;
}
else
{
return RESET;
}
}

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/**
* Copyright (c) 2022, Nations Technologies Inc.
*
* All rights reserved.
*
* This software is the exclusive property of Nations Technologies Inc. (Hereinafter
* referred to as NATIONS). This software, and the product of NATIONS described herein
* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties
* of the People's Republic of China and other applicable jurisdictions worldwide.
*
* NATIONS does not grant any license under its patents, copyrights, trademarks, or other
* intellectual property rights. Names and brands of third party may be mentioned or referred
* thereto (if any) for identification purposes only.
*
* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and
* improvements to this software at any time without notice. Please contact NATIONS and obtain
* the latest version of this software before placing orders.
* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes
* no responsibility for the accuracy and reliability of this software.
*
* It is the responsibility of the user of this software to properly design, program, and test
* the functionality and safety of any application made of this information and any resulting product.
* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or
* consequential damages arising in any way out of the use of this software or the Product.
*
* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any
* malfunction or failure of which may cause loss of human life, bodily injury or severe property
* damage. Such applications are deemed, "Insecure Usage".
*
* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS
* harmless from and against all claims, costs, damages, and other liabilities, arising from or related
* to any customer's Insecure Usage.
* Any express or implied warranty with regard to this software or the Product, including,but not
* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement
* are disclaimed to the fullest extent permitted by law.
* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe
* or otherwise distribute this software for any purposes, in whole or in part.
*
* NATIONS products and technologies shall not be used for or incorporated into any products or systems
* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations.
* User shall comply with any applicable export control laws and regulations promulgated and administered by
* the governments of any countries asserting jurisdiction over the parties or transactions.
**/
/**
*\*\file n32g003_pwr.c
*\*\author Nations
*\*\version v1.0.0
*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
*/
#include "n32g003_pwr.h"
#include "n32g003_rcc.h"
/** PWR Private Defines **/
/** PWR Driving Functions Declaration **/
/**
*\*\name PWR_Reset.
*\*\fun Deinitializes the PWR peripheral registers to their default reset values.
*\*\param none
*\*\return none
**/
void PWR_Reset(void)
{
RCC_Peripheral_Reset(RCC_RST_PWRRST);
}
/**
*\*\name PWR_PVD_Enable.
*\*\fun Enables the Power Voltage Detector(PVD).
*\*\param none
*\*\return none
**/
void PWR_PVD_Enable(void)
{
PWR->CTRL |= PWR_PVD_ENABLE;
}
/**
*\*\name PWR_PVD_Disable.
*\*\fun Disables the Power Voltage Detector(PVD).
*\*\param none
*\*\return none
**/
void PWR_PVD_Disable(void)
{
PWR->CTRL &= (~PWR_PVD_ENABLE);
}
/**
*\*\name PWR_PVD_Interrupt_Enable.
*\*\fun Enables the Power Voltage Detector Interrupt.
*\*\param none
*\*\return none
**/
void PWR_PVD_Interrupt_Enable(void)
{
PWR->CTRL |= PWR_PVD_INT_ENABLE;
}
/**
*\*\name PWR_PVD_Interrupt_Disable.
*\*\fun Disables the Power Voltage Detector Interrupt.
*\*\param none
*\*\return none
**/
void PWR_PVD_Interrupt_Disable(void)
{
PWR->CTRL &= (~PWR_PVD_INT_ENABLE);
}
/**
*\*\name PWR_PVD_Filter_Enable.
*\*\fun Enables the Power Voltage Detector Filter.
*\*\param none
*\*\return none
**/
void PWR_PVD_Filter_Enable(void)
{
PWR->CTRL |= PWR_PVD_FIL_ENABLE;
}
/**
*\*\name PWR_PVD_Filter_Disable.
*\*\fun Disables the Power Voltage Detector Filter.
*\*\param none
*\*\return none
**/
void PWR_PVD_Filter_Disable(void)
{
PWR->CTRL &= (~PWR_PVD_FIL_ENABLE);
}
/**
*\*\name PWR_PVD_Level_Config.
*\*\fun Configures the voltage threshold detected by the Power Voltage Detector(PVD).
*\*\param level :
*\*\ - PWR_PVD_LEVEL_1V8
*\*\ - PWR_PVD_LEVEL_2V0
*\*\ - PWR_PVD_LEVEL_2V2
*\*\ - PWR_PVD_LEVEL_2V4
*\*\ - PWR_PVD_LEVEL_2V6
*\*\ - PWR_PVD_LEVEL_2V8
*\*\ - PWR_PVD_LEVEL_3V0
*\*\ - PWR_PVD_LEVEL_3V2
*\*\ - PWR_PVD_LEVEL_3V4
*\*\ - PWR_PVD_LEVEL_3V6
*\*\ - PWR_PVD_LEVEL_3V8
*\*\ - PWR_PVD_LEVEL_4V0
*\*\ - PWR_PVD_LEVEL_4V2
*\*\ - PWR_PVD_LEVEL_4V4
*\*\ - PWR_PVD_LEVEL_4V6
*\*\ - PWR_PVD_LEVEL_4V8
*\*\return none
**/
void PWR_PVD_Level_Config(uint32_t level)
{
uint32_t temp_value = 0;
temp_value = PWR->CTRL;
/* Clear PLS[8:5] bits bit */
temp_value &= PWR_CTRL_PLS_MASK;
/* Set PLS[8:5] bits according to level value */
temp_value |= level;
/* Store the new value */
PWR->CTRL = temp_value;
}
/**
*\*\name PWR_LVR_Enable.
*\*\fun Enables the Low Voltage Detector(LVR).
*\*\param none
*\*\return none
**/
void PWR_LVR_Enable(void)
{
PWR->CTRL2 |= PWR_LVR_ENABLE;
}
/**
*\*\name PWR_LVR_Disable.
*\*\fun Disables the Low Voltage Detector(LVR).
*\*\param none
*\*\return none
**/
void PWR_LVR_Disable(void)
{
PWR->CTRL2 &= (~PWR_LVR_ENABLE);
}
/**
*\*\name PWR_LVR_Reset_Enable.
*\*\fun Enables the Low Voltage Detector reset.
*\*\param none
*\*\return none
**/
void PWR_LVR_Reset_Enable(void)
{
PWR->CTRL2 |= PWR_LVR_RST_ENABLE;
}
/**
*\*\name PWR_LVR_Reset_Disable.
*\*\fun Disables the Low Voltage Detector reset.
*\*\param none
*\*\return none
**/
void PWR_LVR_Reset_Disable(void)
{
PWR->CTRL2 &= (~PWR_LVR_RST_ENABLE);
}
/**
*\*\name PWR_LVR_Filter_Enable.
*\*\fun Enables the Low Voltage Detector Filter.
*\*\param none
*\*\return none
**/
void PWR_LVR_Filter_Enable(void)
{
PWR->CTRL2 |= PWR_LVR_FIL_ENABLE;
}
/**
*\*\name PWR_LVR_Filter_Disable.
*\*\fun Disables the Low Voltage Detector Filter.
*\*\param none
*\*\return none
**/
void PWR_LVR_Filter_Disable(void)
{
PWR->CTRL2 &= (~PWR_LVR_FIL_ENABLE);
}
/**
*\*\name PWR_LVR_Level_Config.
*\*\fun Configures the voltage threshold detected by the Low Voltage Detector(LVR).
*\*\param level :
*\*\ - PWR_LVR_LEVEL_1V8
*\*\ - PWR_LVR_LEVEL_2V0
*\*\ - PWR_LVR_LEVEL_2V2
*\*\ - PWR_LVR_LEVEL_2V4
*\*\ - PWR_LVR_LEVEL_2V6
*\*\ - PWR_LVR_LEVEL_2V8
*\*\ - PWR_LVR_LEVEL_3V0
*\*\ - PWR_LVR_LEVEL_3V2
*\*\ - PWR_LVR_LEVEL_3V4
*\*\ - PWR_LVR_LEVEL_3V6
*\*\ - PWR_LVR_LEVEL_3V8
*\*\ - PWR_LVR_LEVEL_4V0
*\*\ - PWR_LVR_LEVEL_4V2
*\*\ - PWR_LVR_LEVEL_4V4
*\*\ - PWR_LVR_LEVEL_4V6
*\*\ - PWR_LVR_LEVEL_4V8
*\*\return none
**/
void PWR_LVR_Level_Config(uint32_t level)
{
uint32_t temp_value = 0;
temp_value = PWR->CTRL2;
/* Clear LVRS[14:11] bits*/
temp_value &= PWR_CTRL2_LVRLS_MASK;
/* Set LVRS[14:11] bits according to level value */
temp_value |= level;
/* Store the new value */
PWR->CTRL2 = temp_value;
}
/**
*\*\name PWR_Wakeup_Pin_Enable.
*\*\fun Enables the Wakeup Pin functionality.
*\*\param pin :
*\*\ - WAKEUP_PIN1 PA1
*\*\ - WAKEUP_PIN2 PA2
*\*\param polarity :
*\*\ - PWR_PIN_RISING
*\*\ - PWR_PIN_FALLING
*\*\return none
**/
void PWR_Wakeup_Pin_Enable(WAKEUP_PINX pin, uint32_t polarity)
{
uint32_t temp_value = 0;
temp_value = PWR->CTRLSTS;
/* Clear WKUPPOL bit*/
temp_value &= (PWR_CTRLSTS_WKUPPOL_MASK);
/* Clear WKUP1EN or WKUP0EN bit*/
temp_value &= (~(uint32_t)pin);
/* Set wakeup polarity value */
temp_value |= (polarity << PWR_BIT_SHIFT_10);
/* Set wakeup value */
temp_value |= pin;
/* Store the new value */
PWR->CTRLSTS = temp_value;
}
/**
*\*\name PWR_Wakeup_Pin_Disable.
*\*\fun Disables the WakeUp Pin functionality.
*\*\param pin :
*\*\ - WAKEUP_PIN1 PA1
*\*\ - WAKEUP_PIN2 PA2
*\*\return none
**/
void PWR_Wakeup_Pin_Disable(WAKEUP_PINX pin)
{
uint32_t temp_value = 0;
temp_value = PWR->CTRLSTS;
/* Set wakeup value */
temp_value &= (~(uint32_t)pin);
/* Store the new value */
PWR->CTRLSTS = temp_value;
}
/**
*\*\name PWR_STOP_Mode_Enter.
*\*\fun Enters STOP mode.
*\*\param enter_mode :
*\*\ - PWR_STOP_ENTRY_WFI (enter STOP mode with WFI instruction)
*\*\ - PWR_STOP_ENTRY_WFE (enter STOP mode with WFE instruction)
*\*\return none
**/
void PWR_STOP_Mode_Enter(uint8_t enter_mode)
{
uint32_t temp_value = 0;
temp_value = PWR->CTRL;
/* Clear PDSTP bits */
temp_value &= PWR_CTRL_PDSTP_MASK;
/* Store the new value */
PWR->CTRL = temp_value;
/* Set SLEEPDEEP bit of Cortex System Control Register */
SCB->SCR |= SCB_SCR_SLEEPDEEP;
/* Select STOP mode entry */
if (enter_mode == PWR_STOP_ENTRY_WFI)
{
/* Request Wait For Interrupt */
__WFI();
}
else
{
/* Request Wait For Event */
__SEV();
__WFE();
__WFE();
}
/* Reset SLEEPDEEP bit of Cortex System Control Register */
SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP);
}
/**
*\*\name PWR_PD_Mode_Enter.
*\*\fun Enters PD mode.
*\*\param enter_mode :
*\*\ - PWR_PD_ENTRY_WFI (enter PD mode with WFI instruction)
*\*\ - PWR_PD_ENTRY_WFE (enter PD mode with WFE instruction)
*\*\return none
**/
void PWR_PD_Mode_Enter(uint8_t enter_mode)
{
/* Clear Wake-up flag */
PWR->CTRL |= PWR_CLEAR_WKUPF;
/* Clear PDS bits */
PWR->CTRL &= PWR_CTRL_PDSTP_MASK;
/* Select PD mode */
PWR->CTRL |= PWR_PD_MODE;
/* Set SLEEPDEEP bit of Cortex System Control Register */
SCB->SCR |= SCB_SCR_SLEEPDEEP;
/* This option is used to ensure that store operations are completed */
#if defined(__CC_ARM)
__force_stores();
#endif
/* Select PD mode entry */
if (enter_mode == PWR_PD_ENTRY_WFI)
{
/* Request Wait For Interrupt */
__WFI();
}
else
{
/* Request Wait For Event */
__SEV();
__WFE();
__WFE();
}
}
/**
*\*\name PWR_HSI_40M_Trim_Select.
*\*\fun PWR control selects the HSI frequency as 40M.
*\*\param none
*\*\return none
**/
void PWR_HSI_40M_Trim_Select(void)
{
/* Enable the HSI is controlled by the PWR */
PWR->CTRL3 |= PWR_CONTROL_HSI;
/* Select the HSI frequency as 40M */
PWR->CTRL3 |= PWR_HSI_TRIM_40M;
}
/**
*\*\name PWR_PDR_Trigger_Level_Config.
*\*\fun VDDD PDR trigger level configuration in STOP mode.
*\*\param level :
*\*\ - PWR_PDR_LEVEL_0V8
*\*\ - PWR_PDR_LEVEL_1V0
*\*\ - PWR_PDR_LEVEL_1V2
*\*\return none
**/
void PWR_PDR_Trigger_Level_Config(uint32_t level)
{
uint32_t temp_value = 0;
/* Enable PDR select signal is controlled by the PWR */
PWR->CTRL3 |= PWR_CONTROL_PDR_SEL;
temp_value = PWR->CTRL;
/* Clear PDRS[10:9] bits*/
temp_value &= PWR_CTRL_PDRS_MASK;
/* Set PDRS[10:9] bits according to level value */
temp_value |= level;
/* Store the new value */
PWR->CTRL = temp_value;
}
/**
*\*\name PWR_VDDD_Output_Config.
*\*\fun After the chip enters STOP mode, configure the output voltage of VDDD.
*\*\param voltage_output :
*\*\ - PWR_VDDD_OUTPUT_1V5
*\*\ - PWR_VDDD_OUTPUT_1V0
*\*\ - PWR_VDDD_OUTPUT_1V2
*\*\return none
*\*\note When configuring PWR_VDDD_OUTPUT_1V0 and PWR_VDDD_OUTPUT_1V2, you must
*\*\ first call the PWR_PDR_Trigger_Level_Config() function with the
*\*\ parameter PWR_PDR_LEVEL_0V8.
**/
void PWR_VDDD_Output_Config(uint32_t voltage_output)
{
uint32_t temp_value = 0;
/* Enable VDDD output voltage select */
PWR->CTRL6 |= PWR_VDDD_OUTPUT_SEL_EN;
temp_value = PWR->CTRL5;
/* Clear STPMRSEL[3:2] bits*/
temp_value &= PWR_CTRL5_STPMRSEL_MASK;
/* Set STPMRSEL[3:2] bits according to level value */
temp_value |= voltage_output;
/* Store the new value */
PWR->CTRL5 = temp_value;
}
/**
*\*\name PWR_CTRL2_write_Protection_Enable.
*\*\fun Enable the PWR_CTRL2 registers write protection.
*\*\param none
*\*\return none
**/
void PWR_CTRL2_write_Protection_Enable(void)
{
/* Enable the write protection for PWR_CTRL2 registers */
PWR->CTRL2 = PWR_CTRL2_KEYS;
}
/**
*\*\name PWR_CTRL4_write_Protection_Enable.
*\*\fun Enable the PWR_CTRL4 registers write protection.
*\*\param none
*\*\return none
**/
void PWR_CTRL4_write_Protection_Enable(void)
{
/* Enable the write protection for PWR_CTRL4 registers */
PWR->CTRL4 = PWR_CTRL4_KEYS;
}
/**
*\*\name PWR_Flag_Status_Get.
*\*\fun Checks whether the specified PWR flag is set or not.
*\*\param flag :
*\*\ - PWR_WKUP_FLAG
*\*\ - PWR_DBGPD_FLAG
*\*\ - PWR_PVD_OUTPUT_FLAG
*\*\ - PWR_LVR_OUTPUT_FLAG
*\*\return SET or RESET.
**/
FlagStatus PWR_Flag_Status_Get(uint32_t flag)
{
if (flag == PWR_LVR_OUTPUT_FLAG)
{
/* Check the status of the PWR flag */
if ((PWR->CTRL2 & flag) == (uint32_t)RESET)
{
/* PWR Flag is reset */
return RESET;
}
else
{
/* PWR Flag is set */
return SET;
}
}
else
{
/* Check the status of the PWR flag */
if ((PWR->CTRLSTS & flag) == (uint32_t)RESET)
{
/* PWR Flag is reset */
return RESET;
}
else
{
/* PWR Flag is set */
return SET;
}
}
}
/**
*\*\name PWR_Flag_Status_Clear.
*\*\fun Clears the PWR's pending flags.
*\*\param flag :
*\*\ - PWR_WKUP_FLAG
*\*\ - PWR_DBGPD_FLAG
*\*\return none
**/
void PWR_Flag_Status_Clear(uint32_t flag)
{
if(flag == PWR_DBGPD_FLAG)
{
PWR->CTRL |= (flag << PWR_BIT_SHIFT_2);
}
else
{
PWR->CTRL |= (flag << PWR_BIT_SHIFT_2);
}
}
/**
*\*\name DBG_Peripheral_ON.
*\*\fun Configures the specified peripheral run when the MCU under Debug mode.
*\*\param DBG_Periph :
*\*\ - PWR_DBG_STOP Keep debugger connection during STOP mode
*\*\ - PWR_DBG_PD Keep debugger connection during PD mode
*\*\ - PWR_DBG_IWDG IWDG stopped when Core is halted
*\*\ - PWR_DBG_TIM1 TIM1 counter stopped when Core is halted
*\*\ - PWR_DBG_TIM3 TIM3 counter stopped when Core is halted
*\*\ - PWR_DBG_TIM6 TIM6 counter stopped when Core is halted
*\*\return none
**/
void DBG_Peripheral_ON(uint32_t DBG_Periph)
{
PWR->DBG_CTRL |= DBG_Periph;
}
/**
*\*\name DBG_Peripheral_OFF.
*\*\fun Configures the specified peripheral run or stop when the MCU under Debug mode.
*\*\param DBG_Periph :
*\*\ - PWR_DBG_STOP Keep debugger connection during STOP mode
*\*\ - PWR_DBG_PD Keep debugger connection during PD mode
*\*\ - PWR_DBG_IWDG IWDG stopped when Core is halted
*\*\ - PWR_DBG_TIM1 TIM1 counter stopped when Core is halted
*\*\ - PWR_DBG_TIM3 TIM3 counter stopped when Core is halted
*\*\ - PWR_DBG_TIM6 TIM6 counter stopped when Core is halted
*\*\return none
**/
void DBG_Peripheral_OFF(uint32_t DBG_Periph)
{
PWR->DBG_CTRL &= (~DBG_Periph);
}

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/**
* Copyright (c) 2022, Nations Technologies Inc.
*
* All rights reserved.
*
* This software is the exclusive property of Nations Technologies Inc. (Hereinafter
* referred to as NATIONS). This software, and the product of NATIONS described herein
* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties
* of the People's Republic of China and other applicable jurisdictions worldwide.
*
* NATIONS does not grant any license under its patents, copyrights, trademarks, or other
* intellectual property rights. Names and brands of third party may be mentioned or referred
* thereto (if any) for identification purposes only.
*
* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and
* improvements to this software at any time without notice. Please contact NATIONS and obtain
* the latest version of this software before placing orders.
* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes
* no responsibility for the accuracy and reliability of this software.
*
* It is the responsibility of the user of this software to properly design, program, and test
* the functionality and safety of any application made of this information and any resulting product.
* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or
* consequential damages arising in any way out of the use of this software or the Product.
*
* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any
* malfunction or failure of which may cause loss of human life, bodily injury or severe property
* damage. Such applications are deemed, "Insecure Usage".
*
* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS
* harmless from and against all claims, costs, damages, and other liabilities, arising from or related
* to any customer's Insecure Usage.
* Any express or implied warranty with regard to this software or the Product, including,but not
* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement
* are disclaimed to the fullest extent permitted by law.
* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe
* or otherwise distribute this software for any purposes, in whole or in part.
*
* NATIONS products and technologies shall not be used for or incorporated into any products or systems
* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations.
* User shall comply with any applicable export control laws and regulations promulgated and administered by
* the governments of any countries asserting jurisdiction over the parties or transactions.
**/
/**
*\*\file n32g003_rcc.c
*\*\author Nations
*\*\version v1.0.0
*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
*/
#include "n32g003_rcc.h"
/** RCC_Private_Defines **/
static __I uint8_t AHBPresTable[16] = {1, 1, 1, 1, 1, 1, 1, 1, 2, 4, 8, 12, 16, 24, 24,24};
static __I uint8_t APBPresTable[8] = {1, 1, 1, 1, 2, 4, 8, 16};
static __I uint8_t ADCCLKPresTable[16] = {1, 2, 3, 4, 6, 8, 10, 12, 24, 32, 32, 32, 32, 32, 32, 32};
static __I uint8_t ADC1MCLKPresTable[4] = {6, 12, 24, 48};
/** RCC Driving Functions Declaration **/
/**
*\*\name RCC_Reset.
*\*\fun Reset the RCC registers.
*\*\param none
*\*\return none
**/
void RCC_Reset(void)
{
/* Set SYSPRES[1:0] bit */
RCC->CFG |= (uint32_t)0x00003000;
/* Reset MCO[1:0] APBPRES[2:0] AHBPRES[3:0] bit */
RCC->CFG &= (uint32_t)0xF9FFF80F;
/* Reset LSIDETEN bit */
RCC->LSICTRL &= (uint32_t)0xFFFFFF7F;
/* Reset TIM1CLKSEL TIM6CLKSEL ADCPRES[3:0]bit */
RCC->CFG2 &= (uint32_t)0x3FFFFFF0;
/* Set ADC1MPRES[1:0] ADCPRES[3:0]bit */
RCC->CFG2 |= (uint32_t)0x00000C01;
}
/**
*\*\name RCC_HSI_Calibration_Value_Set.
*\*\fun Adjusts the Internal High Speed oscillator (HSI) calibration value.
*\*\param calibration_value(the calibration trimming value):
*\*\ This parameter must be a number between 0 and 0x0F
*\*\return none
**/
void RCC_HSI_Calibration_Value_Set(uint8_t calibration_value)
{
uint32_t temp_value = 0;
temp_value = RCC->HSICTRL;
/* Clear HSITRIM[3:0] bits */
temp_value &= RCC_HSITRIM_MASK;
/* Set the HSITRIM[3:0] bits according to HSICalibrationValue value */
temp_value |= (uint32_t)calibration_value << RCC_CTRL_HSITRIM_OFFSET;
/* Store the new value */
RCC->HSICTRL = temp_value;
}
/**
*\*\name RCC_LSI_Calibration_Value_Set.
*\*\fun Adjusts the Internal Low Speed oscillator (LSI) calibration value.
*\*\param calibration_value(the calibration trimming value):
*\*\ This parameter must be a number between 0 and 0x1F
*\*\return none
**/
void RCC_LSI_Calibration_Value_Set(uint8_t calibration_value)
{
uint32_t temp_value = 0;
temp_value = RCC->LSICTRL;
/* Clear LSITRIM[4:0] bits */
temp_value &= RCC_LSITRIM_MASK;
/* Set the LSITRIM[4:0] bits according to LSICalibrationValue value */
temp_value |= (uint32_t)calibration_value << RCC_CTRL_LSITRIM_OFFSET;
/* Store the new value */
RCC->LSICTRL = temp_value;
}
/**
*\*\name RCC_Sysclk_Config.
*\*\fun Configures the system clock (SYSCLK).
*\*\When HSI is 48M:
*\*\param HSI_div(system clock is derived from the HSI clock):
*\*\ - RCC_HSICLK_DIV1 system clock = HSI clock
*\*\ - RCC_HSICLK_DIV2 system clock = HSI clock/2
*\*\ - RCC_HSICLK_DIV6 system clock = HSI clock/6
*\*\When HSI is 40M:
*\*\param HSI_div(system clock is derived from the HSI clock):
*\*\ - RCC_HSICLK_DIV1 system clock = HSI clock
*\*\ - RCC_HSICLK_DIV5 system clock = HSI clock/5
*\*\return none
**/
void RCC_Sysclk_Config(uint32_t HSI_div)
{
uint32_t temp_value = 0;
temp_value = RCC->CFG;
/* Clear SYSPRES[1:0] bits */
temp_value &= RCC_HSICLK_DIV_MASK;
/* Set SYSPRES[1:0] bits according to HSI_div value */
temp_value |= HSI_div;
/* Store the new value */
RCC->CFG = temp_value;
}
/**
*\*\name RCC_Hclk_Config.
*\*\fun Configures the AHB clock (HCLK).
*\*\param sysclk_div(AHB clock is derived from the system clock (SYSCLK)):
*\*\ - RCC_SYSCLK_DIV1 AHB clock = SYSCLK
*\*\ - RCC_SYSCLK_DIV2 AHB clock = SYSCLK/2
*\*\ - RCC_SYSCLK_DIV4 AHB clock = SYSCLK/4
*\*\ - RCC_SYSCLK_DIV8 AHB clock = SYSCLK/8
*\*\ - RCC_SYSCLK_DIV12 AHB clock = SYSCLK/12
*\*\ - RCC_SYSCLK_DIV16 AHB clock = SYSCLK/16
*\*\ - RCC_SYSCLK_DIV24 AHB clock = SYSCLK/24
*\*\return none
**/
void RCC_Hclk_Config(uint32_t sysclk_div)
{
uint32_t temp_value = 0;
temp_value = RCC->CFG;
/* Clear AHBPRES[3:0] bits */
temp_value &= RCC_SYSCLK_DIV_MASK;
/* Set AHBPRES[3:0] bits according to rcc_sysclk value */
temp_value |= sysclk_div;
/* Store the new value */
RCC->CFG = temp_value;
}
/**
*\*\name RCC_Pclk_Config.
*\*\fun Configures the Low Speed APB clock (PCLK1).
*\*\param hclk_div(APB1 clock is derived from the AHB clock (HCLK)):
*\*\ - RCC_HCLK_DIV1 APB1 clock = HCLK
*\*\ - RCC_HCLK_DIV2 APB1 clock = HCLK/2
*\*\ - RCC_HCLK_DIV4 APB1 clock = HCLK/4
*\*\ - RCC_HCLK_DIV8 APB1 clock = HCLK/8
*\*\ - RCC_HCLK_DIV16 APB1 clock = HCLK/16
*\*\return none
**/
void RCC_Pclk_Config(uint32_t hclk_div)
{
uint32_t temp_value = 0;
temp_value = RCC->CFG;
/* Clear APB1PRES[2:0] bits */
temp_value &= RCC_APB_DIV_MASK;
/* Set APB1PRES[2:0] bits according to hclk_div value */
temp_value |= hclk_div;
/* Store the new value */
RCC->CFG = temp_value;
}
/**
*\*\name RCC_TIM1_Clock_Config.
*\*\fun Configures the TIM1 clock source(TIM1CLK).
*\*\param timer_clksrc(TIM1 clock source):
*\*\ - RCC_TIM1_CLKSRC_PCLK
*\*\ - RCC_TIM1_CLKSRC_SYSCLK
*\*\return none
**/
void RCC_TIM1_Clock_Config(uint32_t timer_clksrc)
{
uint32_t temp_value = 0;
temp_value = RCC->CFG2;
/* Clear TIMCLK_SEL bits */
temp_value &= RCC_TIM1_CLKSRC_MASK;
/* Set TIMCLK_SEL bits according to timer_clksrc value */
temp_value |= timer_clksrc;
/* Store the new value */
RCC->CFG2 = temp_value;
}
/**
*\*\name RCC_ADC_1M_Clock_Config.
*\*\fun Configures the ADC 1M clock (ADC1MCLK).
*\*\param ADC1M_prescaler(ADC1M clock prescaler):
*\*\ - RCC_ADC1MCLK_DIV6 HSI Clock Divided By 6
*\*\ - RCC_ADC1MCLK_DIV12 HSI Clock Divided By 12
*\*\ - RCC_ADC1MCLK_DIV24 HSI Clock Divided By 24
*\*\ - RCC_ADC1MCLK_DIV40 HSI Clock Divided By 40
*\*\ - RCC_ADC1MCLK_DIV48 HSI Clock Divided By 48
*\*\return none
*\*\note To ensure normal work of the ADC module, the HSI divide result must be 1Mhz.
**/
void RCC_ADC_1M_Clock_Config(uint32_t ADC1M_prescaler)
{
uint32_t temp_value = 0;
temp_value = RCC->CFG2;
/* Clear ADC1MPRE[1:0] bits */
temp_value &= RCC_ADC1MCLK_DIV_MASK;
/* Set ADC1MPRE[1:0] bits according to ADC1M_prescaler value */
temp_value |= ADC1M_prescaler;
/* Store the new value */
RCC->CFG2 = temp_value;
}
/**
*\*\name RCC_ADC_Clock_Config.
*\*\fun Configures the ADCHCLK prescaler.
*\*\param ADC_prescaler(ADCHCLK prescaler):
*\*\ - RCC_ADC_DIV1 HSI Clock Divided By 1
*\*\ - RCC_ADC_DIV2 HSI Clock Divided By 2
*\*\ - RCC_ADC_DIV3 HSI Clock Divided By 3
*\*\ - RCC_ADC_DIV4 HSI Clock Divided By 4
*\*\ - RCC_ADC_DIV6 HSI Clock Divided By 6
*\*\ - RCC_ADC_DIV8 HSI Clock Divided By 8
*\*\ - RCC_ADC_DIV10 HSI Clock Divided By 10
*\*\ - RCC_ADC_DIV12 HSI Clock Divided By 12
*\*\ - RCC_ADC_DIV24 HSI Clock Divided By 24
*\*\ - RCC_ADC_DIV32 HSI Clock Divided By 32
*\*\ - RCC_ADC_DIV_OTHERS HSI Clock Divided By 32
*\*\return none
**/
void RCC_ADC_Clock_Config(uint32_t ADC_prescaler)
{
uint32_t temp_value = 0;
temp_value = RCC->CFG2;
/* Clear ADCPRES[3:0] bits */
temp_value &= RCC_ADC_DIV_MASK;
/* Set ADCPRES[3:0] bits according to ADC_prescaler value */
temp_value |= ADC_prescaler;
/* Store the new value */
RCC->CFG2 = temp_value;
}
/**
*\*\name RCC_TIM6_Clock_Config.
*\*\fun Configures the TIM6 clock source(TIM6CLK).
*\*\param timer_clksrc(TIM6 clock source):
*\*\ - RCC_TIM6_CLKSRC_PCLK
*\*\ - RCC_TIM6_CLKSRC_LSI
*\*\return none
**/
void RCC_TIM6_Clock_Config(uint32_t timer_clksrc)
{
uint32_t temp_value = 0;
temp_value = RCC->CFG2;
/* Clear TIM6CLK_SEL bits */
temp_value &= RCC_TIM6_CLKSRC_MASK;
/* Set TIM6CLK_SEL bits according to timer_clksrc value */
temp_value |= timer_clksrc;
/* Store the new value */
RCC->CFG2 = temp_value;
}
/**
*\*\name RCC_Clocks_Frequencies_Value_Get.
*\*\fun Returns the frequencies of different on chip clocks.
*\*\param RCC_clocks pointer to a RCC_ClocksType structure which will hold
*\*\ the clocks frequencies.
*\*\return none
*\*\note The result of this function could be not correct when using
*\*\ fractional value for HSI crystal.
**/
void RCC_Clocks_Frequencies_Value_Get(RCC_ClocksType* RCC_clocks)
{
uint32_t temp_value = 0;
uint32_t presc_value = 0;
/* Get SYSCLK source
* -------------------------------------------------------*/
temp_value = PWR->CTRL3 & PWR_CTRL3_HSISEL;
switch (temp_value)
{
case PWR_CTRL3_HSISEL: /* HSI 40M used as system clock */
if((RCC->CFG & RCC_CFG_SYSPRES) == RCC_HSICLK_DIV1)
{
RCC_clocks->SysclkFreq = SYSCLK_FREQ_40M;
}
else
{
RCC_clocks->SysclkFreq = SYSCLK_FREQ_8M;
}
/* Get ADCCLK prescaler */
presc_value = ADCCLKPresTable[(RCC->CFG & RCC_CFG2_ADCPRES)];
/* ADCCLK clock frequency */
RCC_clocks->AdcClkFreq = HSI_FREQ_40M/presc_value;
/* Get ADC1MCLK prescaler */
RCC_clocks->Adc1MClkFreq = HSI_FREQ_40M/40;
break;
default:/* HSI 48M used as system clock */
if((RCC->CFG & RCC_CFG_SYSPRES) == RCC_HSICLK_DIV1)
{
RCC_clocks->SysclkFreq = SYSCLK_FREQ_48M;
}
else if((RCC->CFG & RCC_CFG_SYSPRES) == RCC_HSICLK_DIV2)
{
RCC_clocks->SysclkFreq = SYSCLK_FREQ_24M;
}
else
{
RCC_clocks->SysclkFreq = SYSCLK_FREQ_8M;
}
/* Get ADCCLK prescaler */
presc_value = ADCCLKPresTable[(RCC->CFG & RCC_CFG2_ADCPRES)];
/* ADCCLK clock frequency */
RCC_clocks->AdcClkFreq = HSI_FREQ_48M/presc_value;
/* Get ADC1MCLK prescaler */
presc_value = ADC1MCLKPresTable[((RCC->CFG & RCC_CFG2_ADC1MPRES) >> RCC_CFG2_ADC1MPRES_OFFSET)];
/* ADCCLK clock frequency */
RCC_clocks->Adc1MClkFreq = HSI_FREQ_48M/presc_value;
break;
}
/* Get HCLK prescaler */
presc_value = AHBPresTable[((RCC->CFG & RCC_CFG_AHBPRES) >> RCC_CFG_AHBPRES_OFFSET)];
/* HCLK clock frequency */
RCC_clocks->HclkFreq = RCC_clocks->SysclkFreq/presc_value;
/* Get PCLK prescaler */
presc_value = APBPresTable[((RCC->CFG & RCC_CFG_APBPRES) >> RCC_CFG_APBPRES_OFFSET)];
/* PCLK clock frequency */
RCC_clocks->PclkFreq = RCC_clocks->HclkFreq/presc_value;
}
/**
*\*\name RCC_AHB_Peripheral_Clock_Enable.
*\*\fun Enables the AHB peripheral clock.
*\*\param AHB_periph (AHB peripheral to gates its clock):
*\*\ - RCC_AHB_PERIPH_CRC
*\*\ - RCC_AHB_PERIPH_ADC
*\*\return none
**/
void RCC_AHB_Peripheral_Clock_Enable(uint32_t AHB_periph)
{
RCC->AHBPCLKEN |= AHB_periph;
}
/**
*\*\name RCC_AHB_Peripheral_Clock_Disable.
*\*\fun Disables the AHB peripheral clock.
*\*\param AHB_periph (AHB peripheral to gates its clock):
*\*\ - RCC_AHB_PERIPH_CRC
*\*\ - RCC_AHB_PERIPH_ADC
*\*\return none
**/
void RCC_AHB_Peripheral_Clock_Disable(uint32_t AHB_periph)
{
RCC->AHBPCLKEN &= ~AHB_periph;
}
/**
*\*\name RCC_APB_Peripheral_Clock_Enable.
*\*\fun Enables the High Speed APB (APB1) peripheral clock.
*\*\param APB_periph (APB1 peripheral to gates its clock):
*\*\ - RCC_APB_PERIPH_AFIO
*\*\ - RCC_APB_PERIPH_BEEPER
*\*\ - RCC_APB_PERIPH_IOPA
*\*\ - RCC_APB_PERIPH_IOPB
*\*\ - RCC_APB_PERIPH_COMP
*\*\ - RCC_APB_PERIPH_COMP_FILT
*\*\ - RCC_APB_PERIPH_UART1
*\*\ - RCC_APB_PERIPH_UART2
*\*\ - RCC_APB_PERIPH_I2C
*\*\ - RCC_APB_PERIPH_PWR
*\*\ - RCC_APB_PERIPH_SPI
*\*\ - RCC_APB_PERIPH_TIM1
*\*\ - RCC_APB_PERIPH_TIM3
*\*\ - RCC_APB_PERIPH_TIM6
*\*\ - RCC_APB_PERIPH_IWDG
*\*\return none.
**/
void RCC_APB_Peripheral_Clock_Enable(uint32_t APB_periph)
{
RCC->APBPCLKEN |= APB_periph;
}
/**
*\*\name RCC_APB_Peripheral_Clock_Disable.
*\*\fun Disables the High Speed APB (APB1) peripheral clock.
*\*\param APB_periph (APB1 peripheral to gates its clock):
*\*\ - RCC_APB_PERIPH_AFIO
*\*\ - RCC_APB_PERIPH_BEEPER
*\*\ - RCC_APB_PERIPH_IOPA
*\*\ - RCC_APB_PERIPH_IOPB
*\*\ - RCC_APB_PERIPH_COMP
*\*\ - RCC_APB_PERIPH_COMP_FILT
*\*\ - RCC_APB_PERIPH_UART1
*\*\ - RCC_APB_PERIPH_UART2
*\*\ - RCC_APB_PERIPH_I2C
*\*\ - RCC_APB_PERIPH_PWR
*\*\ - RCC_APB_PERIPH_SPI
*\*\ - RCC_APB_PERIPH_TIM1
*\*\ - RCC_APB_PERIPH_TIM3
*\*\ - RCC_APB_PERIPH_TIM6
*\*\ - RCC_APB_PERIPH_IWDG
*\*\return none.
**/
void RCC_APB_Peripheral_Clock_Disable(uint32_t APB_periph)
{
RCC->APBPCLKEN &= ~APB_periph;
}
/**
*\*\name RCC_Peripheral_Reset.
*\*\fun AHB and APB peripheral reset.
*\*\param Periph specifies the APB peripheral to reset.
*\*\ - RCC_RST_AFIORST
*\*\ - RCC_RST_BEEPRST
*\*\ - RCC_RST_GPIOARST
*\*\ - RCC_RST_GPIOBRST
*\*\ - RCC_RST_UART1RST
*\*\ - RCC_RST_UART2RST
*\*\ - RCC_RST_I2CRST
*\*\ - RCC_RST_PWRRST
*\*\ - RCC_RST_ADCRST
*\*\ - RCC_RST_SPIRST
*\*\ - RCC_RST_TIM1RST
*\*\ - RCC_RST_TIM3RST
*\*\ - RCC_RST_TIM6RST
*\*\ - RCC_RST_COMPRST
*\*\return none.
**/
void RCC_Peripheral_Reset(uint32_t Periph)
{
RCC->PRST |= Periph;
RCC->PRST &= ~Periph;
}
/**
*\*\name RCC_MCO_Prescaler_Config.
*\*\fun Configures the MCO clock prescaler.
*\*\param MCO_prescaler(MCO clock prescaler):
*\*\ - RCC_MCO_CLK_DIV1
*\*\ - RCC_MCO_CLK_DIV2
*\*\ - RCC_MCO_CLK_DIV3
*\*\ - RCC_MCO_CLK_DIV4
*\*\ - RCC_MCO_CLK_DIV5
*\*\ - RCC_MCO_CLK_DIV6
*\*\ - RCC_MCO_CLK_DIV7
*\*\ - RCC_MCO_CLK_DIV8
*\*\ - RCC_MCO_CLK_DIV9
*\*\ - RCC_MCO_CLK_DIV10
*\*\ - RCC_MCO_CLK_DIV11
*\*\ - RCC_MCO_CLK_DIV12
*\*\ - RCC_MCO_CLK_DIV13
*\*\ - RCC_MCO_CLK_DIV14
*\*\ - RCC_MCO_CLK_DIV15
*\*\ - RCC_MCO_CLK_DIV32
*\*\return none.
*\*\note if MCO select LSI,the minimum MCO_prescaler is RCC_MCO_CLK_DIV1
\*\ if MCO select HSI,the minimum MCO_prescaler is RCC_MCO_CLK_DIV2
**/
void RCC_MCO_Prescaler_Config(uint32_t MCO_prescaler)
{
uint32_t temp_value = 0;
temp_value = RCC->CFG;
/* Clear MCOPRE[3:0] bits */
temp_value &= RCC_MCO_CLK_DIV_MASK;
/* Set MCOPRE[3:0] bits according to MCO_prescaler value */
temp_value |= MCO_prescaler;
/* Store the new value */
RCC->CFG = temp_value;
}
/**
*\*\name RCC_MCO_Source_Config.
*\*\fun Selects the clock source to output on MCO pin.
*\*\param MCO_source(clock source to output):
*\*\ - RCC_MCO_NOCLK
*\*\ - RCC_MCO_HSI
*\*\ - RCC_MCO_LSI
*\*\return none.
**/
void RCC_MCO_Source_Config(uint32_t MCO_source)
{
uint32_t temp_value = 0;
temp_value = RCC->CFG;
/* Clear MCO[1:0] bits */
temp_value &= RCC_MCO_MASK;
/* Set MCO[1:0] bits according to MCO_source value */
temp_value |= MCO_source;
/* Store the new value */
RCC->CFG = temp_value;
}
/**
*\*\name RCC_Flag_Status_Get.
*\*\fun Checks whether the specified RCC flag is set or not.
*\*\param RCC_flag:
*\*\ - RCC_FLAG_HSI40MRDF HSI 40M oscillator clock ready
*\*\ - RCC_FLAG_HSI48MRDF HSI 48M oscillator clock ready
*\*\ - RCC_FLAG_LSIRDF LSI 32k oscillator clock ready
*\*\ - RCC_FLAG_LSIDETFF LSI 32k detect finish
*\*\ - RCC_FLAG_PINRST Pin reset
*\*\ - RCC_FLAG_PORRST POR/PDR reset
*\*\ - RCC_FLAG_SFTRST Software reset
*\*\ - RCC_FLAG_IWDGRST Independent Watchdog reset
*\*\ - RCC_FLAG_LVRRST LVR reset
*\*\ - RCC_FLAG_LPWRRST Low Power reset
*\*\ - RCC_FLAG_EMCCLAMPF EMC Power reset
*\*\return FlagStatus:
*\*\ - SET
*\*\ - RESET
**/
FlagStatus RCC_Flag_Status_Get(uint8_t RCC_flag)
{
uint32_t temp_value = 0;
uint32_t reg_value = 0;
/* Get the RCC register index */
temp_value = RCC_flag >> RCC_FLAG_OFFSET;
switch(temp_value)
{
case 1: /* The flag to check is in HSICTRL register */
reg_value = RCC->HSICTRL;
break;
case 2: /* The flag to check is in LSICTRL register */
reg_value = RCC->LSICTRL;
break;
default:/* The flag to check is in CTRLSTS register */
reg_value = RCC->CTRLSTS;
break;
}
/* Get the flag position */
temp_value = RCC_flag & FLAG_Mask;
if ((reg_value & ((uint32_t)1 << temp_value)) != (uint32_t)RESET)
{
return SET;
}
else
{
return RESET;
}
}
/**
*\*\name RCC_Reset_Flag_Clear.
*\*\fun Clears the RCC reset flags.
*\*\param none
*\*\return none
**/
void RCC_Reset_Flag_Clear(void)
{
/* Set RMRSTF bit to clear the reset flags */
RCC->CTRLSTS |= RCC_REMOVE_RESET_FLAG;
/* RMRSTF bit should be reset */
RCC->CTRLSTS &= (~RCC_REMOVE_RESET_FLAG);
}
/**
*\*\name RCC_EMC_Reset_Disable.
*\*\fun Disable the RCC's EMC Clamp reset bits.
*\*\param none
*\*\return none
**/
void RCC_EMC_Reset_Disable(void)
{
RCC->EMCCTRL &= (~RCC_EMCCTRL_EMCRSTEN);
}
/**
*\*\name RCC_EMC_Reset_Enable.
*\*\fun Enable the RCC's EMC Clamp reset bits.
*\*\param none
*\*\return none
**/
void RCC_EMC_Reset_Enable(void)
{
RCC->EMCCTRL |= RCC_EMCCTRL_EMCRSTEN;
}
/**
*\*\name RCC_EMC_Detect_Disable.
*\*\fun Disable the RCC's EMC Clamp detect bits.
*\*\param none
*\*\return none
**/
void RCC_EMC_Detect_Disable(void)
{
RCC->EMCCTRL &= (~RCC_EMCCTRL_EMCDETEN);
}
/**
*\*\name RCC_EMC_Detect_Enable.
*\*\fun Enable the RCC's EMC Clamp detect bits.
*\*\param none
*\*\return none
**/
void RCC_EMC_Detect_Enable(void)
{
RCC->EMCCTRL |= RCC_EMCCTRL_EMCDETEN;
}
/**
*\*\name RCC_LSI_Detect_Disable.
*\*\fun Disable the LSI detect.
*\*\param none
*\*\return none
**/
void RCC_LSI_Detect_Disable(void)
{
RCC->LSICTRL &= (~RCC_LSICTRL_LSIDETEN);
}
/**
*\*\name RCC_LSI_Detect_Enable.
*\*\fun Enable the LSI detect.
*\*\param none
*\*\return none
**/
void RCC_LSI_Detect_Enable(void)
{
RCC->LSICTRL |= RCC_LSICTRL_LSIDETEN;
}
/**
*\*\name RCC_LSI_Clocks_Frequencies_Get.
*\*\fun Get the LSI Frequencies.
*\*\param none
*\*\return LSIFREQ[15:0] (LSI Frequencies LSICLK(kHz)= 8*HSICLK/LSIFREQ[15:0] (HSICLK is 48000kHz or 40000kHz))
**/
uint16_t RCC_LSI_Clocks_Frequencies_Get(void)
{
return (uint16_t)((RCC->LSICTRL & RCC_LSICTRL_LSIFREQ) >> 8);
}
/******************* (C) COPYRIGHT 2018 NATIONZ *****END OF FILE****/

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/**
* Copyright (c) 2022, Nations Technologies Inc.
*
* All rights reserved.
*
* This software is the exclusive property of Nations Technologies Inc. (Hereinafter
* referred to as NATIONS). This software, and the product of NATIONS described herein
* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties
* of the People's Republic of China and other applicable jurisdictions worldwide.
*
* NATIONS does not grant any license under its patents, copyrights, trademarks, or other
* intellectual property rights. Names and brands of third party may be mentioned or referred
* thereto (if any) for identification purposes only.
*
* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and
* improvements to this software at any time without notice. Please contact NATIONS and obtain
* the latest version of this software before placing orders.
* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes
* no responsibility for the accuracy and reliability of this software.
*
* It is the responsibility of the user of this software to properly design, program, and test
* the functionality and safety of any application made of this information and any resulting product.
* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or
* consequential damages arising in any way out of the use of this software or the Product.
*
* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any
* malfunction or failure of which may cause loss of human life, bodily injury or severe property
* damage. Such applications are deemed, "Insecure Usage".
*
* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS
* harmless from and against all claims, costs, damages, and other liabilities, arising from or related
* to any customer's Insecure Usage.
* Any express or implied warranty with regard to this software or the Product, including,but not
* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement
* are disclaimed to the fullest extent permitted by law.
* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe
* or otherwise distribute this software for any purposes, in whole or in part.
*
* NATIONS products and technologies shall not be used for or incorporated into any products or systems
* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations.
* User shall comply with any applicable export control laws and regulations promulgated and administered by
* the governments of any countries asserting jurisdiction over the parties or transactions.
**/
/**
*\*\file n32g003_spi.c
*\*\author Nations
*\*\version v1.0.0
*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
**/
#include "n32g003_spi.h"
#include "n32g003_rcc.h"
/* SPI Driving Functions Declaration */
/**
*\*\name SPI_Reset.
*\*\fun Reset the SPI registers.
*\*\param none
*\*\return none
**/
void SPI_Reset(void)
{
/* SPI Reset */
RCC_Peripheral_Reset(RCC_RST_SPIRST);
}
/**
*\*\name SPI_ON.
*\*\fun SPI turn ON.
*\*\param none
*\*\return none
**/
void SPI_ON(void)
{
/* Enable SPI */
SPI->CTRL1 |= SPI_TURN_ON;
}
/**
*\*\name SPI_OFF.
*\*\fun SPI turn OFF.
*\*\param none
*\*\return none
**/
void SPI_OFF(void)
{
/* Disable SPI */
SPI->CTRL1 &= SPI_TURN_OFF;
}
/**
*\*\name SPI_Initializes_Structure.
*\*\fun Fills each SPI_InitStruct member with its default value.
*\*\param SPI_InitStruct :
*\*\ - DataDirection
*\*\ - SpiMode
*\*\ - DataLen
*\*\ - CLKPOL
*\*\ - CLKPHA
*\*\ - NSS
*\*\ - BaudRatePres
*\*\ - FirstBit
*\*\return none
**/
void SPI_Initializes_Structure(SPI_InitType* SPI_InitStruct)
{
/* Initialize the DataDirection member */
SPI_InitStruct->DataDirection = SPI_DIR_DOUBLELINE_FULLDUPLEX;
/* initialize the SpiMode member */
SPI_InitStruct->SpiMode = SPI_MODE_SLAVE;
/* initialize the DataLen member */
SPI_InitStruct->DataLen = SPI_DATA_SIZE_8BITS;
/* Initialize the CLKPOL member */
SPI_InitStruct->CLKPOL = SPI_CLKPOL_LOW;
/* Initialize the CLKPHA member */
SPI_InitStruct->CLKPHA = SPI_CLKPHA_FIRST_EDGE;
/* Initialize the NSS member */
SPI_InitStruct->NSS = SPI_NSS_HARD;
/* Initialize the BaudRatePres member */
SPI_InitStruct->BaudRatePres = SPI_BR_PRESCALER_2;
/* Initialize the FirstBit member */
SPI_InitStruct->FirstBit = SPI_FB_MSB;
}
/**
*\*\name SPI_DataDirection_Config.
*\*\fun Config the SPI DataDirection.
*\*\param DataDirection :
*\*\ - SPI_DIR_DOUBLELINE_FULLDUPLEX
*\*\ - SPI_DIR_DOUBLELINE_RONLY_TX
*\*\ - SPI_DIR_DOUBLELINE_RONLY_RX
*\*\ - SPI_DIR_SINGLELINE_RX
*\*\ - SPI_DIR_SINGLELINE_TX
*\*\return none
**/
void SPI_DataDirection_Config(uint16_t DataDirection)
{
/* Clear SPI_CTRL1[15:14] and [10] bits */
SPI->CTRL1 &= SPI_DATADIRECTION_MASK;
/* Set SPI_CTRL1[15:14] and [10] bits */
SPI->CTRL1 |= DataDirection;
}
/**
*\*\name SPI_SpiMode_Config.
*\*\fun Config the SPI mode.
*\*\param SpiMode :
*\*\ - SPI_MODE_MASTER
*\*\ - SPI_MODE_SLAVE
*\*\return none
**/
void SPI_SpiMode_Config(uint16_t SpiMode)
{
/* Clear SPI_CTRL1 MSEL bits */
SPI->CTRL1 &= SPI_MODE_MASK;
/* Set SPI_CTRL1 MSEL bits */
SPI->CTRL1 |= SpiMode;
}
/**
*\*\name SPI_DataLen_Config.
*\*\fun Config the SPI DataLen.
*\*\param DataLen :
*\*\ - SPI_DATA_SIZE_16BITS
*\*\ - SPI_DATA_SIZE_8BITS
*\*\return none
*\*\note Must be used with SPI OFF.
**/
void SPI_DataLen_Config(uint16_t DataLen)
{
/* Clear SPI_CTRL1 DATFF bits */
SPI->CTRL1 &= SPI_DATALEN_MASK;
/* Set SPI_CTRL1 DATFF bits */
SPI->CTRL1 |= DataLen;
}
/**
*\*\name SPI_CLKPOL_Config.
*\*\fun Config the SPI CLKPOL.
*\*\param CLKPOL :
*\*\ - SPI_CLKPOL_LOW
*\*\ - SPI_CLKPOL_HIGH
*\*\return none
**/
void SPI_CLKPOL_Config(uint16_t CLKPOL)
{
/* Clear SPI_CTRL1 CLKPOL bits */
SPI->CTRL1 &= SPI_CLKPOL_MASK;
/* Set SPI_CTRL1 CLKPOL bits */
SPI->CTRL1 |= CLKPOL;
}
/**
*\*\name SPI_CLKPHA_Config.
*\*\fun Config the SPI CLKPHA.
*\*\param CLKPHA :
*\*\ - SPI_CLKPHA_FIRST_EDGE
*\*\ - SPI_CLKPHA_SECOND_EDGE
*\*\return none
**/
void SPI_CLKPHA_Config(uint16_t CLKPHA)
{
/* Clear SPI_CTRL1 CLKPHA bits */
SPI->CTRL1 &= SPI_CLKPHA_MASK;
/* Set SPI_CTRL1 CLKPHA bits */
SPI->CTRL1 |= CLKPHA;
}
/**
*\*\name SPI_NSS_Config.
*\*\fun Config the SPI NSS.
*\*\param NSS :
*\*\ - SPI_NSS_SOFT
*\*\ - SPI_NSS_HARD
*\*\return none
**/
void SPI_NSS_Config(uint16_t NSS)
{
/* Clear SPI_CTRL1 SSMEN bits */
SPI->CTRL1 &= SPI_NSS_MASK;
/* Set SPI_CTRL1 SSMEN bits */
SPI->CTRL1 |= NSS;
}
/**
*\*\name SPI_BaudRatePres_Config.
*\*\fun Config the SPI BaudRatePres.
*\*\param BaudRatePres :
*\*\ - SPI_BR_PRESCALER_2
*\*\ - SPI_BR_PRESCALER_4
*\*\ - SPI_BR_PRESCALER_8
*\*\ - SPI_BR_PRESCALER_16
*\*\ - SPI_BR_PRESCALER_32
*\*\ - SPI_BR_PRESCALER_64
*\*\ - SPI_BR_PRESCALER_128
*\*\ - SPI_BR_PRESCALER_256
*\*\return none
**/
void SPI_BaudRatePres_Config(uint16_t BaudRatePres)
{
/* Clear SPI_CTRL1 BR[2:0] bits */
SPI->CTRL1 &= SPI_BAUDRATEPRES_MASK;
/* Set SPI_CTRL1 BR[2:0] bits */
SPI->CTRL1 |= BaudRatePres;
}
/**
*\*\name SPI_FirstBit_Config.
*\*\fun Config the SPI FirstBit.
*\*\param FirstBit :
*\*\ - SPI_FB_MSB
*\*\ - SPI_FB_LSB
*\*\return none
**/
void SPI_FirstBit_Config(uint16_t FirstBit)
{
/* Clear SPI_CTRL1 LSBFF bits */
SPI->CTRL1 &= SPI_FIRSTBIT_MASK;
/* Set SPI_CTRL1 LSBFF bits */
SPI->CTRL1 |= FirstBit;
}
/**
*\*\name SPI_Initializes.
*\*\fun Initializes the SPI according to SPI_InitStruct.
*\*\param SPI_InitStruct :
*\*\ - DataDirection
*\*\ - SPI_DIR_DOUBLELINE_FULLDUPLEX
*\*\ - SPI_DIR_DOUBLELINE_RONLY_TX
*\*\ - SPI_DIR_DOUBLELINE_RONLY_RX
*\*\ - SPI_DIR_SINGLELINE_RX
*\*\ - SPI_DIR_SINGLELINE_TX
*\*\ - SpiMode
*\*\ - SPI_MODE_MASTER
*\*\ - SPI_MODE_SLAVE
*\*\ - DataLen
*\*\ - SPI_DATA_SIZE_16BITS
*\*\ - SPI_DATA_SIZE_8BITS
*\*\ - CLKPOL
*\*\ - SPI_CLKPOL_LOW
*\*\ - SPI_CLKPOL_HIGH
*\*\ - CLKPHA
*\*\ - SPI_CLKPHA_FIRST_EDGE
*\*\ - SPI_CLKPHA_SECOND_EDGE
*\*\ - NSS
*\*\ - SPI_NSS_SOFT
*\*\ - SPI_NSS_HARD
*\*\ - BaudRatePres
*\*\ - SPI_BR_PRESCALER_2
*\*\ - SPI_BR_PRESCALER_4
*\*\ - SPI_BR_PRESCALER_8
*\*\ - SPI_BR_PRESCALER_16
*\*\ - SPI_BR_PRESCALER_32
*\*\ - SPI_BR_PRESCALER_64
*\*\ - SPI_BR_PRESCALER_128
*\*\ - SPI_BR_PRESCALER_256
*\*\ - FirstBit
*\*\ - SPI_FB_MSB
*\*\ - SPI_FB_LSB
*\*\return none
**/
void SPI_Initializes(SPI_InitType* SPI_InitStruct)
{
SPI_DataDirection_Config(SPI_InitStruct->DataDirection);
SPI_SpiMode_Config(SPI_InitStruct->SpiMode);
SPI_DataLen_Config(SPI_InitStruct->DataLen);
SPI_CLKPHA_Config(SPI_InitStruct->CLKPHA);
SPI_CLKPOL_Config(SPI_InitStruct->CLKPOL);
SPI_NSS_Config(SPI_InitStruct->NSS);
SPI_BaudRatePres_Config(SPI_InitStruct->BaudRatePres);
SPI_FirstBit_Config(SPI_InitStruct->FirstBit);
}
/**
*\*\name SPI_Set_Nss_Level.
*\*\fun Configures internally by software the NSS pin for the selected SPI.
*\*\param SPI_NSS_Internal_Soft :
*\*\ - SPI_NSS_HIGH
*\*\ - SPI_NSS_LOW
*\*\return none
**/
void SPI_Set_Nss_Level(uint16_t SPI_NSS_Internal_Soft)
{
if(SPI_NSS_Internal_Soft == SPI_NSS_HIGH)
{
/* Set NSS pin internally by software */
SPI->CTRL1 |= SPI_NSS_HIGH;
}
else
{
/* Reset NSS pin internally by software */
SPI->CTRL1 &= SPI_NSS_LOW;
}
}
/**
*\*\name SPI_NSS_Output_Enable.
*\*\fun Enables the NSS output for the selected SPI.
*\*\return none
**/
void SPI_NSS_Output_Enable(void)
{
/* Set the SPI_CTRL2 SSOEN bit to enable NSS output */
SPI->CTRL2 |= SPI_NSS_OUTPUT_ENABLE;
}
/**
*\*\name SPI_NSS_Output_Disable.
*\*\fun Disable the NSS output for the selected SPI.
*\*\return none
**/
void SPI_NSS_Output_Disable(void)
{
/* Clean the SPI_CTRL2 SSOEN bit to disable SS output */
SPI->CTRL2 &= SPI_NSS_OUTPUT_DISABLE;
}
/**
*\*\name SPI_Interrupts_Enable.
*\*\fun Enable SPI interrupts.
*\*\param spi_interrupt :
*\*\ - SPI_INT_TE SPI_CTRL2
*\*\ - SPI_INT_RNE SPI_CTRL2
*\*\ - SPI_INT_ERR SPI_CTRL2
*\*\return none
**/
void SPI_Interrupts_Enable(uint8_t spi_interrupt)
{
/* Set the SPI_CTRL2 TEINTEN/RNEINTEN/ERRINTEN bit to enable SPI interrupts */
SPI->CTRL2 |= spi_interrupt;
}
/**
*\*\name SPI_Interrupts_Disable.
*\*\fun Disable SPI interrupts.
*\*\param spi_interrupt :
*\*\ - SPI_INT_TE SPI_CTRL2
*\*\ - SPI_INT_RNE SPI_CTRL2
*\*\ - SPI_INT_ERR SPI_CTRL2
*\*\return none
**/
void SPI_Interrupts_Disable(uint8_t spi_interrupt)
{
/* Clean the SPI_CTRL2 TEINTEN/RNEINTEN/ERRINTEN bit to disable SPI interrupts */
SPI->CTRL2 &= (~spi_interrupt);
}
/**
*\*\name SPI_Data_Transmit.
*\*\fun Transmits a Data through the SPI peripheral.
*\*\param Data: data to be transmitted
*\*\return none
**/
void SPI_Data_Transmit(uint16_t Data)
{
/* Write in the SPI_DAT register the data to be sent */
SPI->DAT = Data;
}
/**
*\*\name SPI_Data_Get.
*\*\fun Get SPI data from SPI_DAT register.
*\*\return The data in the SPI_DAT register
**/
uint16_t SPI_Data_Get(void)
{
/* Return the data in the SPI_DAT register */
return SPI->DAT;
}
/**
*\*\name SPI_Flag_Status_Get.
*\*\fun Get SPI flag status.
*\*\param spi_flag :
*\*\ - SPI_FLAG_TE
*\*\ - SPI_FLAG_RNE
*\*\ - SPI_FLAG_BUSY
*\*\ - SPI_FLAG_OVER
*\*\ - SPI_FLAG_MODERR
*\*\return SET or RESET
**/
FlagStatus SPI_Flag_Status_Get(uint8_t spi_flag)
{
return (((SPI->STS & spi_flag) == spi_flag) ? SET : RESET);
}
/**
*\*\name SPI_Interrupt_Flag_Status_Get.
*\*\fun Get SPI interrupt flag status.
*\*\param spi_flag :
*\*\ - SPI_INT_FLAG_RNE
*\*\ - SPI_INT_FLAG_TE
*\*\ - SPI_INT_FLAG_MODERR
*\*\ - SPI_INT_FLAG_OVER
*\*\ - SPI_INT_FLAG_ERR
*\*\return SET or RESET
**/
FlagStatus SPI_Interrupt_Flag_Status_Get(uint16_t spi_flag)
{
/* Interrupt flag */
switch (spi_flag)
{
case SPI_INT_FLAG_TE:
if((SPI->CTRL2 & SPI_INT_TE) == SPI_INT_TE && (SPI->STS & SPI_INT_FLAG_TE) == SPI_INT_FLAG_TE)
{
return SET;
}
else
{
return RESET;
}
case SPI_INT_FLAG_RNE:
if((SPI->CTRL2 & SPI_INT_RNE) && (SPI->STS & SPI_INT_FLAG_RNE))
{
return SET;
}
else
{
return RESET;
}
case SPI_INT_FLAG_ERR:
case SPI_INT_FLAG_MODERR:
case SPI_INT_FLAG_OVER:
if((SPI->CTRL2 & SPI_INT_ERR) && (SPI->STS & spi_flag))
{
return SET;
}
else
{
return RESET;
}
default:
return RESET;
}
}
/**
*\*\name SPI_Clear_Flag_Status.
*\*\fun Get SPI flag status.
*\*\param none
*\*\return none
**/
void SPI_OVER_Flag_Clear(void)
{
volatile u8 temp_vlue;
/* read SPI_DAT and SPI_STS to Clear the Flag*/
temp_vlue = SPI->DAT;
temp_vlue = SPI->STS;
}

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/**
* Copyright (c) 2022, Nations Technologies Inc.
*
* All rights reserved.
*
* This software is the exclusive property of Nations Technologies Inc. (Hereinafter
* referred to as NATIONS). This software, and the product of NATIONS described herein
* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties
* of the People's Republic of China and other applicable jurisdictions worldwide.
*
* NATIONS does not grant any license under its patents, copyrights, trademarks, or other
* intellectual property rights. Names and brands of third party may be mentioned or referred
* thereto (if any) for identification purposes only.
*
* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and
* improvements to this software at any time without notice. Please contact NATIONS and obtain
* the latest version of this software before placing orders.
* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes
* no responsibility for the accuracy and reliability of this software.
*
* It is the responsibility of the user of this software to properly design, program, and test
* the functionality and safety of any application made of this information and any resulting product.
* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or
* consequential damages arising in any way out of the use of this software or the Product.
*
* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any
* malfunction or failure of which may cause loss of human life, bodily injury or severe property
* damage. Such applications are deemed, "Insecure Usage".
*
* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS
* harmless from and against all claims, costs, damages, and other liabilities, arising from or related
* to any customer's Insecure Usage.
* Any express or implied warranty with regard to this software or the Product, including,but not
* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement
* are disclaimed to the fullest extent permitted by law.
* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe
* or otherwise distribute this software for any purposes, in whole or in part.
*
* NATIONS products and technologies shall not be used for or incorporated into any products or systems
* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations.
* User shall comply with any applicable export control laws and regulations promulgated and administered by
* the governments of any countries asserting jurisdiction over the parties or transactions.
**/
/**
*\*\file n32g003_uart.c
*\*\author Nations
*\*\version v1.0.0
*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
**/
#include "n32g003_uart.h"
#include "n32g003_rcc.h"
/**
*\*\name UART_Reset
*\*\fun Reset the UARTx registers.
*\*\param UARTx :
*\*\ - UART1
*\*\ - UART2
*\*\return none
**/
void UART_Reset(UART_Module* UARTx)
{
if (UARTx == UART1)
{
/* UART1 Reset */
RCC_Peripheral_Reset(RCC_RST_UART1RST);
}
else if (UARTx == UART2)
{
/* UART2 Reset */
RCC_Peripheral_Reset(RCC_RST_UART2RST);
}
}
/**
*\*\name UART_Initializes
*\*\fun Initializes the UARTx peripheral according to UART_InitStruct .
*\*\param UARTx :
*\*\ - UART1
*\*\ - UART2
*\*\param UART_InitStruct :
*\*\ - buad_rate :
*\*\ - (((buad_rate) > 0) && ((buad_rate) < 0x00337F99))
*\*\ - WordLength
*\*\ - UART_WL_8B
*\*\ - UART_WL_9B
*\*\ - StopBits
*\*\ - UART_STPB_1
*\*\ - UART_STPB_2
*\*\ - Parity
*\*\ - UART_PE_NO
*\*\ - UART_PE_EVEN
*\*\ - UART_PE_ODD
*\*\ - Mode
*\*\ - UART_MODE_RX
*\*\ - UART_MODE_TX
*\*\return none
**/
void UART_Initializes(UART_Module* UARTx, UART_InitType* UART_InitStruct)
{
UART_Baud_Rate_Config(UARTx,UART_InitStruct->BaudRate);
UART_Word_Length_Config(UARTx,UART_InitStruct->WordLength);
UART_Stop_Bits_Config(UARTx,UART_InitStruct->StopBits);
UART_Parity_Config(UARTx,UART_InitStruct->Parity);
UART_Mode_Config(UARTx,UART_InitStruct->Mode);
}
/**
*\*\name UART_Baud_Rate_Config
*\*\fun Configure the baud rate of the UART.
*\*\ The baud rate is computed using the following formula:
*\*\ - IntegerDivider = ((PCLKx) / (16 * (UART_InitStruct->BaudRate)))
*\*\ - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5
*\*\param UARTx :
*\*\ - UART1
*\*\ - UART2
*\*\param buad_rate :
*\*\ - (((buad_rate) > 0) && ((buad_rate) < 0x00337F99))
*\*\return none
**/
void UART_Baud_Rate_Config(UART_Module* UARTx,uint32_t buad_rate)
{
uint32_t temp_value = 0x00, apb_clock_value = 0x00;
uint32_t integer_divider_value = 0x00;
uint32_t fractional_divider_value = 0x00;
RCC_ClocksType RCC_ClocksStatus;
RCC_Clocks_Frequencies_Value_Get(&RCC_ClocksStatus);
apb_clock_value = RCC_ClocksStatus.PclkFreq;
/* Determine the integer part */
integer_divider_value = ((25 * apb_clock_value) / (4 * buad_rate));
temp_value = (integer_divider_value / 100) << 4;
/* Determine the fractional part */
fractional_divider_value = integer_divider_value - (100 * (temp_value >> 4));
/* Implement the fractional part in the register */
temp_value |= ((((fractional_divider_value * 16) + 50) / 100)) & ((uint8_t)0x0F);
/* Write to UART BRR */
UARTx->BRCF = (uint16_t)temp_value;
}
/**
*\*\name UART_Word_Length_Config
*\*\fun Configure the word length of the UART.
*\*\param UARTx :
*\*\ - UART1
*\*\ - UART2
*\*\param word_length :
*\*\ - UART_WL_8B
*\*\ - UART_WL_9B
*\*\return none
**/
void UART_Word_Length_Config(UART_Module* UARTx,uint16_t word_length)
{
uint32_t temp_value = 0x00;
temp_value = UARTx->CTRL1;
/* Clear M bit */
temp_value &= UART_WL_MASK;
/* Configure the UART Word Length */
temp_value |= word_length;
UARTx->CTRL1 = (uint16_t)temp_value;
}
/**
*\*\name UART_Stop_Bits_Config
*\*\fun Configure the stop bits of the UART.
*\*\param UARTx :
*\*\ - UART1
*\*\ - UART2
*\*\param stop_bits :
*\*\ - UART_STPB_1
*\*\ - UART_STPB_2
*\*\return none
**/
void UART_Stop_Bits_Config(UART_Module* UARTx,uint16_t stop_bits)
{
uint32_t temp_value = 0x00;
temp_value = UARTx->CTRL2;
/* Clear STOP[13:12] bits */
temp_value &= CTRL2_STPB_CLR_MASK;
/* Set STOP[13:12] bits according to stop bits value */
temp_value |= stop_bits;
UARTx->CTRL2 = (uint16_t)temp_value;
}
/**
*\*\name UART_Parity_Config
*\*\fun Configure the parity of the UART.
*\*\param UARTx :
*\*\ - UART1
*\*\ - UART2
*\*\param parity :
*\*\ - UART_PE_NO
*\*\ - UART_PE_EVEN
*\*\ - UART_PE_ODD
*\*\return none
**/
void UART_Parity_Config(UART_Module* UARTx,uint16_t parity)
{
uint32_t temp_value = 0x00;
temp_value = UARTx->CTRL1;
/* Clear parity[10:9] bits */
temp_value &= UART_PE_MASK;
/* Configure the UART parity */
temp_value |= parity;
UARTx->CTRL1 = (uint16_t)temp_value;
}
/**
*\*\name UART_Mode_Config
*\*\fun Configure the mode of the UART.
*\*\param UARTx :
*\*\ - UART1
*\*\ - UART2
*\*\param mode :
*\*\ - UART_MODE_RX
*\*\ - UART_MODE_TX
*\*\return none
**/
void UART_Mode_Config(UART_Module* UARTx,uint16_t mode)
{
uint32_t temp_value = 0x00;
temp_value = UARTx->CTRL1;
/* Clear mode[3:2] bits */
temp_value &= UART_MODE_MASK;
/* Configure the UART parity */
temp_value |= mode;
UARTx->CTRL1 = (uint16_t)temp_value;
}
/**
*\*\name UART_Structure_Initializes.
*\*\fun Fills each UART_InitStruct member with its default value.
*\*\param UART_InitStruct :
*\*\ - BaudRate
*\*\ - WordLength
*\*\ - StopBits
*\*\ - Parity
*\*\ - Mode
*\*\ - HardwareFlowControl
*\*\return none
**/
void UART_Structure_Initializes(UART_InitType* UART_InitStruct)
{
/* UART_InitStruct members default value */
UART_InitStruct->BaudRate = 9600;
UART_InitStruct->WordLength = UART_WL_8B;
UART_InitStruct->StopBits = UART_STPB_1;
UART_InitStruct->Parity = UART_PE_NO;
UART_InitStruct->Mode = UART_MODE_RX | UART_MODE_TX;
}
/**
*\*\name UART_Enable.
*\*\fun Enables the specified UART peripheral.
*\*\param UARTx :
*\*\ - UART1
*\*\ - UART2
*\*\return none
**/
void UART_Enable(UART_Module* UARTx)
{
/* Enable the selected UART by setting the UE bit in the CTRL1 register */
UARTx->CTRL1 |= CTRL1_UEN_SET;
}
/**
*\*\name UART_Disable.
*\*\fun Disables the specified UART peripheral.
*\*\param UARTx :
*\*\ - UART1
*\*\ - UART2
*\*\return none
**/
void UART_Disable(UART_Module* UARTx)
{
/* Disable the selected UART by clearing the UE bit in the CTRL1 register */
UARTx->CTRL1 &= CTRL1_UEN_RESET;
}
/**
*\*\name UART_Interrput_Enable.
*\*\fun Enables the specified UART interrupts.
*\*\param UARTx :
*\*\ - UART1
*\*\ - UART2
*\*\param UART_interrupt :
*\*\ - UART_INT_PEF
*\*\ - UART_INT_TXDE
*\*\ - UART_INT_TXC
*\*\ - UART_INT_RXDNE
*\*\ - UART_INT_IDLEF
*\*\return none
**/
void UART_Interrput_Enable(UART_Module* UARTx, uint16_t UART_interrupt)
{
uint32_t register_value = 0x00, interrupt_position = 0x00, temp_value = 0x00;
uint32_t base_value = 0x00;
base_value = (uint32_t)UARTx;
/* Get the UART register index */
register_value = (((uint8_t)UART_interrupt) >> 0x5);
/* Get the interrupt position */
interrupt_position = UART_interrupt & INT_MASK;
temp_value = (((uint32_t)0x01) << interrupt_position);
if (register_value == 0x01) /* The IT is in CTRL1 register */
{
base_value += 0x0C;
}
else if (register_value == 0x02) /* The IT is in CTRL2 register */
{
base_value += 0x10;
}
else /* The IT is in CTRL3 register */
{
base_value += 0x14;
}
*(__IO uint32_t*)base_value |= temp_value;
}
/**
*\*\name UART_Interrput_Disable.
*\*\fun Disables the specified UART interrupts.
*\*\param UARTx :
*\*\ - UART1
*\*\ - UART2
*\*\param UART_interrupt :
*\*\ - UART_INT_PEF
*\*\ - UART_INT_TXDE
*\*\ - UART_INT_TXC
*\*\ - UART_INT_RXDNE
*\*\ - UART_INT_IDLEF
*\*\return none
**/
void UART_Interrput_Disable(UART_Module* UARTx, uint16_t UART_interrupt)
{
uint32_t register_value = 0x00, interrupt_position = 0x00, temp_value = 0x00;
uint32_t base_value = 0x00;
base_value = (uint32_t)UARTx;
/* Get the UART register index */
register_value = (((uint8_t)UART_interrupt) >> 0x5);
/* Get the interrupt position */
interrupt_position = UART_interrupt & INT_MASK;
temp_value = (((uint32_t)0x01) << interrupt_position);
if (register_value == 0x01) /* The IT is in CTRL1 register */
{
base_value += 0x0C;
}
else if (register_value == 0x02) /* The IT is in CTRL2 register */
{
base_value += 0x10;
}
else /* The IT is in CTRL3 register */
{
base_value += 0x14;
}
*(__IO uint32_t*)base_value &= ~temp_value;
}
/**
*\*\name UART_Address_Set.
*\*\fun Sets the address of the UART node.
*\*\param UARTx :
*\*\ - UART1
*\*\ - UART2
*\*\param UART_address :
*\*\ - (((UART_address)>=0x00)&&((UART_address)<0x10))
*\*\return none
**/
void UART_Address_Set(UART_Module* UARTx, uint8_t UART_address)
{
/* Clear the UART address */
UARTx->CTRL2 &= CTRL2_ADDR_MASK;
/* Set the UART address node */
UARTx->CTRL2 |= UART_address;
}
/**
*\*\name UART_WakeUp_Mode_Set.
*\*\fun Selects the UART WakeUp method.
*\*\param UARTx :
*\*\ - UART1
*\*\ - UART2
*\*\param UART_wake_up_mode :
*\*\ - UART_WUM_IDLELINE
*\*\ - UART_WUM_ADDRMASK
*\*\return none
**/
void UART_WakeUp_Mode_Set(UART_Module* UARTx, uint16_t UART_wake_up_mode)
{
UARTx->CTRL1 &= CTRL1_WUM_MASK;
UARTx->CTRL1 |= UART_wake_up_mode;
}
/**
*\*\name UART_Receiver_Wakeup_Enable.
*\*\fun Enable the UART mute mode.
*\*\param UARTx :
*\*\ - UART1
*\*\ - UART2
*\*\return none
**/
void UART_Receiver_Wakeup_Enable(UART_Module* UARTx)
{
/* Enable the UART mute mode by setting the RWU bit in the CTRL1 register */
UARTx->CTRL1 |= CTRL1_RCVWU_SET;
}
/**
*\*\name UART_Receiver_Wakeup_Disable.
*\*\fun Disable the UART mute mode.
*\*\param UARTx :
*\*\ - UART1
*\*\ - UART2
*\*\return none
**/
void UART_Receiver_Wakeup_Disable(UART_Module* UARTx)
{
/* Disable the UART mute mode by clearing the RWU bit in the CTRL1 register */
UARTx->CTRL1 &= CTRL1_RCVWU_RESET;
}
/**
*\*\name UART_Data_Send.
*\*\fun Transmits single data through the UARTx peripheral.
*\*\param UARTx :
*\*\ - UART1
*\*\ - UART2
*\*\param data :
*\*\ - The data to transmit.
*\*\return none
**/
void UART_Data_Send(UART_Module* UARTx, uint16_t data)
{
/* Transmit Data */
UARTx->DAT = (data & (uint16_t)0x01FF);
}
/**
*\*\name UART_Data_Receive.
*\*\fun Returns the most recent received data by the UARTx peripheral.
*\*\param UARTx :
*\*\ - UART1
*\*\ - UART2
*\*\return The received data.
**/
uint16_t UART_Data_Receive(UART_Module* UARTx)
{
/* Receive Data */
return (uint16_t)(UARTx->DAT & (uint16_t)0x01FF);
}
/**
*\*\name UART_Break_Frame_Send.
*\*\fun Transmits break characters.
*\*\param UARTx :
*\*\ - UART1
*\*\ - UART2
*\*\return none
**/
void UART_Break_Frame_Send(UART_Module* UARTx)
{
/* Send break characters */
UARTx->CTRL1 |= CTRL1_SDBRK_SET;
}
/**
*\*\name UART_Half_Duplex_Enable.
*\*\fun Enables the UART's Half Duplex communication.
*\*\param UARTx :
*\*\ - UART1
*\*\ - UART2
*\*\return none
**/
void UART_Half_Duplex_Enable(UART_Module* UARTx)
{
/* Enable the Half-Duplex mode by setting the HDSEL bit in the CTRL3 register */
UARTx->CTRL3 |= CTRL3_HDMEN_SET;
}
/**
*\*\name UART_Half_Duplex_Disable.
*\*\fun Disables the UART's Half Duplex communication.
*\*\param UARTx :
*\*\ - UART1
*\*\ - UART2
*\*\return none
**/
void UART_Half_Duplex_Disable(UART_Module* UARTx)
{
/* Disable the Half-Duplex mode by clearing the HDSEL bit in the CTRL3 register */
UARTx->CTRL3 &= CTRL3_HDMEN_RESET;
}
/**
*\*\name UART_Flag_Status_Get.
*\*\fun Checks whether the specified UART flag is set or not.
*\*\param UARTx :
*\*\ - UART1
*\*\ - UART2
*\*\param UART_flag :
*\*\ - UART_FLAG_TXDE
*\*\ - UART_FLAG_TXC
*\*\ - UART_FLAG_RXDNE
*\*\ - UART_FLAG_IDLEF
*\*\ - UART_FLAG_OREF
*\*\ - UART_FLAG_NEF
*\*\ - UART_FLAG_FEF
*\*\ - UART_FLAG_PEF
*\*\return SET or RESET
**/
FlagStatus UART_Flag_Status_Get(UART_Module* UARTx, uint16_t UART_flag)
{
if ((UARTx->STS & UART_flag) != (uint16_t)RESET)
{
return SET;
}
else
{
return RESET;
}
}
/**
*\*\name UART_Flag_Clear.
*\*\fun Clears the UARTx's pending flags.
*\*\param UARTx :
*\*\ - UART1
*\*\ - UART2
*\*\param UART_flag :
*\*\ - UART_FLAG_TXC
*\*\ - UART_FLAG_RXDNE
*\*\return none
**/
void UART_Flag_Clear(UART_Module* UARTx, uint16_t UART_flag)
{
UARTx->STS = (uint16_t)~UART_flag;
}
/**
*\*\name UART_Interrupt_Status_Get.
*\*\fun Checks whether the specified UART interrupt has occurred or not.
*\*\param UARTx :
*\*\ - UART1
*\*\ - UART2
*\*\param UART_interrupt :
*\*\ - UART_INT_TXDE
*\*\ - UART_INT_TXC
*\*\ - UART_INT_RXDNE
*\*\ - UART_INT_IDLEF
*\*\ - UART_INT_PEF
*\*\ - UART_INT_OREF
*\*\return SET or RESET
**/
ITStatus UART_Interrupt_Status_Get(UART_Module* UARTx, uint16_t UART_interrupt)
{
uint32_t bit_position = 0x00, temp_value = 0x00, register_value = 0x00;
/* Get the UART register index */
register_value = (((uint8_t)UART_interrupt) >> 0x5);
/* Get the interrupt position */
temp_value = UART_interrupt & INT_MASK;
temp_value = (uint32_t)0x01 << temp_value;
if (register_value == 0x01) /* The IT is in CTRL1 register */
{
temp_value &= UARTx->CTRL1;
}
else if (register_value == 0x02) /* The IT is in CTRL2 register */
{
temp_value &= UARTx->CTRL2;
}
else /* The IT is in CTRL3 register */
{
temp_value &= UARTx->CTRL3;
}
bit_position = UART_interrupt >> 0x8;
bit_position = (uint32_t)0x01 << bit_position;
bit_position &= UARTx->STS;
if ((temp_value != (uint16_t)RESET) && (bit_position != (uint16_t)RESET))
{
return SET;
}
else
{
return RESET;
}
}
/**
*\*\name UART_Interrupt_Status_Clear.
*\*\fun Clears the UARTx's interrupt Status.
*\*\param UARTx :
*\*\ - UART1
*\*\ - UART2
*\*\param UART_Interrupt :
*\*\ - UART_INT_TXC
*\*\ - UART_INT_RXDNE
*\*\return none
**/
void UART_Interrupt_Status_Clear(UART_Module* UARTx, uint16_t UART_Interrupt)
{
uint16_t bit_position = 0x00, temp_value = 0x00;
bit_position = UART_Interrupt >> 0x8;
temp_value = ((uint16_t)0x01 << (uint16_t)bit_position);
UARTx->STS = (uint16_t)~temp_value;
}

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/******************************************************************************
* @file main.c
* @brief N32G003F5S7-STB 开发板 闪灯 + 调试串口打印示例
*
* 硬件连接（原理图 N32G003F5S7-STB_V1.0.sch，目标 MCU 为 U1）：
* - 用户灯 D1：PA6(U1.16) -> 跳线 J16 -> D1 -> R1 -> GND，
* PA6 输出高电平点亮（需短接 J16 跳线帽）。
* 可选：D2 接 PA7（跳线 J17）、D3 接 PA10（跳线 J18）。
* - 调试串口（DEBUG USB）：UART1 TX = PA2(U1.6)、RX = PA3(U1.10)，
* 经 J5 跳线（7-8、9-10 短接）连到板载 Nu-Link 虚拟串口。
* 参数：115200，8 数据位，无校验，1 停止位，无流控。
* - 注意：N32G003 没有 DMA 外设，串口发送只能用查询/中断方式，
* 本程序采用查询方式发送。
* 另外 PA8/PA9 与 SWDIO/SWCLK 双键合在同一封装引脚，
* 禁止用作普通 GPIO，否则 SWD 调试会断开。
*
* 功能：主循环翻转 D1 闪烁，同时通过 printf 向调试串口打印
* 循环计数（约每 0.8s 一行）。
*
* 说明：系统时钟初始化 SystemInit() 由启动文件在进入 main 之前
* 自动调用；printf 重定向依赖工程勾选 MicroLIB。
*****************************************************************************/
#include "n32g003.h"
#include <stdio.h>
/* 用户灯 D1 连接的引脚（详见板卡原理图），注意不要用 PA8/PA9（与 SWD 冲突） */
#define LED_PORT GPIOA
#define LED_PIN GPIO_PIN_6
#define LED_CLK RCC_APB_PERIPH_IOPA
/* 调试串口：UART1，TX = PA2，RX = PA3（AF5，见用户手册表 5-7） */
#define UARTx UART1
#define UARTx_CLK RCC_APB_PERIPH_UART1
#define UARTx_GPIO GPIOA
#define UARTx_TX_PIN GPIO_PIN_2
#define UARTx_RX_PIN GPIO_PIN_3
#define UARTx_GPIO_AF GPIO_AF5_UART1
#define UARTx_BAUDRATE 115200u
/* 循环计数器：调试时可在 Watch 窗口观察，确认程序正常运行 */
static volatile uint32_t g_loop_count = 0;
/**
* @brief 简单的软件延时（空指令循环）
* @param n 循环次数（默认 48MHz 主频下约 5000000 ≈ 0.4s，可按需调整）
*/
static void delay_loop(volatile uint32_t n)
{
while (n--) {
__NOP();
}
}
/**
* @brief LED 引脚初始化：开时钟 + 推挽输出
*/
static void led_init(void)
{
GPIO_InitType gpio_init;
RCC_APB_Peripheral_Clock_Enable(LED_CLK);
GPIO_Structure_Initialize(&gpio_init);
gpio_init.Pin = LED_PIN;
gpio_init.GPIO_Mode = GPIO_MODE_OUT_PP; /* 推挽输出 */
gpio_init.GPIO_Pull = GPIO_NO_PULL;
gpio_init.GPIO_Slew_Rate = GPIO_SLEW_RATE_FAST;
gpio_init.GPIO_Alternate = GPIO_NO_AF;
GPIO_Peripheral_Initialize(LED_PORT, &gpio_init);
}
/**
* @brief 调试串口初始化：UART1，PA2(TX)/PA3(RX) 复用 AF5
* 115200，8 数据位，无校验，1 停止位，无流控
*/
static void uart_init(void)
{
GPIO_InitType gpio_init;
UART_InitType uart_init;
/* 开 GPIOA 和 UART1 时钟 */
RCC_APB_Peripheral_Clock_Enable(RCC_APB_PERIPH_IOPA | UARTx_CLK);
/* TX：复用推挽输出 */
GPIO_Structure_Initialize(&gpio_init);
gpio_init.Pin = UARTx_TX_PIN;
gpio_init.GPIO_Mode = GPIO_MODE_AF_PP;
gpio_init.GPIO_Alternate = UARTx_GPIO_AF;
GPIO_Peripheral_Initialize(UARTx_GPIO, &gpio_init);
/* RX：复用输入 */
gpio_init.Pin = UARTx_RX_PIN;
gpio_init.GPIO_Mode = GPIO_MODE_INPUT;
gpio_init.GPIO_Alternate = UARTx_GPIO_AF;
GPIO_Peripheral_Initialize(UARTx_GPIO, &gpio_init);
uart_init.BaudRate = UARTx_BAUDRATE;
uart_init.WordLength = UART_WL_8B;
uart_init.StopBits = UART_STPB_1;
uart_init.Parity = UART_PE_NO;
uart_init.Mode = UART_MODE_RX | UART_MODE_TX;
UART_Initializes(UARTx, &uart_init);
UART_Enable(UARTx);
}
/**
* @brief 重定向 printf 到调试串口（查询方式发送，需勾选 MicroLIB）
*/
int fputc(int ch, FILE *f)
{
(void)f;
UART_Data_Send(UARTx, (uint8_t)ch);
while (UART_Flag_Status_Get(UARTx, UART_FLAG_TXDE) == RESET) {
}
return ch;
}
/**
* @brief 主函数
*/
int main(void)
{
led_init();
uart_init();
printf("\r\nN32G003F5S7-STB: LED blink + UART printf demo\r\n");
while (1) {
GPIO_Pin_Toggle(LED_PORT, LED_PIN); /* 翻转 LED */
g_loop_count++; /* 观察点：递增说明 CPU 正在运行 */
printf("loop count = %u\r\n", (unsigned int)g_loop_count);
delay_loop(5000000u);
}
}

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Component: ARM Compiler 6.14 Tool: armlink [5db06800]
==============================================================================
Section Cross References
main.o(.text.main) refers to main.o(.text.delay_loop) for delay_loop
main.o(.text.main) refers to main.o(.bss.g_loop_count) for [Anonymous Symbol]
main.o(.ARM.exidx.text.main) refers to main.o(.text.main) for [Anonymous Symbol]
main.o(.ARM.exidx.text.delay_loop) refers to main.o(.text.delay_loop) for [Anonymous Symbol]
system_n32g003.o(.text.System_Initializes) refers to system_n32g003.o(.text.System_Clock_Set) for System_Clock_Set
system_n32g003.o(.ARM.exidx.text.System_Initializes) refers to system_n32g003.o(.text.System_Initializes) for [Anonymous Symbol]
system_n32g003.o(.text.System_Clock_Set) refers to system_n32g003.o(.text.Systeminit_Flash_Latency_Set) for Systeminit_Flash_Latency_Set
system_n32g003.o(.text.System_Clock_Set) refers to n32g003_rcc.o(.text.RCC_Sysclk_Config) for RCC_Sysclk_Config
system_n32g003.o(.ARM.exidx.text.System_Clock_Set) refers to system_n32g003.o(.text.System_Clock_Set) for [Anonymous Symbol]
system_n32g003.o(.text.System_Core_Clock_Frequency_Update) refers to aeabi_sdivfast.o(.text_divfast) for __aeabi_uidiv
system_n32g003.o(.text.System_Core_Clock_Frequency_Update) refers to system_n32g003.o(.data.SystemCoreClockFrequency) for SystemCoreClockFrequency
system_n32g003.o(.text.System_Core_Clock_Frequency_Update) refers to system_n32g003.o(.rodata.AHBPrescTable) for AHBPrescTable
system_n32g003.o(.ARM.exidx.text.System_Core_Clock_Frequency_Update) refers to system_n32g003.o(.text.System_Core_Clock_Frequency_Update) for [Anonymous Symbol]
system_n32g003.o(.ARM.exidx.text.Systeminit_Flash_Latency_Set) refers to system_n32g003.o(.text.Systeminit_Flash_Latency_Set) for [Anonymous Symbol]
n32g003_rcc.o(.ARM.exidx.text.RCC_Reset) refers to n32g003_rcc.o(.text.RCC_Reset) for [Anonymous Symbol]
n32g003_rcc.o(.ARM.exidx.text.RCC_HSI_Calibration_Value_Set) refers to n32g003_rcc.o(.text.RCC_HSI_Calibration_Value_Set) for [Anonymous Symbol]
n32g003_rcc.o(.ARM.exidx.text.RCC_LSI_Calibration_Value_Set) refers to n32g003_rcc.o(.text.RCC_LSI_Calibration_Value_Set) for [Anonymous Symbol]
n32g003_rcc.o(.ARM.exidx.text.RCC_Sysclk_Config) refers to n32g003_rcc.o(.text.RCC_Sysclk_Config) for [Anonymous Symbol]
n32g003_rcc.o(.ARM.exidx.text.RCC_Hclk_Config) refers to n32g003_rcc.o(.text.RCC_Hclk_Config) for [Anonymous Symbol]
n32g003_rcc.o(.ARM.exidx.text.RCC_Pclk_Config) refers to n32g003_rcc.o(.text.RCC_Pclk_Config) for [Anonymous Symbol]
n32g003_rcc.o(.ARM.exidx.text.RCC_TIM1_Clock_Config) refers to n32g003_rcc.o(.text.RCC_TIM1_Clock_Config) for [Anonymous Symbol]
n32g003_rcc.o(.ARM.exidx.text.RCC_ADC_1M_Clock_Config) refers to n32g003_rcc.o(.text.RCC_ADC_1M_Clock_Config) for [Anonymous Symbol]
n32g003_rcc.o(.ARM.exidx.text.RCC_ADC_Clock_Config) refers to n32g003_rcc.o(.text.RCC_ADC_Clock_Config) for [Anonymous Symbol]
n32g003_rcc.o(.ARM.exidx.text.RCC_TIM6_Clock_Config) refers to n32g003_rcc.o(.text.RCC_TIM6_Clock_Config) for [Anonymous Symbol]
n32g003_rcc.o(.text.RCC_Clocks_Frequencies_Value_Get) refers to aeabi_sdivfast.o(.text_divfast) for __aeabi_uidiv
n32g003_rcc.o(.text.RCC_Clocks_Frequencies_Value_Get) refers to n32g003_rcc.o(.rodata.ADCCLKPresTable) for [Anonymous Symbol]
n32g003_rcc.o(.text.RCC_Clocks_Frequencies_Value_Get) refers to n32g003_rcc.o(.rodata.ADC1MCLKPresTable) for [Anonymous Symbol]
n32g003_rcc.o(.text.RCC_Clocks_Frequencies_Value_Get) refers to n32g003_rcc.o(.rodata.AHBPresTable) for [Anonymous Symbol]
n32g003_rcc.o(.text.RCC_Clocks_Frequencies_Value_Get) refers to n32g003_rcc.o(.rodata.APBPresTable) for [Anonymous Symbol]
n32g003_rcc.o(.ARM.exidx.text.RCC_Clocks_Frequencies_Value_Get) refers to n32g003_rcc.o(.text.RCC_Clocks_Frequencies_Value_Get) for [Anonymous Symbol]
n32g003_rcc.o(.ARM.exidx.text.RCC_AHB_Peripheral_Clock_Enable) refers to n32g003_rcc.o(.text.RCC_AHB_Peripheral_Clock_Enable) for [Anonymous Symbol]
n32g003_rcc.o(.ARM.exidx.text.RCC_AHB_Peripheral_Clock_Disable) refers to n32g003_rcc.o(.text.RCC_AHB_Peripheral_Clock_Disable) for [Anonymous Symbol]
n32g003_rcc.o(.ARM.exidx.text.RCC_APB_Peripheral_Clock_Enable) refers to n32g003_rcc.o(.text.RCC_APB_Peripheral_Clock_Enable) for [Anonymous Symbol]
n32g003_rcc.o(.ARM.exidx.text.RCC_APB_Peripheral_Clock_Disable) refers to n32g003_rcc.o(.text.RCC_APB_Peripheral_Clock_Disable) for [Anonymous Symbol]
n32g003_rcc.o(.ARM.exidx.text.RCC_Peripheral_Reset) refers to n32g003_rcc.o(.text.RCC_Peripheral_Reset) for [Anonymous Symbol]
n32g003_rcc.o(.ARM.exidx.text.RCC_MCO_Prescaler_Config) refers to n32g003_rcc.o(.text.RCC_MCO_Prescaler_Config) for [Anonymous Symbol]
n32g003_rcc.o(.ARM.exidx.text.RCC_MCO_Source_Config) refers to n32g003_rcc.o(.text.RCC_MCO_Source_Config) for [Anonymous Symbol]
n32g003_rcc.o(.ARM.exidx.text.RCC_Flag_Status_Get) refers to n32g003_rcc.o(.text.RCC_Flag_Status_Get) for [Anonymous Symbol]
n32g003_rcc.o(.ARM.exidx.text.RCC_Reset_Flag_Clear) refers to n32g003_rcc.o(.text.RCC_Reset_Flag_Clear) for [Anonymous Symbol]
n32g003_rcc.o(.ARM.exidx.text.RCC_EMC_Reset_Disable) refers to n32g003_rcc.o(.text.RCC_EMC_Reset_Disable) for [Anonymous Symbol]
n32g003_rcc.o(.ARM.exidx.text.RCC_EMC_Reset_Enable) refers to n32g003_rcc.o(.text.RCC_EMC_Reset_Enable) for [Anonymous Symbol]
n32g003_rcc.o(.ARM.exidx.text.RCC_EMC_Detect_Disable) refers to n32g003_rcc.o(.text.RCC_EMC_Detect_Disable) for [Anonymous Symbol]
n32g003_rcc.o(.ARM.exidx.text.RCC_EMC_Detect_Enable) refers to n32g003_rcc.o(.text.RCC_EMC_Detect_Enable) for [Anonymous Symbol]
n32g003_rcc.o(.ARM.exidx.text.RCC_LSI_Detect_Disable) refers to n32g003_rcc.o(.text.RCC_LSI_Detect_Disable) for [Anonymous Symbol]
n32g003_rcc.o(.ARM.exidx.text.RCC_LSI_Detect_Enable) refers to n32g003_rcc.o(.text.RCC_LSI_Detect_Enable) for [Anonymous Symbol]
n32g003_rcc.o(.ARM.exidx.text.RCC_LSI_Clocks_Frequencies_Get) refers to n32g003_rcc.o(.text.RCC_LSI_Clocks_Frequencies_Get) for [Anonymous Symbol]
startup_n32g003.o(STACK) refers (Special) to heapauxi.o(.text) for __use_two_region_memory
startup_n32g003.o(HEAP) refers (Special) to heapauxi.o(.text) for __use_two_region_memory
startup_n32g003.o(RESET) refers (Special) to heapauxi.o(.text) for __use_two_region_memory
startup_n32g003.o(RESET) refers to startup_n32g003.o(STACK) for __initial_sp
startup_n32g003.o(RESET) refers to startup_n32g003.o(.text) for Reset_Handler
startup_n32g003.o(.text) refers (Special) to heapauxi.o(.text) for __use_two_region_memory
startup_n32g003.o(.text) refers to system_n32g003.o(.text.System_Initializes) for System_Initializes
startup_n32g003.o(.text) refers to __main.o(!!!main) for __main
startup_n32g003.o(.text) refers to startup_n32g003.o(HEAP) for Heap_Mem
startup_n32g003.o(.text) refers to startup_n32g003.o(STACK) for Stack_Mem
__main.o(!!!main) refers to __rtentry.o(.ARM.Collect$$rtentry$$00000000) for __rt_entry
__rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) for __rt_entry_li
__rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) for __rt_entry_main
__rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000C) for __rt_entry_postli_1
__rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$00000009) for __rt_entry_postsh_1
__rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$00000002) for __rt_entry_presh_1
__rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry4.o(.ARM.Collect$$rtentry$$00000004) for __rt_entry_sh
aeabi_idiv0_sigfpe.o(.text) refers to rt_div0.o(.text) for __rt_div0
__rtentry2.o(.ARM.Collect$$rtentry$$00000008) refers to boardinit2.o(.text) for _platform_post_stackheap_init
__rtentry2.o(.ARM.Collect$$rtentry$$0000000A) refers to libinit.o(.ARM.Collect$$libinit$$00000000) for __rt_lib_init
__rtentry2.o(.ARM.Collect$$rtentry$$0000000B) refers to boardinit3.o(.text) for _platform_post_lib_init
__rtentry2.o(.ARM.Collect$$rtentry$$0000000D) refers to main.o(.text.main) for main
__rtentry2.o(.ARM.Collect$$rtentry$$0000000D) refers to exit.o(.text) for exit
__rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$00000001) for .ARM.Collect$$rtentry$$00000001
__rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$00000008) for .ARM.Collect$$rtentry$$00000008
__rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) for .ARM.Collect$$rtentry$$0000000A
__rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000B) for .ARM.Collect$$rtentry$$0000000B
__rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) for .ARM.Collect$$rtentry$$0000000D
__rtentry4.o(.ARM.Collect$$rtentry$$00000004) refers to sys_stackheap_outer.o(.text) for __user_setup_stackheap
__rtentry4.o(.ARM.exidx) refers to __rtentry4.o(.ARM.Collect$$rtentry$$00000004) for .ARM.Collect$$rtentry$$00000004
rt_div0.o(.text) refers to defsig_fpe_outer.o(.text) for __rt_SIGFPE
sys_stackheap_outer.o(.text) refers to libspace.o(.text) for __user_perproc_libspace
sys_stackheap_outer.o(.text) refers to startup_n32g003.o(.text) for __user_initial_stackheap
sys_stackheap_outer.o(__vectab_stack_and_reset_area) refers to tempstk.o(.text) for __temporary_stack_top
sys_stackheap_outer.o(__vectab_stack_and_reset_area) refers to __main.o(!!!main) for __main
exit.o(.text) refers to rtexit.o(.ARM.Collect$$rtexit$$00000000) for __rt_exit
defsig_fpe_outer.o(.text) refers to defsig_fpe_inner.o(.text) for __rt_SIGFPE_inner
defsig_fpe_outer.o(.text) refers to defsig_exit.o(.text) for __sig_exit
defsig_fpe_formal.o(.text) refers to rt_raise.o(.text) for __rt_raise
libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000002E) for __rt_lib_init_alloca_1
libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000002C) for __rt_lib_init_argv_1
libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001B) for __rt_lib_init_atexit_1
libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000021) for __rt_lib_init_clock_1
libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000032) for __rt_lib_init_cpp_1
libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000030) for __rt_lib_init_exceptions_1
libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000002) for __rt_lib_init_fp_1
libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001F) for __rt_lib_init_fp_trap_1
libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000023) for __rt_lib_init_getenv_1
libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000A) for __rt_lib_init_heap_1
libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000011) for __rt_lib_init_lc_collate_1
libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000013) for __rt_lib_init_lc_ctype_1
libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000015) for __rt_lib_init_lc_monetary_1
libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000017) for __rt_lib_init_lc_numeric_1
libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000019) for __rt_lib_init_lc_time_1
libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000004) for __rt_lib_init_preinit_1
libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000E) for __rt_lib_init_rand_1
libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000033) for __rt_lib_init_return
libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001D) for __rt_lib_init_signal_1
libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000025) for __rt_lib_init_stdio_1
libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000C) for __rt_lib_init_user_alloc_1
libspace.o(.text) refers to libspace.o(.bss) for __libspace_start
rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for __rt_exit_exit
rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for __rt_exit_ls
rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000002) for __rt_exit_prels_1
rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for __rt_exit_exit
rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for __rt_exit_ls
rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000002) for __rt_exit_prels_1
rtexit.o(.ARM.exidx) refers to rtexit.o(.ARM.Collect$$rtexit$$00000000) for .ARM.Collect$$rtexit$$00000000
rt_raise.o(.text) refers to __raise.o(.text) for __raise
rt_raise.o(.text) refers to sys_exit.o(.text) for _sys_exit
defsig_exit.o(.text) refers to sys_exit.o(.text) for _sys_exit
defsig_fpe_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display
libinit2.o(.ARM.Collect$$libinit$$00000010) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F
libinit2.o(.ARM.Collect$$libinit$$00000012) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F
libinit2.o(.ARM.Collect$$libinit$$00000014) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F
libinit2.o(.ARM.Collect$$libinit$$00000016) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F
libinit2.o(.ARM.Collect$$libinit$$00000018) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F
libinit2.o(.ARM.Collect$$libinit$$00000026) refers to argv_veneer.o(.text) for __ARM_argv_veneer
libinit2.o(.ARM.Collect$$libinit$$00000027) refers to argv_veneer.o(.text) for __ARM_argv_veneer
sys_exit.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting
sys_exit.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function
sys_exit_hlt.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting
sys_exit_hlt.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function
rtexit2.o(.ARM.Collect$$rtexit$$00000003) refers to libshutdown.o(.ARM.Collect$$libshutdown$$00000000) for __rt_lib_shutdown
rtexit2.o(.ARM.Collect$$rtexit$$00000004) refers to sys_exit.o(.text) for _sys_exit
rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000001) for .ARM.Collect$$rtexit$$00000001
rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for .ARM.Collect$$rtexit$$00000003
rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for .ARM.Collect$$rtexit$$00000004
__raise.o(.text) refers to defsig.o(CL$$defsig) for __default_signal_handler
defsig_general.o(.text) refers to sys_wrch.o(.text) for _ttywrch
sys_wrch.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting
sys_wrch.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function
sys_wrch_hlt.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting
sys_wrch_hlt.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function
defsig.o(CL$$defsig) refers to defsig_fpe_inner.o(.text) for __rt_SIGFPE_inner
defsig.o(CL$$defsig) refers to defsig_rtmem_inner.o(.text) for __rt_SIGRTMEM_inner
_get_argv_nomalloc.o(.text) refers (Special) to hrguard.o(.text) for __heap_region$guard
_get_argv_nomalloc.o(.text) refers to defsig_rtmem_outer.o(.text) for __rt_SIGRTMEM
_get_argv_nomalloc.o(.text) refers to sys_command.o(.text) for _sys_command_string
libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000002) for __rt_lib_shutdown_cpp_1
libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000007) for __rt_lib_shutdown_fp_trap_1
libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000F) for __rt_lib_shutdown_heap_1
libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000010) for __rt_lib_shutdown_return
libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000A) for __rt_lib_shutdown_signal_1
libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000004) for __rt_lib_shutdown_stdio_1
libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C) for __rt_lib_shutdown_user_alloc_1
sys_command.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting
sys_command.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function
sys_command_hlt.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting
sys_command_hlt.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function
defsig_abrt_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display
defsig_rtred_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display
defsig_rtmem_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display
defsig_rtmem_outer.o(.text) refers to defsig_rtmem_inner.o(.text) for __rt_SIGRTMEM_inner
defsig_rtmem_outer.o(.text) refers to defsig_exit.o(.text) for __sig_exit
defsig_rtmem_formal.o(.text) refers to rt_raise.o(.text) for __rt_raise
defsig_stak_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display
defsig_pvfn_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display
defsig_cppl_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display
defsig_segv_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display
defsig_other.o(.text) refers to defsig_general.o(.text) for __default_signal_display
==============================================================================
Removing Unused input sections from the image.
Removing main.o(.text), (0 bytes).
Removing main.o(.ARM.exidx.text.main), (8 bytes).
Removing main.o(.ARM.exidx.text.delay_loop), (8 bytes).
Removing main.o(.ARM.use_no_argv), (4 bytes).
Removing system_n32g003.o(.text), (0 bytes).
Removing system_n32g003.o(.ARM.exidx.text.System_Initializes), (8 bytes).
Removing system_n32g003.o(.ARM.exidx.text.System_Clock_Set), (8 bytes).
Removing system_n32g003.o(.text.System_Core_Clock_Frequency_Update), (116 bytes).
Removing system_n32g003.o(.ARM.exidx.text.System_Core_Clock_Frequency_Update), (8 bytes).
Removing system_n32g003.o(.ARM.exidx.text.Systeminit_Flash_Latency_Set), (8 bytes).
Removing system_n32g003.o(.data.SystemCoreClockFrequency), (4 bytes).
Removing system_n32g003.o(.rodata.AHBPrescTable), (16 bytes).
Removing n32g003_rcc.o(.text), (0 bytes).
Removing n32g003_rcc.o(.text.RCC_Reset), (64 bytes).
Removing n32g003_rcc.o(.ARM.exidx.text.RCC_Reset), (8 bytes).
Removing n32g003_rcc.o(.text.RCC_HSI_Calibration_Value_Set), (20 bytes).
Removing n32g003_rcc.o(.ARM.exidx.text.RCC_HSI_Calibration_Value_Set), (8 bytes).
Removing n32g003_rcc.o(.text.RCC_LSI_Calibration_Value_Set), (20 bytes).
Removing n32g003_rcc.o(.ARM.exidx.text.RCC_LSI_Calibration_Value_Set), (8 bytes).
Removing n32g003_rcc.o(.ARM.exidx.text.RCC_Sysclk_Config), (8 bytes).
Removing n32g003_rcc.o(.text.RCC_Hclk_Config), (20 bytes).
Removing n32g003_rcc.o(.ARM.exidx.text.RCC_Hclk_Config), (8 bytes).
Removing n32g003_rcc.o(.text.RCC_Pclk_Config), (20 bytes).
Removing n32g003_rcc.o(.ARM.exidx.text.RCC_Pclk_Config), (8 bytes).
Removing n32g003_rcc.o(.text.RCC_TIM1_Clock_Config), (20 bytes).
Removing n32g003_rcc.o(.ARM.exidx.text.RCC_TIM1_Clock_Config), (8 bytes).
Removing n32g003_rcc.o(.text.RCC_ADC_1M_Clock_Config), (20 bytes).
Removing n32g003_rcc.o(.ARM.exidx.text.RCC_ADC_1M_Clock_Config), (8 bytes).
Removing n32g003_rcc.o(.text.RCC_ADC_Clock_Config), (20 bytes).
Removing n32g003_rcc.o(.ARM.exidx.text.RCC_ADC_Clock_Config), (8 bytes).
Removing n32g003_rcc.o(.text.RCC_TIM6_Clock_Config), (20 bytes).
Removing n32g003_rcc.o(.ARM.exidx.text.RCC_TIM6_Clock_Config), (8 bytes).
Removing n32g003_rcc.o(.text.RCC_Clocks_Frequencies_Value_Get), (200 bytes).
Removing n32g003_rcc.o(.ARM.exidx.text.RCC_Clocks_Frequencies_Value_Get), (8 bytes).
Removing n32g003_rcc.o(.text.RCC_AHB_Peripheral_Clock_Enable), (16 bytes).
Removing n32g003_rcc.o(.ARM.exidx.text.RCC_AHB_Peripheral_Clock_Enable), (8 bytes).
Removing n32g003_rcc.o(.text.RCC_AHB_Peripheral_Clock_Disable), (16 bytes).
Removing n32g003_rcc.o(.ARM.exidx.text.RCC_AHB_Peripheral_Clock_Disable), (8 bytes).
Removing n32g003_rcc.o(.text.RCC_APB_Peripheral_Clock_Enable), (16 bytes).
Removing n32g003_rcc.o(.ARM.exidx.text.RCC_APB_Peripheral_Clock_Enable), (8 bytes).
Removing n32g003_rcc.o(.text.RCC_APB_Peripheral_Clock_Disable), (16 bytes).
Removing n32g003_rcc.o(.ARM.exidx.text.RCC_APB_Peripheral_Clock_Disable), (8 bytes).
Removing n32g003_rcc.o(.text.RCC_Peripheral_Reset), (20 bytes).
Removing n32g003_rcc.o(.ARM.exidx.text.RCC_Peripheral_Reset), (8 bytes).
Removing n32g003_rcc.o(.text.RCC_MCO_Prescaler_Config), (20 bytes).
Removing n32g003_rcc.o(.ARM.exidx.text.RCC_MCO_Prescaler_Config), (8 bytes).
Removing n32g003_rcc.o(.text.RCC_MCO_Source_Config), (20 bytes).
Removing n32g003_rcc.o(.ARM.exidx.text.RCC_MCO_Source_Config), (8 bytes).
Removing n32g003_rcc.o(.text.RCC_Flag_Status_Get), (36 bytes).
Removing n32g003_rcc.o(.ARM.exidx.text.RCC_Flag_Status_Get), (8 bytes).
Removing n32g003_rcc.o(.text.RCC_Reset_Flag_Clear), (24 bytes).
Removing n32g003_rcc.o(.ARM.exidx.text.RCC_Reset_Flag_Clear), (8 bytes).
Removing n32g003_rcc.o(.text.RCC_EMC_Reset_Disable), (20 bytes).
Removing n32g003_rcc.o(.ARM.exidx.text.RCC_EMC_Reset_Disable), (8 bytes).
Removing n32g003_rcc.o(.text.RCC_EMC_Reset_Enable), (20 bytes).
Removing n32g003_rcc.o(.ARM.exidx.text.RCC_EMC_Reset_Enable), (8 bytes).
Removing n32g003_rcc.o(.text.RCC_EMC_Detect_Disable), (16 bytes).
Removing n32g003_rcc.o(.ARM.exidx.text.RCC_EMC_Detect_Disable), (8 bytes).
Removing n32g003_rcc.o(.text.RCC_EMC_Detect_Enable), (16 bytes).
Removing n32g003_rcc.o(.ARM.exidx.text.RCC_EMC_Detect_Enable), (8 bytes).
Removing n32g003_rcc.o(.text.RCC_LSI_Detect_Disable), (16 bytes).
Removing n32g003_rcc.o(.ARM.exidx.text.RCC_LSI_Detect_Disable), (8 bytes).
Removing n32g003_rcc.o(.text.RCC_LSI_Detect_Enable), (16 bytes).
Removing n32g003_rcc.o(.ARM.exidx.text.RCC_LSI_Detect_Enable), (8 bytes).
Removing n32g003_rcc.o(.text.RCC_LSI_Clocks_Frequencies_Get), (16 bytes).
Removing n32g003_rcc.o(.ARM.exidx.text.RCC_LSI_Clocks_Frequencies_Get), (8 bytes).
Removing n32g003_rcc.o(.rodata.ADCCLKPresTable), (16 bytes).
Removing n32g003_rcc.o(.rodata.ADC1MCLKPresTable), (4 bytes).
Removing n32g003_rcc.o(.rodata.AHBPresTable), (16 bytes).
Removing n32g003_rcc.o(.rodata.APBPresTable), (8 bytes).
70 unused section(s) (total 1176 bytes) removed from the image.
==============================================================================
Image Symbol Table
Local Symbols
Symbol Name Value Ov Type Size Object(Section)
../clib/angel/boardlib.s 0x00000000 Number 0 boardinit1.o ABSOLUTE
../clib/angel/boardlib.s 0x00000000 Number 0 boardinit2.o ABSOLUTE
../clib/angel/boardlib.s 0x00000000 Number 0 boardinit3.o ABSOLUTE
../clib/angel/boardlib.s 0x00000000 Number 0 boardshut.o ABSOLUTE
../clib/angel/handlers.s 0x00000000 Number 0 __scatter_zi.o ABSOLUTE
../clib/angel/kernel.s 0x00000000 Number 0 __rtentry.o ABSOLUTE
../clib/angel/kernel.s 0x00000000 Number 0 __rtentry2.o ABSOLUTE
../clib/angel/kernel.s 0x00000000 Number 0 __rtentry4.o ABSOLUTE
../clib/angel/kernel.s 0x00000000 Number 0 rtexit.o ABSOLUTE
../clib/angel/kernel.s 0x00000000 Number 0 rtexit2.o ABSOLUTE
../clib/angel/rt.s 0x00000000 Number 0 aeabi_idiv0.o ABSOLUTE
../clib/angel/rt.s 0x00000000 Number 0 aeabi_idiv0_sigfpe.o ABSOLUTE
../clib/angel/rt.s 0x00000000 Number 0 rt_div0.o ABSOLUTE
../clib/angel/rt.s 0x00000000 Number 0 rt_raise.o ABSOLUTE
../clib/angel/scatterp.s 0x00000000 Number 0 __scatter.o ABSOLUTE
../clib/angel/startup.s 0x00000000 Number 0 __main.o ABSOLUTE
../clib/angel/sys.s 0x00000000 Number 0 sys_stackheap_outer.o ABSOLUTE
../clib/angel/sys.s 0x00000000 Number 0 libspace.o ABSOLUTE
../clib/angel/sys.s 0x00000000 Number 0 tempstk.o ABSOLUTE
../clib/angel/sys.s 0x00000000 Number 0 use_no_semi.o ABSOLUTE
../clib/angel/sys.s 0x00000000 Number 0 indicate_semi.o ABSOLUTE
../clib/angel/sysapp.c 0x00000000 Number 0 sys_exit.o ABSOLUTE
../clib/angel/sysapp.c 0x00000000 Number 0 sys_exit_hlt.o ABSOLUTE
../clib/angel/sysapp.c 0x00000000 Number 0 sys_wrch.o ABSOLUTE
../clib/angel/sysapp.c 0x00000000 Number 0 sys_wrch_hlt.o ABSOLUTE
../clib/angel/sysapp.c 0x00000000 Number 0 sys_command.o ABSOLUTE
../clib/angel/sysapp.c 0x00000000 Number 0 sys_command_hlt.o ABSOLUTE
../clib/armsys.c 0x00000000 Number 0 argv_veneer.o ABSOLUTE
../clib/armsys.c 0x00000000 Number 0 _get_argv_nomalloc.o ABSOLUTE
../clib/armsys.c 0x00000000 Number 0 no_argv.o ABSOLUTE
../clib/division.s 0x00000000 Number 0 aeabi_sdivfast.o ABSOLUTE
../clib/division.s 0x00000000 Number 0 aeabi_sdivfast_div0.o ABSOLUTE
../clib/heapalloc.c 0x00000000 Number 0 hrguard.o ABSOLUTE
../clib/heapaux.c 0x00000000 Number 0 heapauxi.o ABSOLUTE
../clib/libinit.s 0x00000000 Number 0 libinit.o ABSOLUTE
../clib/libinit.s 0x00000000 Number 0 libinit2.o ABSOLUTE
../clib/libinit.s 0x00000000 Number 0 libshutdown.o ABSOLUTE
../clib/libinit.s 0x00000000 Number 0 libshutdown2.o ABSOLUTE
../clib/signal.c 0x00000000 Number 0 defsig_fpe_outer.o ABSOLUTE
../clib/signal.c 0x00000000 Number 0 defsig_fpe_formal.o ABSOLUTE
../clib/signal.c 0x00000000 Number 0 defsig_exit.o ABSOLUTE
../clib/signal.c 0x00000000 Number 0 defsig_fpe_inner.o ABSOLUTE
../clib/signal.c 0x00000000 Number 0 __raise.o ABSOLUTE
../clib/signal.c 0x00000000 Number 0 defsig_general.o ABSOLUTE
../clib/signal.c 0x00000000 Number 0 defsig_abrt_inner.o ABSOLUTE
../clib/signal.c 0x00000000 Number 0 defsig_rtred_inner.o ABSOLUTE
../clib/signal.c 0x00000000 Number 0 defsig_rtmem_inner.o ABSOLUTE
../clib/signal.c 0x00000000 Number 0 defsig_rtmem_outer.o ABSOLUTE
../clib/signal.c 0x00000000 Number 0 defsig_rtmem_formal.o ABSOLUTE
../clib/signal.c 0x00000000 Number 0 defsig_stak_inner.o ABSOLUTE
../clib/signal.c 0x00000000 Number 0 defsig_pvfn_inner.o ABSOLUTE
../clib/signal.c 0x00000000 Number 0 defsig_cppl_inner.o ABSOLUTE
../clib/signal.c 0x00000000 Number 0 defsig_segv_inner.o ABSOLUTE
../clib/signal.c 0x00000000 Number 0 defsig_other.o ABSOLUTE
../clib/signal.s 0x00000000 Number 0 defsig.o ABSOLUTE
../clib/stdlib.c 0x00000000 Number 0 exit.o ABSOLUTE
../fplib/cfplib/fpinit.c 0x00000000 Number 0 fpinit.o ABSOLUTE
dc.s 0x00000000 Number 0 dc.o ABSOLUTE
firmware/CMSIS/device/startup/startup_n32g003.s 0x00000000 Number 0 startup_n32g003.o ABSOLUTE
main.c 0x00000000 Number 0 main.o ABSOLUTE
n32g003_rcc.c 0x00000000 Number 0 n32g003_rcc.o ABSOLUTE
system_n32g003.c 0x00000000 Number 0 system_n32g003.o ABSOLUTE
RESET 0x08000000 Section 128 startup_n32g003.o(RESET)
!!!main 0x08000080 Section 8 __main.o(!!!main)
!!!scatter 0x08000088 Section 60 __scatter.o(!!!scatter)
!!handler_zi 0x080000c4 Section 28 __scatter_zi.o(!!handler_zi)
.ARM.Collect$$libinit$$00000000 0x080000e0 Section 2 libinit.o(.ARM.Collect$$libinit$$00000000)
.ARM.Collect$$libinit$$00000002 0x080000e2 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000002)
.ARM.Collect$$libinit$$00000004 0x080000e2 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000004)
.ARM.Collect$$libinit$$0000000A 0x080000e2 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000000A)
.ARM.Collect$$libinit$$0000000C 0x080000e2 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000000C)
.ARM.Collect$$libinit$$0000000E 0x080000e2 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000000E)
.ARM.Collect$$libinit$$00000011 0x080000e2 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000011)
.ARM.Collect$$libinit$$00000013 0x080000e2 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000013)
.ARM.Collect$$libinit$$00000015 0x080000e2 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000015)
.ARM.Collect$$libinit$$00000017 0x080000e2 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000017)
.ARM.Collect$$libinit$$00000019 0x080000e2 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000019)
.ARM.Collect$$libinit$$0000001B 0x080000e2 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000001B)
.ARM.Collect$$libinit$$0000001D 0x080000e2 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000001D)
.ARM.Collect$$libinit$$0000001F 0x080000e2 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000001F)
.ARM.Collect$$libinit$$00000021 0x080000e2 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000021)
.ARM.Collect$$libinit$$00000023 0x080000e2 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000023)
.ARM.Collect$$libinit$$00000025 0x080000e2 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000025)
.ARM.Collect$$libinit$$0000002C 0x080000e2 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000002C)
.ARM.Collect$$libinit$$0000002E 0x080000e2 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000002E)
.ARM.Collect$$libinit$$00000030 0x080000e2 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000030)
.ARM.Collect$$libinit$$00000032 0x080000e2 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000032)
.ARM.Collect$$libinit$$00000033 0x080000e2 Section 2 libinit2.o(.ARM.Collect$$libinit$$00000033)
.ARM.Collect$$libshutdown$$00000000 0x080000e4 Section 2 libshutdown.o(.ARM.Collect$$libshutdown$$00000000)
.ARM.Collect$$libshutdown$$00000002 0x080000e6 Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000002)
.ARM.Collect$$libshutdown$$00000004 0x080000e6 Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000004)
.ARM.Collect$$libshutdown$$00000007 0x080000e6 Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000007)
.ARM.Collect$$libshutdown$$0000000A 0x080000e6 Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000A)
.ARM.Collect$$libshutdown$$0000000C 0x080000e6 Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C)
.ARM.Collect$$libshutdown$$0000000F 0x080000e6 Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000F)
.ARM.Collect$$libshutdown$$00000010 0x080000e6 Section 2 libshutdown2.o(.ARM.Collect$$libshutdown$$00000010)
.ARM.Collect$$rtentry$$00000000 0x080000e8 Section 0 __rtentry.o(.ARM.Collect$$rtentry$$00000000)
.ARM.Collect$$rtentry$$00000002 0x080000e8 Section 0 __rtentry2.o(.ARM.Collect$$rtentry$$00000002)
.ARM.Collect$$rtentry$$00000004 0x080000e8 Section 6 __rtentry4.o(.ARM.Collect$$rtentry$$00000004)
.ARM.Collect$$rtentry$$00000009 0x080000ee Section 0 __rtentry2.o(.ARM.Collect$$rtentry$$00000009)
.ARM.Collect$$rtentry$$0000000A 0x080000ee Section 4 __rtentry2.o(.ARM.Collect$$rtentry$$0000000A)
.ARM.Collect$$rtentry$$0000000C 0x080000f2 Section 0 __rtentry2.o(.ARM.Collect$$rtentry$$0000000C)
.ARM.Collect$$rtentry$$0000000D 0x080000f2 Section 8 __rtentry2.o(.ARM.Collect$$rtentry$$0000000D)
.ARM.Collect$$rtexit$$00000000 0x080000fa Section 2 rtexit.o(.ARM.Collect$$rtexit$$00000000)
.ARM.Collect$$rtexit$$00000002 0x080000fc Section 0 rtexit2.o(.ARM.Collect$$rtexit$$00000002)
.ARM.Collect$$rtexit$$00000003 0x080000fc Section 4 rtexit2.o(.ARM.Collect$$rtexit$$00000003)
.ARM.Collect$$rtexit$$00000004 0x08000100 Section 6 rtexit2.o(.ARM.Collect$$rtexit$$00000004)
.text 0x08000108 Section 56 startup_n32g003.o(.text)
.text 0x08000140 Section 0 heapauxi.o(.text)
.text 0x08000146 Section 62 sys_stackheap_outer.o(.text)
.text 0x08000184 Section 0 exit.o(.text)
.text 0x08000194 Section 8 libspace.o(.text)
.text 0x0800019c Section 0 sys_exit.o(.text)
.text 0x080001a8 Section 2 use_no_semi.o(.text)
.text 0x080001aa Section 0 indicate_semi.o(.text)
[Anonymous Symbol] 0x080001ac Section 0 n32g003_rcc.o(.text.RCC_Sysclk_Config)
System_Clock_Set 0x080001bd Thumb Code 88 system_n32g003.o(.text.System_Clock_Set)
[Anonymous Symbol] 0x080001bc Section 0 system_n32g003.o(.text.System_Clock_Set)
[Anonymous Symbol] 0x08000214 Section 0 system_n32g003.o(.text.System_Initializes)
__arm_cp.0_0 0x08000264 Number 4 system_n32g003.o(.text.System_Initializes)
__arm_cp.0_1 0x08000268 Number 4 system_n32g003.o(.text.System_Initializes)
__arm_cp.0_2 0x0800026c Number 4 system_n32g003.o(.text.System_Initializes)
__arm_cp.0_3 0x08000270 Number 4 system_n32g003.o(.text.System_Initializes)
__arm_cp.0_4 0x08000274 Number 4 system_n32g003.o(.text.System_Initializes)
Systeminit_Flash_Latency_Set 0x08000279 Thumb Code 20 system_n32g003.o(.text.Systeminit_Flash_Latency_Set)
[Anonymous Symbol] 0x08000278 Section 0 system_n32g003.o(.text.Systeminit_Flash_Latency_Set)
__arm_cp.3_0 0x08000288 Number 4 system_n32g003.o(.text.Systeminit_Flash_Latency_Set)
delay_loop 0x0800028d Thumb Code 36 main.o(.text.delay_loop)
[Anonymous Symbol] 0x0800028c Section 0 main.o(.text.delay_loop)
__arm_cp.1_0 0x080002ac Number 4 main.o(.text.delay_loop)
[Anonymous Symbol] 0x080002b0 Section 0 main.o(.text.main)
__arm_cp.0_0 0x080002c4 Number 4 main.o(.text.main)
.bss 0x20000000 Section 96 libspace.o(.bss)
g_loop_count 0x20000060 Data 4 main.o(.bss.g_loop_count)
[Anonymous Symbol] 0x20000060 Section 0 main.o(.bss.g_loop_count)
Heap_Mem 0x20000068 Data 512 startup_n32g003.o(HEAP)
HEAP 0x20000068 Section 512 startup_n32g003.o(HEAP)
Stack_Mem 0x20000268 Data 1024 startup_n32g003.o(STACK)
STACK 0x20000268 Section 1024 startup_n32g003.o(STACK)
__initial_sp 0x20000668 Data 0 startup_n32g003.o(STACK)
Global Symbols
Symbol Name Value Ov Type Size Object(Section)
BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$~IW$USESV6$~STKCKD$USESV7$~SHL$OTIME$ROPI$EBA8$UX$STANDARDLIB$REQ8$PRES8$EABIv2 0x00000000 Number 0 anon$$obj.o ABSOLUTE
__ARM_exceptions_init - Undefined Weak Reference
__alloca_initialize - Undefined Weak Reference
__arm_preinit_ - Undefined Weak Reference
__cpp_initialize__aeabi_ - Undefined Weak Reference
__cxa_finalize - Undefined Weak Reference
__rt_locale - Undefined Weak Reference
__sigvec_lookup - Undefined Weak Reference
_atexit_init - Undefined Weak Reference
_call_atexit_fns - Undefined Weak Reference
_clock_init - Undefined Weak Reference
_fp_trap_init - Undefined Weak Reference
_fp_trap_shutdown - Undefined Weak Reference
_get_lc_collate - Undefined Weak Reference
_get_lc_ctype - Undefined Weak Reference
_get_lc_monetary - Undefined Weak Reference
_get_lc_numeric - Undefined Weak Reference
_get_lc_time - Undefined Weak Reference
_getenv_init - Undefined Weak Reference
_handle_redirection - Undefined Weak Reference
_init_alloc - Undefined Weak Reference
_init_user_alloc - Undefined Weak Reference
_initio - Undefined Weak Reference
_rand_init - Undefined Weak Reference
_signal_finish - Undefined Weak Reference
_signal_init - Undefined Weak Reference
_terminate_alloc - Undefined Weak Reference
_terminate_user_alloc - Undefined Weak Reference
_terminateio - Undefined Weak Reference
__Vectors_Size 0x00000080 Number 0 startup_n32g003.o ABSOLUTE
__Vectors 0x08000000 Data 4 startup_n32g003.o(RESET)
__Vectors_End 0x08000080 Data 0 startup_n32g003.o(RESET)
__main 0x08000081 Thumb Code 8 __main.o(!!!main)
__scatterload 0x08000089 Thumb Code 0 __scatter.o(!!!scatter)
__scatterload_rt2 0x08000089 Thumb Code 52 __scatter.o(!!!scatter)
__scatterload_rt2_thumb_only 0x08000089 Thumb Code 0 __scatter.o(!!!scatter)
__scatterload_null 0x08000099 Thumb Code 0 __scatter.o(!!!scatter)
__scatterload_zeroinit 0x080000c5 Thumb Code 28 __scatter_zi.o(!!handler_zi)
__rt_lib_init 0x080000e1 Thumb Code 0 libinit.o(.ARM.Collect$$libinit$$00000000)
__rt_lib_init_alloca_1 0x080000e3 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000002E)
__rt_lib_init_argv_1 0x080000e3 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000002C)
__rt_lib_init_atexit_1 0x080000e3 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000001B)
__rt_lib_init_clock_1 0x080000e3 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000021)
__rt_lib_init_cpp_1 0x080000e3 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000032)
__rt_lib_init_exceptions_1 0x080000e3 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000030)
__rt_lib_init_fp_1 0x080000e3 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000002)
__rt_lib_init_fp_trap_1 0x080000e3 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000001F)
__rt_lib_init_getenv_1 0x080000e3 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000023)
__rt_lib_init_heap_1 0x080000e3 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000000A)
__rt_lib_init_lc_collate_1 0x080000e3 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000011)
__rt_lib_init_lc_ctype_1 0x080000e3 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000013)
__rt_lib_init_lc_monetary_1 0x080000e3 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000015)
__rt_lib_init_lc_numeric_1 0x080000e3 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000017)
__rt_lib_init_lc_time_1 0x080000e3 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000019)
__rt_lib_init_preinit_1 0x080000e3 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000004)
__rt_lib_init_rand_1 0x080000e3 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000000E)
__rt_lib_init_return 0x080000e3 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000033)
__rt_lib_init_signal_1 0x080000e3 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000001D)
__rt_lib_init_stdio_1 0x080000e3 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000025)
__rt_lib_init_user_alloc_1 0x080000e3 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000000C)
__rt_lib_shutdown 0x080000e5 Thumb Code 0 libshutdown.o(.ARM.Collect$$libshutdown$$00000000)
__rt_lib_shutdown_cpp_1 0x080000e7 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000002)
__rt_lib_shutdown_fp_trap_1 0x080000e7 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000007)
__rt_lib_shutdown_heap_1 0x080000e7 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000F)
__rt_lib_shutdown_return 0x080000e7 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000010)
__rt_lib_shutdown_signal_1 0x080000e7 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000A)
__rt_lib_shutdown_stdio_1 0x080000e7 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000004)
__rt_lib_shutdown_user_alloc_1 0x080000e7 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C)
__rt_entry 0x080000e9 Thumb Code 0 __rtentry.o(.ARM.Collect$$rtentry$$00000000)
__rt_entry_presh_1 0x080000e9 Thumb Code 0 __rtentry2.o(.ARM.Collect$$rtentry$$00000002)
__rt_entry_sh 0x080000e9 Thumb Code 0 __rtentry4.o(.ARM.Collect$$rtentry$$00000004)
__rt_entry_li 0x080000ef Thumb Code 0 __rtentry2.o(.ARM.Collect$$rtentry$$0000000A)
__rt_entry_postsh_1 0x080000ef Thumb Code 0 __rtentry2.o(.ARM.Collect$$rtentry$$00000009)
__rt_entry_main 0x080000f3 Thumb Code 0 __rtentry2.o(.ARM.Collect$$rtentry$$0000000D)
__rt_entry_postli_1 0x080000f3 Thumb Code 0 __rtentry2.o(.ARM.Collect$$rtentry$$0000000C)
__rt_exit 0x080000fb Thumb Code 0 rtexit.o(.ARM.Collect$$rtexit$$00000000)
__rt_exit_ls 0x080000fd Thumb Code 0 rtexit2.o(.ARM.Collect$$rtexit$$00000003)
__rt_exit_prels_1 0x080000fd Thumb Code 0 rtexit2.o(.ARM.Collect$$rtexit$$00000002)
__rt_exit_exit 0x08000101 Thumb Code 0 rtexit2.o(.ARM.Collect$$rtexit$$00000004)
Reset_Handler 0x08000109 Thumb Code 8 startup_n32g003.o(.text)
NMI_Handler 0x08000111 Thumb Code 2 startup_n32g003.o(.text)
HardFault_Handler 0x08000113 Thumb Code 2 startup_n32g003.o(.text)
SVC_Handler 0x08000115 Thumb Code 2 startup_n32g003.o(.text)
PendSV_Handler 0x08000117 Thumb Code 2 startup_n32g003.o(.text)
SysTick_Handler 0x08000119 Thumb Code 2 startup_n32g003.o(.text)
ADC_IRQHandler 0x0800011b Thumb Code 0 startup_n32g003.o(.text)
COMP_IRQHandler 0x0800011b Thumb Code 0 startup_n32g003.o(.text)
EXTI0_1_IRQHandler 0x0800011b Thumb Code 0 startup_n32g003.o(.text)
EXTI2_3_IRQHandler 0x0800011b Thumb Code 0 startup_n32g003.o(.text)
EXTI4_17_IRQHandler 0x0800011b Thumb Code 0 startup_n32g003.o(.text)
FLASH_IRQHandler 0x0800011b Thumb Code 0 startup_n32g003.o(.text)
I2C_ER_IRQHandler 0x0800011b Thumb Code 0 startup_n32g003.o(.text)
I2C_EV_IRQHandler 0x0800011b Thumb Code 0 startup_n32g003.o(.text)
PVD_IRQHandler 0x0800011b Thumb Code 0 startup_n32g003.o(.text)
SPI_IRQHandler 0x0800011b Thumb Code 0 startup_n32g003.o(.text)
TIM1_BRK_UP_TRG_COM_IRQHandler 0x0800011b Thumb Code 0 startup_n32g003.o(.text)
TIM1_CC_IRQHandler 0x0800011b Thumb Code 0 startup_n32g003.o(.text)
TIM3_IRQHandler 0x0800011b Thumb Code 0 startup_n32g003.o(.text)
TIM6_IRQHandler 0x0800011b Thumb Code 0 startup_n32g003.o(.text)
UART1_IRQHandler 0x0800011b Thumb Code 0 startup_n32g003.o(.text)
UART2_IRQHandler 0x0800011b Thumb Code 0 startup_n32g003.o(.text)
__user_initial_stackheap 0x0800011d Thumb Code 0 startup_n32g003.o(.text)
__use_two_region_memory 0x08000141 Thumb Code 2 heapauxi.o(.text)
__rt_heap_escrow$2region 0x08000143 Thumb Code 2 heapauxi.o(.text)
__rt_heap_expand$2region 0x08000145 Thumb Code 2 heapauxi.o(.text)
__user_setup_stackheap 0x08000147 Thumb Code 62 sys_stackheap_outer.o(.text)
exit 0x08000185 Thumb Code 16 exit.o(.text)
__user_libspace 0x08000195 Thumb Code 8 libspace.o(.text)
__user_perproc_libspace 0x08000195 Thumb Code 0 libspace.o(.text)
__user_perthread_libspace 0x08000195 Thumb Code 0 libspace.o(.text)
_sys_exit 0x0800019d Thumb Code 8 sys_exit.o(.text)
__I$use$semihosting 0x080001a9 Thumb Code 0 use_no_semi.o(.text)
__use_no_semihosting_swi 0x080001a9 Thumb Code 2 use_no_semi.o(.text)
__semihosting_library_function 0x080001ab Thumb Code 0 indicate_semi.o(.text)
RCC_Sysclk_Config 0x080001ad Thumb Code 16 n32g003_rcc.o(.text.RCC_Sysclk_Config)
System_Initializes 0x08000215 Thumb Code 100 system_n32g003.o(.text.System_Initializes)
main 0x080002b1 Thumb Code 24 main.o(.text.main)
Region$$Table$$Base 0x080002c8 Number 0 anon$$obj.o(Region$$Table)
Region$$Table$$Limit 0x080002d8 Number 0 anon$$obj.o(Region$$Table)
__libspace_start 0x20000000 Data 96 libspace.o(.bss)
__temporary_stack_top$libspace 0x20000060 Data 0 libspace.o(.bss)
==============================================================================
Memory Map of the image
Image Entry point : 0x08000081
Load Region LR_IROM1 (Base: 0x08000000, Size: 0x000002d8, Max: 0x00007600, ABSOLUTE)
Execution Region ER_IROM1 (Exec base: 0x08000000, Load base: 0x08000000, Size: 0x000002d8, Max: 0x00007600, ABSOLUTE)
Exec Addr Load Addr Size Type Attr Idx E Section Name Object
0x08000000 0x08000000 0x00000080 Data RO 100 RESET startup_n32g003.o
0x08000080 0x08000080 0x00000008 Code RO 119 * !!!main c_p.l(__main.o)
0x08000088 0x08000088 0x0000003c Code RO 294 !!!scatter c_p.l(__scatter.o)
0x080000c4 0x080000c4 0x0000001c Code RO 296 !!handler_zi c_p.l(__scatter_zi.o)
0x080000e0 0x080000e0 0x00000002 Code RO 157 .ARM.Collect$$libinit$$00000000 c_p.l(libinit.o)
0x080000e2 0x080000e2 0x00000000 Code RO 171 .ARM.Collect$$libinit$$00000002 c_p.l(libinit2.o)
0x080000e2 0x080000e2 0x00000000 Code RO 173 .ARM.Collect$$libinit$$00000004 c_p.l(libinit2.o)
0x080000e2 0x080000e2 0x00000000 Code RO 176 .ARM.Collect$$libinit$$0000000A c_p.l(libinit2.o)
0x080000e2 0x080000e2 0x00000000 Code RO 178 .ARM.Collect$$libinit$$0000000C c_p.l(libinit2.o)
0x080000e2 0x080000e2 0x00000000 Code RO 180 .ARM.Collect$$libinit$$0000000E c_p.l(libinit2.o)
0x080000e2 0x080000e2 0x00000000 Code RO 183 .ARM.Collect$$libinit$$00000011 c_p.l(libinit2.o)
0x080000e2 0x080000e2 0x00000000 Code RO 185 .ARM.Collect$$libinit$$00000013 c_p.l(libinit2.o)
0x080000e2 0x080000e2 0x00000000 Code RO 187 .ARM.Collect$$libinit$$00000015 c_p.l(libinit2.o)
0x080000e2 0x080000e2 0x00000000 Code RO 189 .ARM.Collect$$libinit$$00000017 c_p.l(libinit2.o)
0x080000e2 0x080000e2 0x00000000 Code RO 191 .ARM.Collect$$libinit$$00000019 c_p.l(libinit2.o)
0x080000e2 0x080000e2 0x00000000 Code RO 193 .ARM.Collect$$libinit$$0000001B c_p.l(libinit2.o)
0x080000e2 0x080000e2 0x00000000 Code RO 195 .ARM.Collect$$libinit$$0000001D c_p.l(libinit2.o)
0x080000e2 0x080000e2 0x00000000 Code RO 197 .ARM.Collect$$libinit$$0000001F c_p.l(libinit2.o)
0x080000e2 0x080000e2 0x00000000 Code RO 199 .ARM.Collect$$libinit$$00000021 c_p.l(libinit2.o)
0x080000e2 0x080000e2 0x00000000 Code RO 201 .ARM.Collect$$libinit$$00000023 c_p.l(libinit2.o)
0x080000e2 0x080000e2 0x00000000 Code RO 203 .ARM.Collect$$libinit$$00000025 c_p.l(libinit2.o)
0x080000e2 0x080000e2 0x00000000 Code RO 207 .ARM.Collect$$libinit$$0000002C c_p.l(libinit2.o)
0x080000e2 0x080000e2 0x00000000 Code RO 209 .ARM.Collect$$libinit$$0000002E c_p.l(libinit2.o)
0x080000e2 0x080000e2 0x00000000 Code RO 211 .ARM.Collect$$libinit$$00000030 c_p.l(libinit2.o)
0x080000e2 0x080000e2 0x00000000 Code RO 213 .ARM.Collect$$libinit$$00000032 c_p.l(libinit2.o)
0x080000e2 0x080000e2 0x00000002 Code RO 214 .ARM.Collect$$libinit$$00000033 c_p.l(libinit2.o)
0x080000e4 0x080000e4 0x00000002 Code RO 249 .ARM.Collect$$libshutdown$$00000000 c_p.l(libshutdown.o)
0x080000e6 0x080000e6 0x00000000 Code RO 277 .ARM.Collect$$libshutdown$$00000002 c_p.l(libshutdown2.o)
0x080000e6 0x080000e6 0x00000000 Code RO 279 .ARM.Collect$$libshutdown$$00000004 c_p.l(libshutdown2.o)
0x080000e6 0x080000e6 0x00000000 Code RO 282 .ARM.Collect$$libshutdown$$00000007 c_p.l(libshutdown2.o)
0x080000e6 0x080000e6 0x00000000 Code RO 285 .ARM.Collect$$libshutdown$$0000000A c_p.l(libshutdown2.o)
0x080000e6 0x080000e6 0x00000000 Code RO 287 .ARM.Collect$$libshutdown$$0000000C c_p.l(libshutdown2.o)
0x080000e6 0x080000e6 0x00000000 Code RO 290 .ARM.Collect$$libshutdown$$0000000F c_p.l(libshutdown2.o)
0x080000e6 0x080000e6 0x00000002 Code RO 291 .ARM.Collect$$libshutdown$$00000010 c_p.l(libshutdown2.o)
0x080000e8 0x080000e8 0x00000000 Code RO 121 .ARM.Collect$$rtentry$$00000000 c_p.l(__rtentry.o)
0x080000e8 0x080000e8 0x00000000 Code RO 127 .ARM.Collect$$rtentry$$00000002 c_p.l(__rtentry2.o)
0x080000e8 0x080000e8 0x00000006 Code RO 139 .ARM.Collect$$rtentry$$00000004 c_p.l(__rtentry4.o)
0x080000ee 0x080000ee 0x00000000 Code RO 129 .ARM.Collect$$rtentry$$00000009 c_p.l(__rtentry2.o)
0x080000ee 0x080000ee 0x00000004 Code RO 130 .ARM.Collect$$rtentry$$0000000A c_p.l(__rtentry2.o)
0x080000f2 0x080000f2 0x00000000 Code RO 132 .ARM.Collect$$rtentry$$0000000C c_p.l(__rtentry2.o)
0x080000f2 0x080000f2 0x00000008 Code RO 133 .ARM.Collect$$rtentry$$0000000D c_p.l(__rtentry2.o)
0x080000fa 0x080000fa 0x00000002 Code RO 162 .ARM.Collect$$rtexit$$00000000 c_p.l(rtexit.o)
0x080000fc 0x080000fc 0x00000000 Code RO 220 .ARM.Collect$$rtexit$$00000002 c_p.l(rtexit2.o)
0x080000fc 0x080000fc 0x00000004 Code RO 221 .ARM.Collect$$rtexit$$00000003 c_p.l(rtexit2.o)
0x08000100 0x08000100 0x00000006 Code RO 222 .ARM.Collect$$rtexit$$00000004 c_p.l(rtexit2.o)
0x08000106 0x08000106 0x00000002 PAD
0x08000108 0x08000108 0x00000038 Code RO 101 .text startup_n32g003.o
0x08000140 0x08000140 0x00000006 Code RO 117 .text c_p.l(heapauxi.o)
0x08000146 0x08000146 0x0000003e Code RO 143 .text c_p.l(sys_stackheap_outer.o)
0x08000184 0x08000184 0x00000010 Code RO 146 .text c_p.l(exit.o)
0x08000194 0x08000194 0x00000008 Code RO 158 .text c_p.l(libspace.o)
0x0800019c 0x0800019c 0x0000000c Code RO 215 .text c_p.l(sys_exit.o)
0x080001a8 0x080001a8 0x00000002 Code RO 238 .text c_p.l(use_no_semi.o)
0x080001aa 0x080001aa 0x00000000 Code RO 240 .text c_p.l(indicate_semi.o)
0x080001aa 0x080001aa 0x00000002 PAD
0x080001ac 0x080001ac 0x00000010 Code RO 39 .text.RCC_Sysclk_Config n32g003_rcc.o
0x080001bc 0x080001bc 0x00000058 Code RO 17 .text.System_Clock_Set system_n32g003.o
0x08000214 0x08000214 0x00000064 Code RO 15 .text.System_Initializes system_n32g003.o
0x08000278 0x08000278 0x00000014 Code RO 21 .text.Systeminit_Flash_Latency_Set system_n32g003.o
0x0800028c 0x0800028c 0x00000024 Code RO 4 .text.delay_loop main.o
0x080002b0 0x080002b0 0x00000018 Code RO 2 .text.main main.o
0x080002c8 0x080002c8 0x00000010 Data RO 293 Region$$Table anon$$obj.o
Execution Region RW_IRAM1 (Exec base: 0x20000000, Load base: 0x080002d8, Size: 0x00000668, Max: 0x00000c00, ABSOLUTE)
Exec Addr Load Addr Size Type Attr Idx E Section Name Object
0x20000000 - 0x00000060 Zero RW 159 .bss c_p.l(libspace.o)
0x20000060 - 0x00000004 Zero RW 6 .bss.g_loop_count main.o
0x20000064 0x080002d8 0x00000004 PAD
0x20000068 - 0x00000200 Zero RW 99 HEAP startup_n32g003.o
0x20000268 - 0x00000400 Zero RW 98 STACK startup_n32g003.o
==============================================================================
Image component sizes
Code (inc. data) RO Data RW Data ZI Data Debug Object Name
60 8 0 0 4 767 main.o
16 0 0 0 0 6802 n32g003_rcc.o
56 26 128 0 1536 636 startup_n32g003.o
208 24 0 0 0 2482 system_n32g003.o
----------------------------------------------------------------------
340 58 144 0 1544 10687 Object Totals
0 0 16 0 0 0 (incl. Generated)
0 0 0 0 4 0 (incl. Padding)
----------------------------------------------------------------------
Code (inc. data) RO Data RW Data ZI Data Debug Library Member Name
8 0 0 0 0 68 __main.o
0 0 0 0 0 0 __rtentry.o
12 0 0 0 0 0 __rtentry2.o
6 0 0 0 0 0 __rtentry4.o
60 8 0 0 0 0 __scatter.o
28 0 0 0 0 0 __scatter_zi.o
16 0 0 0 0 68 exit.o
6 0 0 0 0 136 heapauxi.o
0 0 0 0 0 0 indicate_semi.o
2 0 0 0 0 0 libinit.o
2 0 0 0 0 0 libinit2.o
2 0 0 0 0 0 libshutdown.o
2 0 0 0 0 0 libshutdown2.o
8 4 0 0 96 68 libspace.o
2 0 0 0 0 0 rtexit.o
10 0 0 0 0 0 rtexit2.o
12 4 0 0 0 60 sys_exit.o
62 0 0 0 0 80 sys_stackheap_outer.o
2 0 0 0 0 68 use_no_semi.o
----------------------------------------------------------------------
244 16 0 0 96 548 Library Totals
4 0 0 0 0 0 (incl. Padding)
----------------------------------------------------------------------
Code (inc. data) RO Data RW Data ZI Data Debug Library Name
240 16 0 0 96 548 c_p.l
----------------------------------------------------------------------
244 16 0 0 96 548 Library Totals
----------------------------------------------------------------------
==============================================================================
Code (inc. data) RO Data RW Data ZI Data Debug
584 74 144 0 1640 11043 Grand Totals
584 74 144 0 1640 11043 ELF Image Totals
584 74 144 0 0 0 ROM Totals
==============================================================================
Total RO Size (Code + RO Data) 728 ( 0.71kB)
Total RW Size (RW Data + ZI Data) 1640 ( 1.60kB)
Total ROM Size (Code + RO Data + RW Data) 728 ( 0.71kB)
==============================================================================

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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<ProjectOpt xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_optx.xsd">
<SchemaVersion>1.0</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Extensions>
<cExt>*.c</cExt>
<aExt>*.s*; *.src; *.a*</aExt>
<oExt>*.obj; *.o</oExt>
<lExt>*.lib</lExt>
<tExt>*.txt; *.h; *.inc</tExt>
<pExt>*.plm</pExt>
<CppX>*.cpp</CppX>
<nMigrate>0</nMigrate>
</Extensions>
<DaveTm>
<dwLowDateTime>0</dwLowDateTime>
<dwHighDateTime>0</dwHighDateTime>
</DaveTm>
<Target>
<TargetName>Target 1</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<TargetOption>
<CLKADS>12000000</CLKADS>
<OPTTT>
<gFlags>1</gFlags>
<BeepAtEnd>1</BeepAtEnd>
<RunSim>0</RunSim>
<RunTarget>1</RunTarget>
<RunAbUc>0</RunAbUc>
</OPTTT>
<OPTHX>
<HexSelection>1</HexSelection>
<FlashByte>65535</FlashByte>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
</OPTHX>
<OPTLEX>
<PageWidth>79</PageWidth>
<PageLength>66</PageLength>
<TabStop>8</TabStop>
<ListingPath>.\Listings\</ListingPath>
</OPTLEX>
<ListingPage>
<CreateCListing>1</CreateCListing>
<CreateAListing>1</CreateAListing>
<CreateLListing>1</CreateLListing>
<CreateIListing>0</CreateIListing>
<AsmCond>1</AsmCond>
<AsmSymb>1</AsmSymb>
<AsmXref>0</AsmXref>
<CCond>1</CCond>
<CCode>0</CCode>
<CListInc>0</CListInc>
<CSymb>0</CSymb>
<LinkerCodeListing>0</LinkerCodeListing>
</ListingPage>
<OPTXL>
<LMap>1</LMap>
<LComments>1</LComments>
<LGenerateSymbols>1</LGenerateSymbols>
<LLibSym>1</LLibSym>
<LLines>1</LLines>
<LLocSym>1</LLocSym>
<LPubSym>1</LPubSym>
<LXref>0</LXref>
<LExpSel>0</LExpSel>
</OPTXL>
<OPTFL>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<IsCurrentTarget>1</IsCurrentTarget>
</OPTFL>
<CpuCode>255</CpuCode>
<DebugOpt>
<uSim>0</uSim>
<uTrg>1</uTrg>
<sLdApp>1</sLdApp>
<sGomain>1</sGomain>
<sRbreak>1</sRbreak>
<sRwatch>1</sRwatch>
<sRmem>1</sRmem>
<sRfunc>1</sRfunc>
<sRbox>1</sRbox>
<tLdApp>1</tLdApp>
<tGomain>1</tGomain>
<tRbreak>1</tRbreak>
<tRwatch>1</tRwatch>
<tRmem>1</tRmem>
<tRfunc>0</tRfunc>
<tRbox>1</tRbox>
<tRtrace>1</tRtrace>
<sRSysVw>1</sRSysVw>
<tRSysVw>1</tRSysVw>
<sRunDeb>0</sRunDeb>
<sLrtime>0</sLrtime>
<bEvRecOn>1</bEvRecOn>
<bSchkAxf>0</bSchkAxf>
<bTchkAxf>0</bTchkAxf>
<nTsel>3</nTsel>
<sDll></sDll>
<sDllPa></sDllPa>
<sDlgDll></sDlgDll>
<sDlgPa></sDlgPa>
<sIfile></sIfile>
<tDll></tDll>
<tDllPa></tDllPa>
<tDlgDll></tDlgDll>
<tDlgPa></tDlgPa>
<tIfile></tIfile>
<pMon>BIN\CMSIS_AGDI.dll</pMon>
</DebugOpt>
<TargetDriverDllRegistry>
<SetRegEntry>
<Number>0</Number>
<Key>ARMRTXEVENTFLAGS</Key>
<Name>-L70 -Z18 -C0 -M0 -T1</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGTARM</Key>
<Name>(1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>ARMDBGFLAGS</Key>
<Name></Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>DLGUARM</Key>
<Name></Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>CMSIS_AGDI</Key>
<Name>-X"CMSIS-DAP-NSLink" -U0001A0000002 -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8009 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0N32G003x.FLM -FS08000000 -FL07600 -FP0($$Device:N32G003F5$Flash\N32G003x.FLM)</Name>
</SetRegEntry>
<SetRegEntry>
<Number>0</Number>
<Key>UL2CM3</Key>
<Name>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC800 -FN1 -FF0N32G003x -FS08000000 -FL07600 -FP0($$Device:N32G003F5$Flash\N32G003x.FLM))</Name>
</SetRegEntry>
</TargetDriverDllRegistry>
<Breakpoint/>
<Tracepoint>
<THDelay>0</THDelay>
</Tracepoint>
<DebugFlag>
<trace>0</trace>
<periodic>1</periodic>
<aLwin>0</aLwin>
<aCover>0</aCover>
<aSer1>0</aSer1>
<aSer2>0</aSer2>
<aPa>0</aPa>
<viewmode>1</viewmode>
<vrSel>0</vrSel>
<aSym>0</aSym>
<aTbox>0</aTbox>
<AscS1>0</AscS1>
<AscS2>0</AscS2>
<AscS3>0</AscS3>
<aSer3>0</aSer3>
<eProf>0</eProf>
<aLa>0</aLa>
<aPa1>0</aPa1>
<AscS4>0</AscS4>
<aSer4>0</aSer4>
<StkLoc>0</StkLoc>
<TrcWin>0</TrcWin>
<newCpu>0</newCpu>
<uProt>0</uProt>
</DebugFlag>
<LintExecutable></LintExecutable>
<LintConfigFile></LintConfigFile>
<bLintAuto>0</bLintAuto>
<bAutoGenD>0</bAutoGenD>
<LntExFlags>0</LntExFlags>
<pMisraName></pMisraName>
<pszMrule></pszMrule>
<pSingCmds></pSingCmds>
<pMultCmds></pMultCmds>
<pMisraNamep></pMisraNamep>
<pszMrulep></pszMrulep>
<pSingCmdsp></pSingCmdsp>
<pMultCmdsp></pMultCmdsp>
</TargetOption>
</Target>
<Group>
<GroupName>Source Group 1</GroupName>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>1</GroupNumber>
<FileNumber>1</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>main.c</PathWithFileName>
<FilenameWithoutPath>main.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>CMSIS</GroupName>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>2</GroupNumber>
<FileNumber>2</FileNumber>
<FileType>1</FileType>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>firmware\CMSIS\device\system_n32g003.c</PathWithFileName>
<FilenameWithoutPath>system_n32g003.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>STARTUP</GroupName>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>3</GroupNumber>
<FileNumber>3</FileNumber>
<FileType>2</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>firmware\CMSIS\device\startup\startup_n32g003.s</PathWithFileName>
<FilenameWithoutPath>startup_n32g003.s</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
<Group>
<GroupName>FWLB</GroupName>
<tvExp>1</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<cbSel>0</cbSel>
<RteFlg>0</RteFlg>
<File>
<GroupNumber>4</GroupNumber>
<FileNumber>4</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>firmware\n32g003_std_periph_driver\src\n32g003_rcc.c</PathWithFileName>
<FilenameWithoutPath>n32g003_rcc.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>4</GroupNumber>
<FileNumber>5</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>firmware\n32g003_std_periph_driver\src\n32g003_gpio.c</PathWithFileName>
<FilenameWithoutPath>n32g003_gpio.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
<File>
<GroupNumber>4</GroupNumber>
<FileNumber>6</FileNumber>
<FileType>1</FileType>
<tvExp>0</tvExp>
<tvExpOptDlg>0</tvExpOptDlg>
<bDave2>0</bDave2>
<PathWithFileName>firmware\n32g003_std_periph_driver\src\n32g003_uart.c</PathWithFileName>
<FilenameWithoutPath>n32g003_uart.c</FilenameWithoutPath>
<RteFlg>0</RteFlg>
<bShared>0</bShared>
</File>
</Group>
</ProjectOpt>

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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
<SchemaVersion>2.1</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Targets>
<Target>
<TargetName>Target 1</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<pCCUsed>6140000::V6.14::ARMCLANG</pCCUsed>
<uAC6>1</uAC6>
<TargetOption>
<TargetCommonOption>
<Device>N32G003F5</Device>
<Vendor>Nationstech</Vendor>
<PackID>Nationstech.N32G003_DFP.1.0.1</PackID>
<PackURL>http://www.keil.com/pack/</PackURL>
<Cpu>IRAM(0x20000000,0x0C00) IROM(0x08000000,0x7600) CPUTYPE("Cortex-M0") CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC800 -FN1 -FF0N32G003x -FS08000000 -FL07600 -FP0($$Device:N32G003F5$Flash\N32G003x.FLM))</FlashDriverDll>
<DeviceId>0</DeviceId>
<RegisterFile>firmware\CMSIS\device\n32g003.h</RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
<Linker></Linker>
<OHString></OHString>
<InfinionOptionDll></InfinionOptionDll>
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile>$$Device:N32G003F5$svd\N32G003.svd</SFDFile>
<bCustSvd>0</bCustSvd>
<UseEnv>0</UseEnv>
<BinPath></BinPath>
<IncludePath></IncludePath>
<LibPath></LibPath>
<RegisterFilePath></RegisterFilePath>
<DBRegisterFilePath></DBRegisterFilePath>
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
<ButtonStop>0</ButtonStop>
<NotGenerated>0</NotGenerated>
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>.\Objects\</OutputDirectory>
<OutputName>test</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>0</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>1</BrowseInformation>
<ListingPath>.\Listings\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
<CreateBatchFile>0</CreateBatchFile>
<BeforeCompile>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopU1X>0</nStopU1X>
<nStopU2X>0</nStopU2X>
</BeforeCompile>
<BeforeMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopB1X>0</nStopB1X>
<nStopB2X>0</nStopB2X>
</BeforeMake>
<AfterMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopA1X>0</nStopA1X>
<nStopA2X>0</nStopA2X>
</AfterMake>
<SelectedForBatchBuild>0</SelectedForBatchBuild>
<SVCSIdString></SVCSIdString>
</TargetCommonOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>1</IncludeInBuild>
<AlwaysBuild>0</AlwaysBuild>
<GenerateAssemblyFile>0</GenerateAssemblyFile>
<AssembleAssemblyFile>0</AssembleAssemblyFile>
<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>1</ComprImg>
</CommonProperty>
<DllOption>
<SimDllName>SARMCM3.DLL</SimDllName>
<SimDllArguments> -REMAP </SimDllArguments>
<SimDlgDll>DARMCM1.DLL</SimDlgDll>
<SimDlgDllArguments>-pCM0</SimDlgDllArguments>
<TargetDllName>SARMCM3.DLL</TargetDllName>
<TargetDllArguments> </TargetDllArguments>
<TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
<TargetDlgDllArguments>-pCM0</TargetDlgDllArguments>
</DllOption>
<DebugOption>
<OPTHX>
<HexSelection>1</HexSelection>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
<Oh166RecLen>16</Oh166RecLen>
</OPTHX>
</DebugOption>
<Utilities>
<Flash1>
<UseTargetDll>1</UseTargetDll>
<UseExternalTool>0</UseExternalTool>
<RunIndependent>0</RunIndependent>
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
<Capability>1</Capability>
<DriverSelection>-1</DriverSelection>
</Flash1>
<bUseTDR>1</bUseTDR>
<Flash2>BIN\UL2CM3.DLL</Flash2>
<Flash3></Flash3>
<Flash4></Flash4>
<pFcarmOut></pFcarmOut>
<pFcarmGrp></pFcarmGrp>
<pFcArmRoot></pFcArmRoot>
<FcArmLst>0</FcArmLst>
</Utilities>
<TargetArmAds>
<ArmAdsMisc>
<GenerateListings>0</GenerateListings>
<asHll>1</asHll>
<asAsm>1</asAsm>
<asMacX>1</asMacX>
<asSyms>1</asSyms>
<asFals>1</asFals>
<asDbgD>1</asDbgD>
<asForm>1</asForm>
<ldLst>0</ldLst>
<ldmm>1</ldmm>
<ldXref>1</ldXref>
<BigEnd>0</BigEnd>
<AdsALst>1</AdsALst>
<AdsACrf>1</AdsACrf>
<AdsANop>0</AdsANop>
<AdsANot>0</AdsANot>
<AdsLLst>1</AdsLLst>
<AdsLmap>1</AdsLmap>
<AdsLcgr>1</AdsLcgr>
<AdsLsym>1</AdsLsym>
<AdsLszi>1</AdsLszi>
<AdsLtoi>1</AdsLtoi>
<AdsLsun>1</AdsLsun>
<AdsLven>1</AdsLven>
<AdsLsxf>1</AdsLsxf>
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>"Cortex-M0"</AdsCpuType>
<RvctDeviceName></RvctDeviceName>
<mOS>0</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
<hadIROM>1</hadIROM>
<hadIRAM>1</hadIRAM>
<hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>0</RvdsVP>
<RvdsMve>0</RvdsMve>
<RvdsCdeCp>0</RvdsCdeCp>
<hadIRAM2>0</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
<useUlib>1</useUlib>
<EndSel>0</EndSel>
<uLtcg>0</uLtcg>
<nSecure>0</nSecure>
<RoSelD>3</RoSelD>
<RwSelD>3</RwSelD>
<CodeSel>0</CodeSel>
<OptFeed>0</OptFeed>
<NoZi1>0</NoZi1>
<NoZi2>0</NoZi2>
<NoZi3>0</NoZi3>
<NoZi4>0</NoZi4>
<NoZi5>0</NoZi5>
<Ro1Chk>0</Ro1Chk>
<Ro2Chk>0</Ro2Chk>
<Ro3Chk>0</Ro3Chk>
<Ir1Chk>1</Ir1Chk>
<Ir2Chk>0</Ir2Chk>
<Ra1Chk>0</Ra1Chk>
<Ra2Chk>0</Ra2Chk>
<Ra3Chk>0</Ra3Chk>
<Im1Chk>1</Im1Chk>
<Im2Chk>0</Im2Chk>
<OnChipMemories>
<Ocm1>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm1>
<Ocm2>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm2>
<Ocm3>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm3>
<Ocm4>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm4>
<Ocm5>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm5>
<Ocm6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm6>
<IRAM>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0xc00</Size>
</IRAM>
<IROM>
<Type>1</Type>
<StartAddress>0x8000000</StartAddress>
<Size>0x7600</Size>
</IROM>
<XRAM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</XRAM>
<OCR_RVCT1>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT1>
<OCR_RVCT2>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT2>
<OCR_RVCT3>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT3>
<OCR_RVCT4>
<Type>1</Type>
<StartAddress>0x8000000</StartAddress>
<Size>0x7600</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT5>
<OCR_RVCT6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT6>
<OCR_RVCT7>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT7>
<OCR_RVCT8>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0xc00</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
<Optim>2</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>1</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>2</wLevel>
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<uC99>0</uC99>
<uGnu>0</uGnu>
<useXO>0</useXO>
<v6Lang>3</v6Lang>
<v6LangP>3</v6LangP>
<vShortEn>1</vShortEn>
<vShortWch>1</vShortWch>
<v6Lto>0</v6Lto>
<v6WtE>0</v6WtE>
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls></MiscControls>
<Define>N32G003, USE_STDPERIPH_DRIVER</Define>
<Undefine></Undefine>
<IncludePath>.\firmware\CMSIS\core;.\firmware\CMSIS\device;.\firmware\n32g003_std_periph_driver\inc</IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>1</interw>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<thumb>0</thumb>
<SplitLS>0</SplitLS>
<SwStkChk>0</SwStkChk>
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<useXO>0</useXO>
<ClangAsOpt>1</ClangAsOpt>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
<LDads>
<umfTarg>1</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
<RepFail>1</RepFail>
<useFile>0</useFile>
<TextAddressRange>0x08000000</TextAddressRange>
<DataAddressRange>0x20000000</DataAddressRange>
<pXoBase></pXoBase>
<ScatterFile></ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc></Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
<Groups>
<Group>
<GroupName>Source Group 1</GroupName>
<Files>
<File>
<FileName>main.c</FileName>
<FileType>1</FileType>
<FilePath>main.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>CMSIS</GroupName>
<Files>
<File>
<FileName>system_n32g003.c</FileName>
<FileType>1</FileType>
<FilePath>firmware\CMSIS\device\system_n32g003.c</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>STARTUP</GroupName>
<Files>
<File>
<FileName>startup_n32g003.s</FileName>
<FileType>2</FileType>
<FilePath>firmware\CMSIS\device\startup\startup_n32g003.s</FilePath>
</File>
</Files>
</Group>
<Group>
<GroupName>FWLB</GroupName>
<Files>
<File>
<FileName>n32g003_rcc.c</FileName>
<FileType>1</FileType>
<FilePath>firmware\n32g003_std_periph_driver\src\n32g003_rcc.c</FilePath>
</File>
<File>
<FileName>n32g003_gpio.c</FileName>
<FileType>1</FileType>
<FilePath>firmware\n32g003_std_periph_driver\src\n32g003_gpio.c</FilePath>
</File>
<File>
<FileName>n32g003_uart.c</FileName>
<FileType>1</FileType>
<FilePath>firmware\n32g003_std_periph_driver\src\n32g003_uart.c</FilePath>
</File>
</Files>
</Group>
</Groups>
</Target>
</Targets>
<RTE>
<apis/>
<components/>
<files/>
</RTE>
<LayerInfo>
<Layers>
<Layer>
<LayName>&lt;Project Info&gt;</LayName>
<LayDesc></LayDesc>
<LayUrl></LayUrl>
<LayKeys></LayKeys>
<LayCat></LayCat>
<LayLic></LayLic>
<LayTarg>0</LayTarg>
<LayPrjMark>1</LayPrjMark>
</Layer>
</Layers>
</LayerInfo>
</Project>