272 lines
12 KiB
C
272 lines
12 KiB
C
/**
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* Copyright (c) 2022, Nations Technologies Inc.
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*
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* All rights reserved.
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*
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* This software is the exclusive property of Nations Technologies Inc. (Hereinafter
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* referred to as NATIONS). This software, and the product of NATIONS described herein
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* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties
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* of the People's Republic of China and other applicable jurisdictions worldwide.
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*
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* NATIONS does not grant any license under its patents, copyrights, trademarks, or other
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* intellectual property rights. Names and brands of third party may be mentioned or referred
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* thereto (if any) for identification purposes only.
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*
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* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and
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* improvements to this software at any time without notice. Please contact NATIONS and obtain
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* the latest version of this software before placing orders.
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* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes
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* no responsibility for the accuracy and reliability of this software.
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*
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* It is the responsibility of the user of this software to properly design, program, and test
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* the functionality and safety of any application made of this information and any resulting product.
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* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or
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* consequential damages arising in any way out of the use of this software or the Product.
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*
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* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any
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* malfunction or failure of which may cause loss of human life, bodily injury or severe property
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* damage. Such applications are deemed, "Insecure Usage".
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*
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* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS
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* harmless from and against all claims, costs, damages, and other liabilities, arising from or related
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* to any customer's Insecure Usage.
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* Any express or implied warranty with regard to this software or the Product, including,but not
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* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement
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* are disclaimed to the fullest extent permitted by law.
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* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe
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* or otherwise distribute this software for any purposes, in whole or in part.
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*
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* NATIONS products and technologies shall not be used for or incorporated into any products or systems
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* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations.
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* User shall comply with any applicable export control laws and regulations promulgated and administered by
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* the governments of any countries asserting jurisdiction over the parties or transactions.
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**/
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/**
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*\*\file n32g003_rcc.h
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*\*\author Nations
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*\*\version v1.0.0
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*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
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*/
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#ifndef __n32g003_RCC_H
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#define __n32g003_RCC_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "n32g003.h"
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/** RCC_Exported_Types **/
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typedef struct
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{
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uint32_t SysclkFreq; /* returns SYSCLK clock frequency expressed in Hz */
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uint32_t HclkFreq; /* returns HCLK clock frequency expressed in Hz */
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uint32_t PclkFreq; /* returns PCLK clock frequency expressed in Hz */
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uint32_t Adc1MClkFreq; /* returns ADC1MHCLK clock frequency expressed in Hz */
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uint32_t AdcClkFreq; /* returns ADCHCLK clock frequency expressed in Hz */
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}RCC_ClocksType;
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/** RCC registers bit mask **/
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#define HSI_FREQ_48M (48000000)
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#define HSI_FREQ_40M (40000000)
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/** Register shift macro definition **/
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#define RCC_CFG_AHBPRES_OFFSET (REG_BIT4_OFFSET)
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#define RCC_CFG_APBPRES_OFFSET (REG_BIT8_OFFSET)
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#define RCC_CFG2_ADC1MPRES_OFFSET (REG_BIT10_OFFSET)
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/* RCC Flag Mask */
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#define FLAG_Mask ((uint8_t)0x1F)
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/** Internal High Speed clock trimming **/
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#define RCC_HSITRIM_MASK (~RCC_HSICTRL_HSITRIM)
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/** Internal Low Speed clock trimming **/
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#define RCC_LSITRIM_MASK (~RCC_LSICTRL_LSITRIM)
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/** SYS_clock_source **/
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#define RCC_HSICLK_DIV_MASK (~RCC_CFG_SYSPRES)
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#define RCC_HSICLK_DIV1 (RCC_CFG_SYSPRES_DIV1)
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#define RCC_HSICLK_DIV2 (RCC_CFG_SYSPRES_DIV2)
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#define RCC_HSICLK_DIV5 (RCC_CFG_SYSPRES_DIV5)
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#define RCC_HSICLK_DIV6 (RCC_CFG_SYSPRES_DIV6)
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/** AHB_clock_source **/
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#define RCC_SYSCLK_DIV_MASK (~RCC_CFG_AHBPRES)
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#define RCC_SYSCLK_DIV1 (RCC_CFG_AHBPRES_DIV1)
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#define RCC_SYSCLK_DIV2 (RCC_CFG_AHBPRES_DIV2)
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#define RCC_SYSCLK_DIV4 (RCC_CFG_AHBPRES_DIV4)
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#define RCC_SYSCLK_DIV8 (RCC_CFG_AHBPRES_DIV8)
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#define RCC_SYSCLK_DIV12 (RCC_CFG_AHBPRES_DIV12)
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#define RCC_SYSCLK_DIV16 (RCC_CFG_AHBPRES_DIV16)
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#define RCC_SYSCLK_DIV24 (RCC_CFG_AHBPRES_DIV24)
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/** APB_clock_source **/
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#define RCC_APB_DIV_MASK (~RCC_CFG_APBPRES)
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#define RCC_HCLK_DIV1 (RCC_CFG_APBPRES_DIV1)
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#define RCC_HCLK_DIV2 (RCC_CFG_APBPRES_DIV2)
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#define RCC_HCLK_DIV4 (RCC_CFG_APBPRES_DIV4)
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#define RCC_HCLK_DIV8 (RCC_CFG_APBPRES_DIV8)
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#define RCC_HCLK_DIV16 (RCC_CFG_APBPRES_DIV16)
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/** RCC_CFGR2_Config **/
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#define RCC_TIM1_CLKSRC_MASK (~RCC_CFG2_TIM1CLKSEL)
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#define RCC_TIM1_CLKSRC_PCLK (RCC_CFG2_TIM1CLKSEL_PCLK)
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#define RCC_TIM1_CLKSRC_SYSCLK (RCC_CFG2_TIM1CLKSEL_SYSCLK)
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#define RCC_ADC1MCLK_DIV_MASK (~RCC_CFG2_ADC1MPRES)
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#define RCC_ADC1MCLK_DIV6 (RCC_CFG2_ADC1MPRES_DIV6)
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#define RCC_ADC1MCLK_DIV12 (RCC_CFG2_ADC1MPRES_DIV12)
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#define RCC_ADC1MCLK_DIV24 (RCC_CFG2_ADC1MPRES_DIV24)
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#define RCC_ADC1MCLK_DIV40 (RCC_CFG2_ADC1MPRES_DIV40)
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#define RCC_ADC1MCLK_DIV48 (RCC_CFG2_ADC1MPRES_DIV48)
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#define RCC_ADC_DIV_MASK (~RCC_CFG2_ADCPRES)
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#define RCC_ADC_DIV1 (RCC_CFG2_ADCPRES_DIV1)
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#define RCC_ADC_DIV2 (RCC_CFG2_ADCPRES_DIV2)
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#define RCC_ADC_DIV3 (RCC_CFG2_ADCPRES_DIV3)
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#define RCC_ADC_DIV4 (RCC_CFG2_ADCPRES_DIV4)
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#define RCC_ADC_DIV6 (RCC_CFG2_ADCPRES_DIV6)
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#define RCC_ADC_DIV8 (RCC_CFG2_ADCPRES_DIV8)
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#define RCC_ADC_DIV10 (RCC_CFG2_ADCPRES_DIV10)
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#define RCC_ADC_DIV12 (RCC_CFG2_ADCPRES_DIV12)
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#define RCC_ADC_DIV24 (RCC_CFG2_ADCPRES_DIV24)
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#define RCC_ADC_DIV32 (RCC_CFG2_ADCPRES_DIV32)
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#define RCC_ADC_DIV_OTHERS (RCC_CFG2_ADCPRES_OTHERS)
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#define RCC_TIM6_CLKSRC_MASK (~RCC_CFG2_TIM6CLKSEL)
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#define RCC_TIM6_CLKSRC_PCLK (RCC_CFG2_TIM6CLKSEL_PCLK)
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#define RCC_TIM6_CLKSRC_LSI (RCC_CFG2_TIM6CLKSEL_LSI)
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/** Peripheral Reset**/
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#define RCC_RST_AFIORST (RCC_PRST_AFIORST)
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#define RCC_RST_BEEPRST (RCC_PRST_BEEPRST)
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#define RCC_RST_GPIOARST (RCC_PRST_GPIOARST)
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#define RCC_RST_GPIOBRST (RCC_PRST_GPIOBRST)
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#define RCC_RST_UART1RST (RCC_PRST_UART1RST)
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#define RCC_RST_UART2RST (RCC_PRST_UART2RST)
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#define RCC_RST_I2CRST (RCC_PRST_I2CRST)
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#define RCC_RST_PWRRST (RCC_PRST_PWRRST)
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#define RCC_RST_ADCRST (RCC_PRST_ADCRST)
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#define RCC_RST_SPIRST (RCC_PRST_SPIRST)
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#define RCC_RST_TIM1RST (RCC_PRST_TIM1RST)
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#define RCC_RST_TIM3RST (RCC_PRST_TIM3RST)
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#define RCC_RST_TIM6RST (RCC_PRST_TIM6RST)
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#define RCC_RST_COMPRST (RCC_PRST_COMPRST)
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/** Peripheral Enable **/
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/** AHB_peripheral **/
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#define RCC_AHB_PERIPH_CRC (RCC_AHBPCLKEN_CRCEN)
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#define RCC_AHB_PERIPH_ADC (RCC_AHBPCLKEN_ADCEN)
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/** APB_peripheral **/
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#define RCC_APB_PERIPH_AFIO (RCC_APBPCLKEN_AFIOEN)
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#define RCC_APB_PERIPH_BEEPER (RCC_APBPCLKEN_BEEPEREN)
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#define RCC_APB_PERIPH_IOPA (RCC_APBPCLKEN_IOPAEN)
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#define RCC_APB_PERIPH_IOPB (RCC_APBPCLKEN_IOPBEN)
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#define RCC_APB_PERIPH_COMP (RCC_APBPCLKEN_COMPEN)
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#define RCC_APB_PERIPH_COMP_FILT (RCC_APBPCLKEN_COMPFILTEN)
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#define RCC_APB_PERIPH_UART1 (RCC_APBPCLKEN_UART1EN)
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#define RCC_APB_PERIPH_UART2 (RCC_APBPCLKEN_UART2EN)
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#define RCC_APB_PERIPH_I2C (RCC_APBPCLKEN_I2CEN)
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#define RCC_APB_PERIPH_PWR (RCC_APBPCLKEN_PWREN)
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#define RCC_APB_PERIPH_SPI (RCC_APBPCLKEN_SPIEN)
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#define RCC_APB_PERIPH_TIM1 (RCC_APBPCLKEN_TIM1EN)
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#define RCC_APB_PERIPH_TIM3 (RCC_APBPCLKEN_TIM3EN)
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#define RCC_APB_PERIPH_TIM6 (RCC_APBPCLKEN_TIM6EN)
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#define RCC_APB_PERIPH_IWDG (RCC_APBPCLKEN_IWDGEN)
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/** RCC_Exported_Constants **/
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/** Register shift macro definition **/
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#define RCC_FLAG_OFFSET (REG_BIT5_OFFSET)
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#define RCC_CTRL_HSITRIM_OFFSET (REG_BIT4_OFFSET)
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#define RCC_CTRL_LSITRIM_OFFSET (REG_BIT2_OFFSET)
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/** Clock_source_to_output_on_MCO_pin **/
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#define RCC_MCO_MASK (~RCC_CFG_MCO)
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#define RCC_MCO_NOCLK (RCC_CFG_MCO_NOCLK)
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#define RCC_MCO_LSI (RCC_CFG_MCO_LSI)
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#define RCC_MCO_HSI (RCC_CFG_MCO_HSI)
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#define RCC_MCO_CLK_DIV_MASK (~RCC_CFG_MCOPRES)
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#define RCC_MCO_CLK_DIV1 (RCC_CFG_MCOPRES_DIV1)
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#define RCC_MCO_CLK_DIV2 (RCC_CFG_MCOPRES_DIV2)
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#define RCC_MCO_CLK_DIV3 (RCC_CFG_MCOPRES_DIV3)
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#define RCC_MCO_CLK_DIV4 (RCC_CFG_MCOPRES_DIV4)
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#define RCC_MCO_CLK_DIV5 (RCC_CFG_MCOPRES_DIV5)
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#define RCC_MCO_CLK_DIV6 (RCC_CFG_MCOPRES_DIV6)
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#define RCC_MCO_CLK_DIV7 (RCC_CFG_MCOPRES_DIV7)
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#define RCC_MCO_CLK_DIV8 (RCC_CFG_MCOPRES_DIV8)
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#define RCC_MCO_CLK_DIV9 (RCC_CFG_MCOPRES_DIV9)
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#define RCC_MCO_CLK_DIV10 (RCC_CFG_MCOPRES_DIV10)
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#define RCC_MCO_CLK_DIV11 (RCC_CFG_MCOPRES_DIV11)
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#define RCC_MCO_CLK_DIV12 (RCC_CFG_MCOPRES_DIV12)
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#define RCC_MCO_CLK_DIV13 (RCC_CFG_MCOPRES_DIV13)
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#define RCC_MCO_CLK_DIV14 (RCC_CFG_MCOPRES_DIV14)
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#define RCC_MCO_CLK_DIV15 (RCC_CFG_MCOPRES_DIV15)
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#define RCC_MCO_CLK_DIV32 (RCC_CFG_MCOPRES_DIV32)
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/** RCC_Flag **/
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#define RCC_FLAG_HSI40MRDF ((uint8_t)0x20)
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#define RCC_FLAG_HSI48MRDF ((uint8_t)0x21)
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#define RCC_FLAG_LSIRDF ((uint8_t)0x41)
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#define RCC_FLAG_LSIDETFF ((uint8_t)0x58)
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#define RCC_FLAG_PINRST ((uint8_t)0x63)
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#define RCC_FLAG_PORRST ((uint8_t)0x64)
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#define RCC_FLAG_SFTRST ((uint8_t)0x65)
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#define RCC_FLAG_IWDGRST ((uint8_t)0x66)
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#define RCC_FLAG_LVRRST ((uint8_t)0x67)
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#define RCC_FLAG_LPWRRST ((uint8_t)0x68)
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#define RCC_FLAG_EMCCLAMPF ((uint8_t)0x6B)
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/** RCC Reset Flag clear**/
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#define RCC_REMOVE_RESET_FLAG (RCC_CTRLSTS_RMRSTF)
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void RCC_Reset(void);
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void RCC_HSI_Calibration_Value_Set(uint8_t calibration_value);
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void RCC_LSI_Calibration_Value_Set(uint8_t calibration_value);
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void RCC_Sysclk_Config(uint32_t HSI_div);
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void RCC_Hclk_Config(uint32_t sysclk_div);
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void RCC_Pclk_Config(uint32_t hclk_div);
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void RCC_TIM1_Clock_Config(uint32_t timer_clksrc);
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void RCC_ADC_1M_Clock_Config(uint32_t ADC1M_prescaler);
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void RCC_ADC_Clock_Config(uint32_t ADC_prescaler);
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void RCC_TIM6_Clock_Config(uint32_t timer_clksrc);
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void RCC_Clocks_Frequencies_Value_Get(RCC_ClocksType* RCC_clocks);
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void RCC_AHB_Peripheral_Clock_Enable(uint32_t AHB_periph);
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void RCC_AHB_Peripheral_Clock_Disable(uint32_t AHB_periph);
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void RCC_APB_Peripheral_Clock_Enable(uint32_t APB_periph);
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void RCC_APB_Peripheral_Clock_Disable(uint32_t APB_periph);
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void RCC_Peripheral_Reset(uint32_t Periph);
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void RCC_MCO_Prescaler_Config(uint32_t MCO_prescaler);
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void RCC_MCO_Source_Config(uint32_t MCO_source);
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FlagStatus RCC_Flag_Status_Get(uint8_t RCC_flag);
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void RCC_Reset_Flag_Clear(void);
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void RCC_EMC_Reset_Disable(void);
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void RCC_EMC_Reset_Enable(void);
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void RCC_EMC_Detect_Disable(void);
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void RCC_EMC_Detect_Enable(void);
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void RCC_LSI_Detect_Disable(void);
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void RCC_LSI_Detect_Enable(void);
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uint16_t RCC_LSI_Clocks_Frequencies_Get(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* __N32G003_RCC_H__ */
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