commit f5bf66b8bb3f016d37714f082055be5ca0df716d Author: evan.liu <583229071@qq.com> Date: Mon Aug 31 21:07:17 2026 +0800 第一次推送 diff --git a/EventRecorderStub.scvd b/EventRecorderStub.scvd new file mode 100644 index 0000000..2956b29 --- /dev/null +++ b/EventRecorderStub.scvd @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/Nu_Link_Driver.ini b/Nu_Link_Driver.ini new file mode 100644 index 0000000..17dcf0b --- /dev/null +++ b/Nu_Link_Driver.ini @@ -0,0 +1,885 @@ +[Version] +Nu_LinkVersion=V5.9 +[Process] +ProcessID=0x00000000 +ProcessCreationTime_L=0x00000000 +ProcessCreationTime_H=0x00000000 +NuLinkID=0x00000000 +[ChipSelect] +;ChipName= +ChipName=NUC1xx +[NUC505] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=NUC505_SPIFLASH.FLM +[NUC4xx] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=NUC400_AP_512.FLM +TraceConf0=0x00000002 +TraceConf1=0x014fb180 +TraceConf2=0x00000800 +TraceConf3=0x00000000 +TraceConf4=0x00000001 +TraceConf5=0x00000000 +[NUC2xx] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=NUC200_AP_128.FLM +[NUC1311] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=NUC1311_AP_64.FLM +[NUC126] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x2000 +ProgramAlgorithm=NUC126_AP_256.FLM +[NUC121] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=NUC121_AP_32.FLM +[NUC1xx] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=NUC100_AP_128.FLM +[NUC029] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x800 +ProgramAlgorithm=NUC029_AP_16.FLM +[NM1820] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x800 +ProgramAlgorithm=NM1820_AP_17_5.FLM +[NM1810] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x800 +ProgramAlgorithm=NM1810_AP_29_5.FLM +[NM1500] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=NM1500_AP_128.FLM +[NM1330] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=NM1330_AP_64.FLM +[NM1320] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=NM1320_AP_32.FLM +[NM1230] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=NM1230_AP_64.FLM +[NM1200] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x800 +ProgramAlgorithm=NM1200_AP_8.FLM +[NM1120] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x800 +ProgramAlgorithm=NM1120_AP_29_5.FLM +[TF5100] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=TF5100_AP_64.FLM +[NDA102] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x800 +ProgramAlgorithm=NDA102_AP_29_5.FLM +[Nano103] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=Nano103_AP_64.FLM +[Nano100] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=Nano100_AP_64.FLM +[N576] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=N576_AP_145.FLM +[N575] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=N575_AP_145.FLM +[N572] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x2000 +ProgramAlgorithm=N572Fxxx.FLM +[N571] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x2000 +ProgramAlgorithm=N571E000.FLM +[N570] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=N570_AP_64.FLM +[N569] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=N569_AP_64.FLM +[N512] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=N512_AP_64.FLM +[Mini57] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x800 +ProgramAlgorithm=Mini57_AP_29_5.FLM +[Mini51] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x800 +ProgramAlgorithm=Mini51_AP_16.FLM +[M481] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=M481_AP_512.FLM +TraceConf0=0x00000002 +TraceConf1=0x00b71b00 +TraceConf2=0x00000800 +TraceConf3=0x00000000 +TraceConf4=0x00000001 +TraceConf5=0x00000000 +[M480LD] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=M480LD_AP_256.FLM +[M479] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=M479_AP_256.FLM +[M451] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=M451_AP_256.FLM +[M251] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x2000 +ProgramAlgorithm=M251_AP_192.FLM +[M2351] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=1 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=M2351_AP_512.FLM +TraceConf0=0x00000002 +TraceConf1=0x00b71b00 +TraceConf2=0x00000800 +TraceConf3=0x00000000 +TraceConf4=0x00000001 +TraceConf5=0x00000000 +[M261] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=1 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=M261_AP_512.FLM +TraceConf0=0x00000002 +TraceConf1=0x00b71b00 +TraceConf2=0x00000800 +TraceConf3=0x00000000 +TraceConf4=0x00000001 +TraceConf5=0x00000000 +[MR63] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=1 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=MR63_AP_512.FLM +TraceConf0=0x00000002 +TraceConf1=0x00b71b00 +TraceConf2=0x00000800 +TraceConf3=0x00000000 +TraceConf4=0x00000001 +TraceConf5=0x00000000 +[M0564] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x2000 +ProgramAlgorithm=M0564_AP_256.FLM +[M0519] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=M0519_AP_128.FLM +[M0518] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=M0518_AP_64.FLM +[M05x] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x800 +ProgramAlgorithm=M0516_AP_64.FLM +[M031] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=1 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x800 +ProgramAlgorithm=M031_AP_128.FLM +[NPCX] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=NPCX_AP_512.FLM +[I94000] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm=I94000_AP_512.FLM +[ISD9300] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=ISD9300_AP_145.FLM +[I9200] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=I9200_AP_128.FLM +[ISD9xxx] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=ISD9100_AP_145.FLM +[ISD9000] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=ISD9000_AP_64.FLM +[AU9xxx] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +FlashSelect=APROM +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableFlashBreakpoint=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x1000 +ProgramAlgorithm=AU9100_AP_145.FLM +[General] +Connect=0 +Reset=Autodetect +MaxClock=1MHz +MemoryVerify=0 +IOVoltage=3300 +Erase=1 +Program=1 +Verify=1 +ResetAndRun=0 +EnableLog=0 +MemAccessWhileRun=0 +RAMForAlgorithmStart=0x20000000 +RAMForAlgorithmSize=0x4000 +ProgramAlgorithm= \ No newline at end of file diff --git a/Objects/ExtDll.iex b/Objects/ExtDll.iex new file mode 100644 index 0000000..6c0896e --- /dev/null +++ b/Objects/ExtDll.iex @@ -0,0 +1,2 @@ +[EXTDLL] +Count=0 diff --git a/Objects/test.sct b/Objects/test.sct new file mode 100644 index 0000000..9d8f1fd --- /dev/null +++ b/Objects/test.sct @@ -0,0 +1,16 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x08000000 0x00007600 { ; load region size_region + ER_IROM1 0x08000000 0x00007600 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + RW_IRAM1 0x20000000 0x00000C00 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/docs/N32G003F5S7-STB_V1.0/CN_UG_N32G003F5S7_STB_Development_Board_Hardware_User_Guide_V1.0.pdf b/docs/N32G003F5S7-STB_V1.0/CN_UG_N32G003F5S7_STB_Development_Board_Hardware_User_Guide_V1.0.pdf new file mode 100644 index 0000000..10f7489 Binary files /dev/null and b/docs/N32G003F5S7-STB_V1.0/CN_UG_N32G003F5S7_STB_Development_Board_Hardware_User_Guide_V1.0.pdf differ diff --git a/docs/N32G003F5S7-STB_V1.0/EN_UG_N32G003F5S7_STB_Development_Board_Hardware_User_Guide_V1.0.pdf b/docs/N32G003F5S7-STB_V1.0/EN_UG_N32G003F5S7_STB_Development_Board_Hardware_User_Guide_V1.0.pdf new file mode 100644 index 0000000..ba7c2ac Binary files /dev/null and b/docs/N32G003F5S7-STB_V1.0/EN_UG_N32G003F5S7_STB_Development_Board_Hardware_User_Guide_V1.0.pdf differ diff --git a/docs/N32G003F5S7-STB_V1.0/N32G003F5S7-STB_V1.0.asc b/docs/N32G003F5S7-STB_V1.0/N32G003F5S7-STB_V1.0.asc new file mode 100644 index 0000000..358cd0d --- /dev/null +++ b/docs/N32G003F5S7-STB_V1.0/N32G003F5S7-STB_V1.0.asc @@ -0,0 +1,22373 @@ +!PADS-POWERPCB-V9.0-BASIC-250L-CP936! DESIGN DATABASE ASCII FILE 1. +*PCB* GENERAL PARAMETERS OF THE PCB DESIGN + +UNITS 1 2=Inches 1=Metric 0=Mils +USERGRID 750000 750000 Space between USER grid points +MAXIMUMLAYER 2 Maximum routing layer +WORKLEVEL 2 Level items will be created on +DISPLAYLEVEL 0 toggle for displaying working level last +LAYERPAIR 1 2 Layer pair used to route connection +VIAMODE T Type of via to use when routing between layers +LINEWIDTH 381000 Width items will be created with +TEXTSIZE 3810000 381000 Height and LineWidth text will be created with +JOBTIME 40856 Amount of time spent on this PCB design +DOTGRID 750000 750000 Space between graphic dots +SCALE 4.175 Scale of window expansion +ORIGIN 516291073 366295464 User defined origin location +WINDOWCENTER 522299653 430149163 Point defining the center of the window +BACKUPTIME 5 Number of minutes between database backups +REAL WIDTH 15000 Widths greater then this are displayed real size +ALLSIGONOFF 1 All signal nets displayed on/off +REFNAMESIZE 3810000 381000 Height and LineWidth used by part ref. names +HIGHLIGHT 0 Highlight nets flag +JOBNAME N32G003F5S7-STB_V1.0.pcb +CONCOL 0 +FBGCOL 29 0 +HATCHGRID 381000 Copper plane hatching grid +TEARDROP 2713690 Teardrop tracks +THERLINEWID 571500 Copper plane thermal line width +ALLSIGFLAGS 65538 ALL Signal Flags +PSVIAGRID 750000 750000 Push & Shove Via Grid +PADFILLWID 381000 CAM finger pad fill width +THERSMDWID 381000 Copper plane thermal line width for SMD +MINHATAREA 0 Minimum hatch area +HATCHMODE 0 Hatch generation mode +HATCHDISP 1 Hatch display flag +DRILLHOLE 228600 Drill hole checking spacing +MITRERADII 0.5 1.0 1.5 2.0 2.5 3.0 3.5 +MITRETYPE 2 Mitring type +HATCHRAD 0.200000 Hatch outline smoothing radius +MITREANG 180 180 180 180 180 180 90 +HATCHANG 0 Hatch angle +THERFLAGS 11530495 Copper plane thermal line flags +DRLOVERSIZE 114300 Drill oversize for plated holes +PLANERAD 0.200000 Plane outline smoothing radius +PLANEFLAGS OUTLINE ALL Y Y Y N N Y Y N N N Y Y N Y Y N N N Plane and Test Points flags +COMPHEIGHT 0 Board Top Component Height Restriction +KPTHATCHGRID 3810000 Copper plane hatching grid +BOTCMPHEIGHT 0 Board Bottom Component Height Restriction +FANOUTGRID 1500 1500 Fanout grid +FANOUTLENGTH 9525000 Maximum fanout length +ROUTERFLAGS 83879441 Autorouter specific flags +VERIFYFLAGS 1861 Verify Design flags +FABCHKFLAGS 3967 Fabrication checks flags +ATMAXSIZE 114300 Acid Traps Maximum Size +ATMAXANGLE 161999820 Acid Traps Maximum Angle +SLMINCOPPER 114300 Slivers Minimum Copper +SLMINMASK 114300 Slivers Minimum Mask +STMINCLEAR 5 Starved Thermal Minimum Clearance +STMINSPOKES 4 Starved Thermal Minimum Spokes +TPMINWIDTH 114300 Minimum Trace Width +TPMINSIZE 114300 Mimimum Pad Size +SSMINGAP 114300 Silk Screen Over Pads Minimum Gap +SBMINGAP 114300 Solder Bridges Minimum Gap +SBLAYER 1 Solder Bridges Layer +ARPTOM 114300 Pad To Mask Annular Ring +ARPTOMLAYER 1 Pad To Mask Annular Ring Layer +ARDTOM 114300 Drill To Mask Annular Ring +ARDTOMLAYER 1 Drill To Mask Annular Ring Layer +ARDTOP 114300 Drill To Pad Annular Ring +ARDTOPLAYER 0 Drill To Pad Annular Ring Layer +VIAPSPACING 6000000 Via patterns via spacing +VIAPSHAPE 1905000 Via patterns via to shape spacing +VIAPTOTRACE -1 Via patterns via to edge spacing +VIAPFILL 1 Via patterns fill type +VIAPSHSIG NONE +VIAPSHVIA STANDARDVIA +VIAPFLAG 4 Via patterns flags +PLNSEPGAP 228600 Plane separation gap +IDFSHAPELAY 0 IDF shapes layer + +TEARDROPDATA 90 90 +*REUSE* + +*REMARK* TYPE TYPENAME +*REMARK* TIMESTAMP SECONDS +*REMARK* PART NAMING PARTNAMING +*REMARK* PART NAME +*REMARK* NET NAMING NETNAMING +*REMARK* NET MERGE NAME +*REMARK* REUSE INSTANCENM PARTNAMING NETNAMING X Y ORI GLUED + + +*TEXT* FREE TEXT + +*REMARK* XLOC YLOC ORI LEVEL HEIGHT WIDTH MIRRORED HJUST VJUST .REUSE. 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+*TESTPOINT* + + +*MISC* MISCELLANEOUS PARAMETERS + +*REMARK* PARENT_KEYWORD PARENT_VALUE +*REMARK* [ { +*REMARK* CHILD_KEYWORD CHILD_VALUE +*REMARK* [ CHILD_KEYWORD CHILD_VALUE +*REMARK* [ { +*REMARK* GRAND_CHILD_KEYWORD GRAND_CHILD_VALUE [...] +*REMARK* } ]] +*REMARK* } ] + +DOCUMENTS_LIST PARENT +{ +VERSION 1 +DOCUMENT PDF +{ +FOOTER1 0,0, +FOOTER2 0,1, +FOOTER3 0,2, +HEADER1 0,0, +HEADER2 0,1, +HEADER3 0,2, +CONFIG_NAME PDF Document +PAGE_SIZE 8,0,314972699,445770000 +COLOR_MODE 1 +BOOKMARK_MODE 2,1,1,1 +STROKE_FONT ,0,0,0 +POPUPS 1,0 +PAGE 1 +{ +PAGE_NAME Silkscreen Top +BOARD_OUTLINE 1 +CONNECTIONS 0 +THROUGH_HOLE 0,0 +MIRROR_IMAGE 0 +MIRROR_REFDES 0 +OFFSET 0,0 +SCALE 1 +JUSTIFICATION 2 +LAYER 126 +{ +LAYER_NUMBER 126 +SMD_PADS 0 +THORUGH_HOLE_PADS 0 +TRACES 0 +LINES 1 +VIAS 0 +COPPERS 0 +HATCH_OUTLINES 0 +POUR_OUTLINES 0 +KEEPOUTS 1 +REF_DES 1 +PART_TYPES 0 +TEXTS 1 +ATTRIBUTES 0 +COMPONENT_OUTLINES_TOP 1 +COMPONENT_OUTLINES_BOTTOM 0 +TEST_POINTS 0 +PARTIAL_DRILLS 0 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: +{ +ROUTE 0 +VIA 0 +PAD 0 +COPPER 0 +2DLINE 0 +TEXT 0 +ERROR 0 +TOPCOMPONENT 0 +BOTTOMCOMPONENT 0 +REFDES 0 +PARTTYPE 0 +ATTRIBUTE 0 +KEEPOUT 0 +TOPPLACEMENT 0 +BOTTOMPLACEMENT 0 +} +LAYER_THICKNESS 0 +COPPER_THICKNESS 0 +DIELECTRIC 3.300000 +COST 0 +} +LAYER 236 +{ +LAYER_NAME Layer_236 +LAYER_TYPE UNASSIGNED +PLANE NONE +ROUTING_DIRECTION NO_PREFERENCE +COLORS : +{ +ROUTE 0 +VIA 0 +PAD 0 +COPPER 0 +2DLINE 0 +TEXT 0 +ERROR 0 +TOPCOMPONENT 0 +BOTTOMCOMPONENT 0 +REFDES 0 +PARTTYPE 0 +ATTRIBUTE 0 +KEEPOUT 0 +TOPPLACEMENT 0 +BOTTOMPLACEMENT 0 +} +LAYER_THICKNESS 0 +COPPER_THICKNESS 0 +DIELECTRIC 3.300000 +COST 0 +} +LAYER 237 +{ +LAYER_NAME Layer_237 +LAYER_TYPE UNASSIGNED +PLANE NONE +ROUTING_DIRECTION NO_PREFERENCE +COLORS : +{ +ROUTE 0 +VIA 0 +PAD 0 +COPPER 0 +2DLINE 0 +TEXT 0 +ERROR 0 +TOPCOMPONENT 0 +BOTTOMCOMPONENT 0 +REFDES 0 +PARTTYPE 0 +ATTRIBUTE 0 +KEEPOUT 0 +TOPPLACEMENT 0 +BOTTOMPLACEMENT 0 +} +LAYER_THICKNESS 0 +COPPER_THICKNESS 0 +DIELECTRIC 3.300000 +COST 0 +} +LAYER 238 +{ +LAYER_NAME Layer_238 +LAYER_TYPE UNASSIGNED +PLANE NONE +ROUTING_DIRECTION NO_PREFERENCE +COLORS : +{ +ROUTE 0 +VIA 0 +PAD 0 +COPPER 0 +2DLINE 0 +TEXT 0 +ERROR 0 +TOPCOMPONENT 0 +BOTTOMCOMPONENT 0 +REFDES 0 +PARTTYPE 0 +ATTRIBUTE 0 +KEEPOUT 0 +TOPPLACEMENT 0 +BOTTOMPLACEMENT 0 +} +LAYER_THICKNESS 0 +COPPER_THICKNESS 0 +DIELECTRIC 3.300000 +COST 0 +} +LAYER 239 +{ +LAYER_NAME Layer_239 +LAYER_TYPE UNASSIGNED +PLANE NONE +ROUTING_DIRECTION NO_PREFERENCE +COLORS : +{ +ROUTE 0 +VIA 0 +PAD 0 +COPPER 0 +2DLINE 0 +TEXT 0 +ERROR 0 +TOPCOMPONENT 0 +BOTTOMCOMPONENT 0 +REFDES 0 +PARTTYPE 0 +ATTRIBUTE 0 +KEEPOUT 0 +TOPPLACEMENT 0 +BOTTOMPLACEMENT 0 +} +LAYER_THICKNESS 0 +COPPER_THICKNESS 0 +DIELECTRIC 3.300000 +COST 0 +} +LAYER 240 +{ +LAYER_NAME Layer_240 +LAYER_TYPE UNASSIGNED +PLANE NONE +ROUTING_DIRECTION NO_PREFERENCE +COLORS : +{ +ROUTE 0 +VIA 0 +PAD 0 +COPPER 0 +2DLINE 0 +TEXT 0 +ERROR 0 +TOPCOMPONENT 0 +BOTTOMCOMPONENT 0 +REFDES 0 +PARTTYPE 0 +ATTRIBUTE 0 +KEEPOUT 0 +TOPPLACEMENT 0 +BOTTOMPLACEMENT 0 +} +LAYER_THICKNESS 0 +COPPER_THICKNESS 0 +DIELECTRIC 3.300000 +COST 0 +} +LAYER 241 +{ +LAYER_NAME Layer_241 +LAYER_TYPE UNASSIGNED +PLANE NONE +ROUTING_DIRECTION NO_PREFERENCE +COLORS : +{ +ROUTE 0 +VIA 0 +PAD 0 +COPPER 0 +2DLINE 0 +TEXT 0 +ERROR 0 +TOPCOMPONENT 0 +BOTTOMCOMPONENT 0 +REFDES 0 +PARTTYPE 0 +ATTRIBUTE 0 +KEEPOUT 0 +TOPPLACEMENT 0 +BOTTOMPLACEMENT 0 +} +LAYER_THICKNESS 0 +COPPER_THICKNESS 0 +DIELECTRIC 3.300000 +COST 0 +} +LAYER 242 +{ +LAYER_NAME Layer_242 +LAYER_TYPE UNASSIGNED +PLANE NONE +ROUTING_DIRECTION NO_PREFERENCE +COLORS : +{ +ROUTE 0 +VIA 0 +PAD 0 +COPPER 0 +2DLINE 0 +TEXT 0 +ERROR 0 +TOPCOMPONENT 0 +BOTTOMCOMPONENT 0 +REFDES 0 +PARTTYPE 0 +ATTRIBUTE 0 +KEEPOUT 0 +TOPPLACEMENT 0 +BOTTOMPLACEMENT 0 +} +LAYER_THICKNESS 0 +COPPER_THICKNESS 0 +DIELECTRIC 3.300000 +COST 0 +} +LAYER 243 +{ +LAYER_NAME Layer_243 +LAYER_TYPE UNASSIGNED +PLANE NONE +ROUTING_DIRECTION NO_PREFERENCE +COLORS : +{ +ROUTE 0 +VIA 0 +PAD 0 +COPPER 0 +2DLINE 0 +TEXT 0 +ERROR 0 +TOPCOMPONENT 0 +BOTTOMCOMPONENT 0 +REFDES 0 +PARTTYPE 0 +ATTRIBUTE 0 +KEEPOUT 0 +TOPPLACEMENT 0 +BOTTOMPLACEMENT 0 +} +LAYER_THICKNESS 0 +COPPER_THICKNESS 0 +DIELECTRIC 3.300000 +COST 0 +} +LAYER 244 +{ +LAYER_NAME Layer_244 +LAYER_TYPE UNASSIGNED +PLANE NONE +ROUTING_DIRECTION NO_PREFERENCE +COLORS : +{ +ROUTE 0 +VIA 0 +PAD 0 +COPPER 0 +2DLINE 0 +TEXT 0 +ERROR 0 +TOPCOMPONENT 0 +BOTTOMCOMPONENT 0 +REFDES 0 +PARTTYPE 0 +ATTRIBUTE 0 +KEEPOUT 0 +TOPPLACEMENT 0 +BOTTOMPLACEMENT 0 +} +LAYER_THICKNESS 0 +COPPER_THICKNESS 0 +DIELECTRIC 3.300000 +COST 0 +} +LAYER 245 +{ +LAYER_NAME Layer_245 +LAYER_TYPE UNASSIGNED +PLANE NONE +ROUTING_DIRECTION NO_PREFERENCE +COLORS : +{ +ROUTE 0 +VIA 0 +PAD 0 +COPPER 0 +2DLINE 0 +TEXT 0 +ERROR 0 +TOPCOMPONENT 0 +BOTTOMCOMPONENT 0 +REFDES 0 +PARTTYPE 0 +ATTRIBUTE 0 +KEEPOUT 0 +TOPPLACEMENT 0 +BOTTOMPLACEMENT 0 +} +LAYER_THICKNESS 0 +COPPER_THICKNESS 0 +DIELECTRIC 3.300000 +COST 0 +} +LAYER 246 +{ +LAYER_NAME Layer_246 +LAYER_TYPE UNASSIGNED +PLANE NONE +ROUTING_DIRECTION NO_PREFERENCE +COLORS : +{ +ROUTE 0 +VIA 0 +PAD 0 +COPPER 0 +2DLINE 0 +TEXT 0 +ERROR 0 +TOPCOMPONENT 0 +BOTTOMCOMPONENT 0 +REFDES 0 +PARTTYPE 0 +ATTRIBUTE 0 +KEEPOUT 0 +TOPPLACEMENT 0 +BOTTOMPLACEMENT 0 +} +LAYER_THICKNESS 0 +COPPER_THICKNESS 0 +DIELECTRIC 3.300000 +COST 0 +} +LAYER 247 +{ +LAYER_NAME Layer_247 +LAYER_TYPE UNASSIGNED +PLANE NONE +ROUTING_DIRECTION NO_PREFERENCE +COLORS : +{ +ROUTE 0 +VIA 0 +PAD 0 +COPPER 0 +2DLINE 0 +TEXT 0 +ERROR 0 +TOPCOMPONENT 0 +BOTTOMCOMPONENT 0 +REFDES 0 +PARTTYPE 0 +ATTRIBUTE 0 +KEEPOUT 0 +TOPPLACEMENT 0 +BOTTOMPLACEMENT 0 +} +LAYER_THICKNESS 0 +COPPER_THICKNESS 0 +DIELECTRIC 3.300000 +COST 0 +} +LAYER 248 +{ +LAYER_NAME Layer_248 +LAYER_TYPE UNASSIGNED +PLANE NONE +ROUTING_DIRECTION NO_PREFERENCE +COLORS : +{ +ROUTE 0 +VIA 0 +PAD 0 +COPPER 0 +2DLINE 0 +TEXT 0 +ERROR 0 +TOPCOMPONENT 0 +BOTTOMCOMPONENT 0 +REFDES 0 +PARTTYPE 0 +ATTRIBUTE 0 +KEEPOUT 0 +TOPPLACEMENT 0 +BOTTOMPLACEMENT 0 +} +LAYER_THICKNESS 0 +COPPER_THICKNESS 0 +DIELECTRIC 3.300000 +COST 0 +} +LAYER 249 +{ +LAYER_NAME Layer_249 +LAYER_TYPE UNASSIGNED +PLANE NONE +ROUTING_DIRECTION NO_PREFERENCE +COLORS : +{ +ROUTE 0 +VIA 0 +PAD 0 +COPPER 0 +2DLINE 0 +TEXT 0 +ERROR 0 +TOPCOMPONENT 0 +BOTTOMCOMPONENT 0 +REFDES 0 +PARTTYPE 0 +ATTRIBUTE 0 +KEEPOUT 0 +TOPPLACEMENT 0 +BOTTOMPLACEMENT 0 +} +LAYER_THICKNESS 0 +COPPER_THICKNESS 0 +DIELECTRIC 3.300000 +COST 0 +} +LAYER 250 +{ +LAYER_NAME Layer_250 +LAYER_TYPE UNASSIGNED +PLANE NONE +ROUTING_DIRECTION NO_PREFERENCE +COLORS : +{ +ROUTE 0 +VIA 0 +PAD 0 +COPPER 0 +2DLINE 0 +TEXT 0 +ERROR 0 +TOPCOMPONENT 0 +BOTTOMCOMPONENT 0 +REFDES 0 +PARTTYPE 0 +ATTRIBUTE 0 +KEEPOUT 0 +TOPPLACEMENT 0 +BOTTOMPLACEMENT 0 +} +LAYER_THICKNESS 0 +COPPER_THICKNESS 0 +DIELECTRIC 3.300000 +COST 0 +} +} +SELECTABILITY DATA +{ +PARTS Y +PINS Y +TRACES Y +VIAS Y +TACKS Y +UNROUTED Y +EDGES Y +NODES Y +SHAPES Y +DIMENSIONS Y +TEXT Y +AREA_PARTS Y +AREA_PINS Y +AREA_TRACES Y +AREA_VIAS Y +AREA_TACKS Y +AREA_UNROUTED Y +AREA_EDGES Y +AREA_NODES Y +AREA_SHAPES Y +AREA_DIMENSIONS Y +AREA_TEXT Y +} +VISIBILITY DATA +{ +PADS Y +TRACKS Y +VIAS Y +COPPER Y +LINES Y +TEXT Y +ERRORS Y +CLUSTER Y +TOP_COMPONENT Y +BOTTOM_COMPONENT Y +REFDES Y +KEEPOUTS Y +SELECTION_COLOR 15 +HIGHLIGHT_COLOR 14 +FIXED_COLOR 3 +PINNUM Y +PINNUM_TOP_COLOR 14 +PINNUM_BOTTOM_COLOR 16 +FONT_FACE +{ +} +} + +*MISC* MISCELLANEOUS PARAMETERS + +*REMARK* PARENT_KEYWORD PARENT_VALUE +*REMARK* [ { +*REMARK* CHILD_KEYWORD CHILD_VALUE +*REMARK* [ CHILD_KEYWORD CHILD_VALUE +*REMARK* [ { +*REMARK* GRAND_CHILD_KEYWORD GRAND_CHILD_VALUE [...] +*REMARK* } ]] +*REMARK* } ] + +RULES_SECTION PARENT +{ +NET_CLASS DATA +GROUP DATA +DESIGN RULES +{ +RULE_SET (1) +{ +FOR : +{ +DEFAULT : +} +AGAINST : +{ +DEFAULT : +} +LAYER 0 +CLEARANCE_RULE : +{ +TRACK_TO_TRACK 228600 +VIA_TO_TRACK 228600 +VIA_TO_VIA 228600 +PAD_TO_TRACK 228600 +PAD_TO_VIA 228600 +PAD_TO_PAD 228600 +SMD_TO_TRACK 228600 +SMD_TO_VIA 228600 +SMD_TO_PAD 228600 +SMD_TO_SMD 228600 +COPPER_TO_TRACK 381000 +COPPER_TO_VIA 381000 +COPPER_TO_PAD 381000 +COPPER_TO_SMD 381000 +COPPER_TO_COPPER 381000 +TEXT_TO_TRACK 228600 +TEXT_TO_VIA 228600 +TEXT_TO_PAD 228600 +TEXT_TO_SMD 228600 +OUTLINE_TO_TRACK 495300 +OUTLINE_TO_VIA 495300 +OUTLINE_TO_PAD 495300 +OUTLINE_TO_SMD 495300 +OUTLINE_TO_COPPER 495300 +DRILL_TO_TRACK 266700 +DRILL_TO_VIA 266700 +DRILL_TO_PAD 266700 +DRILL_TO_SMD 266700 +DRILL_TO_COPPER 266700 +SAME_NET_SMD_TO_VIA 228600 +SAME_NET_SMD_TO_CRN 228600 +SAME_NET_VIA_TO_VIA 228600 +SAME_NET_PAD_TO_CRN 228600 +MIN_TRACK_WIDTH 228600 +REC_TRACK_WIDTH 228600 +MAX_TRACK_WIDTH 1143000 +DRILL_TO_DRILL 228600 +BODY_TO_BODY 228600 +SAME_NET_TRACK_TO_CRN 228600 +} +} +RULE_SET (2) +{ +FOR : +{ +NET $$$18547 +NET $$$29264 +NET PB0/RST +} +AGAINST : +{ +DEFAULT : +} +LAYER 0 +CLEARANCE_RULE : +{ +TRACK_TO_TRACK 228600 +VIA_TO_TRACK 228600 +VIA_TO_VIA 228600 +PAD_TO_TRACK 228600 +PAD_TO_VIA 228600 +PAD_TO_PAD 228600 +SMD_TO_TRACK 228600 +SMD_TO_VIA 228600 +SMD_TO_PAD 228600 +SMD_TO_SMD 228600 +COPPER_TO_TRACK 762000 +COPPER_TO_VIA 762000 +COPPER_TO_PAD 762000 +COPPER_TO_SMD 762000 +COPPER_TO_COPPER 762000 +TEXT_TO_TRACK 228600 +TEXT_TO_VIA 228600 +TEXT_TO_PAD 228600 +TEXT_TO_SMD 228600 +OUTLINE_TO_TRACK 762000 +OUTLINE_TO_VIA 762000 +OUTLINE_TO_PAD 762000 +OUTLINE_TO_SMD 762000 +OUTLINE_TO_COPPER 762000 +DRILL_TO_TRACK 266700 +DRILL_TO_VIA 266700 +DRILL_TO_PAD 266700 +DRILL_TO_SMD 266700 +DRILL_TO_COPPER 266700 +SAME_NET_SMD_TO_VIA 228600 +SAME_NET_SMD_TO_CRN 228600 +SAME_NET_VIA_TO_VIA 228600 +SAME_NET_PAD_TO_CRN 228600 +MIN_TRACK_WIDTH 228600 +REC_TRACK_WIDTH 228600 +MAX_TRACK_WIDTH 1143000 +DRILL_TO_DRILL 228600 +BODY_TO_BODY 228600 +SAME_NET_TRACK_TO_CRN 228600 +} +} +RULE_SET (3) +{ +FOR : +{ +DEFAULT : +} +AGAINST : +{ +DEFAULT : +} +LAYER 0 +HIGH_SPEED_RULE : +{ +MIN_LENGTH 0 +MAX_LENGTH 1905000000 +STUB_LENGTH 0 +PARALLEL_LENGTH 38100000 +PARALLEL_GAP 7620000 +TANDEM_LENGTH 38100000 +TANDEM_GAP 7620000 +MIN_DELAY 0.000000 +MAX_DELAY 10.000000 +MIN_CAPACITANCE 0.000000 +MAX_CAPACITANCE 10.000000 +MIN_IMPEDANCE 50.000000 +MAX_IMPEDANCE 150.000000 +SHIELD_NET * +SHIELD_GAP 7620000 +MATCH_LENGTH_TOLERANCE 7620000 +} +} +RULE_SET (4) +{ +FOR : +{ +DEFAULT : +} +AGAINST : +{ +DEFAULT : +} +LAYER 0 +ROUTE_RULE : +{ +LENGTH_MINIMIZATION_TYPE 1 +VIA_SHARE Y +TRACE_SHARE Y +AUTO_ROUTE Y +RIPUP Y +SHOVE Y +ROUTE_PRIORITY 3 +MAX_NUMBER_OF_VIAS -1 +VALID_LAYER 1 +VALID_LAYER 2 +VALID_VIA_TYPE STANDARDVIA +VALID_VIA_TYPE VIA0812 +VALID_VIA_TYPE VIA0508 +} +} +RULE_SET (5) +{ +FOR : +{ +CONNECTION S6.2,R8.1 +} +AGAINST : +{ +DEFAULT : +} +LAYER 0 +ROUTE_RULE : +{ +LENGTH_MINIMIZATION_TYPE 1 +AUTO_ROUTE Y +RIPUP Y +SHOVE Y +ROUTE_PRIORITY 3 +MAX_NUMBER_OF_VIAS -1 +VALID_LAYER 1 +VALID_LAYER 2 +VALID_VIA_TYPE STANDARDVIA +VALID_VIA_TYPE VIA0508 +} +} +RULE_SET (6) +{ +FOR : +{ +CONNECTION J5.14,D5.1 +CONNECTION J5.13,D5.1 +} +AGAINST : +{ +DEFAULT : +} +LAYER 0 +ROUTE_RULE : +{ +LENGTH_MINIMIZATION_TYPE 1 +AUTO_ROUTE Y +RIPUP Y +SHOVE Y +ROUTE_PRIORITY 3 +MAX_NUMBER_OF_VIAS -1 +VALID_LAYER 1 +VALID_LAYER 2 +VALID_VIA_TYPE STANDARDVIA +VALID_VIA_TYPE VIA0812 +VALID_VIA_TYPE VIA0508 +} +} +} +} + +*MISC* MISCELLANEOUS PARAMETERS + +*REMARK* PARENT_KEYWORD PARENT_VALUE +*REMARK* [ { +*REMARK* CHILD_KEYWORD CHILD_VALUE +*REMARK* [ CHILD_KEYWORD CHILD_VALUE +*REMARK* [ { +*REMARK* GRAND_CHILD_KEYWORD GRAND_CHILD_VALUE [...] +*REMARK* } ]] +*REMARK* } ] + +CAM_SECTION PARENT +{ +CAM_VERSION V2007.0 +CAM_DOC_LIST PARENT +{ +CAM_DOC_DIRECTORY N32G4XM_STB_V1.1 +CAM_DOC_NAME (art001.pho) +{ +DOC_PLOT_TYPE Routing +DOC_DEVICE_TYPE Photo +DOC_OUTPUT_FILE art001.pho +DOC_LAYER_NAMES Top +DOC_LAYER_NUMBERS 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +DOC_LAYER_TYPES Component +DOC_FABRICATION_LAYER_NUMBER 1 +DOC_SCALE 1 1 +DOC_ORIENTATION 0 +DOC_MIRROR N +DOC_JUSTIFICATION OO +DOC_OFFSET 150000000 150000000 +DOC_CLIP 0 +DOC_FIT_OUTPUT 0 +DOC_NO_PLANE_THERMALS 0 +DOC_ASSEMBLY_OPTION "" +DOC_CUSTOM_THERMALS 0 +DOC_BOARD Black +DOC_CONNECTIONS None +DOC_OUTLINES None None +DOC_SLOTS None None +DOC_REFDES None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_PARTTYPES None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_ATTRIBUTES None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_TESTPOINTS None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_OUTLINE_LAYERS N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N +DOC_PADS Black None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_VIAS Black None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_ROUTES Black None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_COPPER Black None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_LINES Black None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_TEXT Black None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_KEEPOUTS None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_PINS_ADV 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +DOC_PAD_OVERSIZE 0 +DOC_PLOT_JOBNAME Y +DOC_PLOT_OLE N +DOC_MIRROR_REFS N +DOC_SUPRESS_PREFIXES "" +DOC_PLOT_QUALITY Filled +DOC_DRILL_CHART Y +DOC_CHART_OFFSET 0 0 +DOC_SUPRESS_EXCLUDE_PADS Y +DOC_COLOR_BY_NET 0 +} +CAM_DOC_NAME (art002.pho) +{ +DOC_PLOT_TYPE Routing +DOC_DEVICE_TYPE Photo +DOC_OUTPUT_FILE art002.pho +DOC_LAYER_NAMES Bottom +DOC_LAYER_NUMBERS 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +DOC_LAYER_TYPES Component +DOC_FABRICATION_LAYER_NUMBER 2 +DOC_SCALE 1 1 +DOC_ORIENTATION 0 +DOC_MIRROR N +DOC_JUSTIFICATION OO +DOC_OFFSET 150000000 150000000 +DOC_CLIP 0 +DOC_FIT_OUTPUT 0 +DOC_NO_PLANE_THERMALS 0 +DOC_ASSEMBLY_OPTION "" +DOC_CUSTOM_THERMALS 0 +DOC_BOARD Black +DOC_CONNECTIONS None +DOC_OUTLINES None None +DOC_SLOTS None None +DOC_REFDES None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_PARTTYPES None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_ATTRIBUTES None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_TESTPOINTS None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_OUTLINE_LAYERS N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N +DOC_PADS Black None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_VIAS Black None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_ROUTES Black None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_COPPER Black None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_LINES None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_TEXT None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_KEEPOUTS None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_PINS_ADV 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +DOC_PAD_OVERSIZE 0 +DOC_PLOT_JOBNAME Y +DOC_PLOT_OLE N +DOC_MIRROR_REFS N +DOC_SUPRESS_PREFIXES "" +DOC_PLOT_QUALITY Filled +DOC_DRILL_CHART Y +DOC_CHART_OFFSET 0 0 +DOC_SUPRESS_EXCLUDE_PADS Y +DOC_COLOR_BY_NET 0 +} +CAM_DOC_NAME TOPSM.pho +{ +DOC_PLOT_TYPE Solder_Mask +DOC_DEVICE_TYPE Photo +DOC_OUTPUT_FILE TOPSM.pho +DOC_LAYER_NAMES Top Solder_Mask_Top +DOC_LAYER_NUMBERS 1 121 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +DOC_LAYER_TYPES Component SilkScreen +DOC_FABRICATION_LAYER_NUMBER 121 +DOC_SCALE 1 1 +DOC_ORIENTATION 0 +DOC_MIRROR N +DOC_JUSTIFICATION OO +DOC_OFFSET 150000000 150000000 +DOC_CLIP 0 +DOC_FIT_OUTPUT 0 +DOC_NO_PLANE_THERMALS 0 +DOC_ASSEMBLY_OPTION "" +DOC_CUSTOM_THERMALS 0 +DOC_BOARD Black +DOC_CONNECTIONS None +DOC_OUTLINES None None +DOC_SLOTS None None +DOC_REFDES None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_PARTTYPES None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_ATTRIBUTES None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_TESTPOINTS Black Black None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_OUTLINE_LAYERS N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N +DOC_PADS Black Black None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_VIAS None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_ROUTES None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_COPPER None Black None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_LINES None Black None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_TEXT None Black None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_KEEPOUTS None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_PINS_ADV 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +DOC_PAD_OVERSIZE 381000 +DOC_PLOT_JOBNAME Y +DOC_PLOT_OLE N +DOC_MIRROR_REFS N +DOC_SUPRESS_PREFIXES T1,T2 +DOC_PLOT_QUALITY Filled +DOC_DRILL_CHART Y +DOC_CHART_OFFSET 0 0 +DOC_SUPRESS_EXCLUDE_PADS Y +DOC_COLOR_BY_NET 0 +} +CAM_DOC_NAME BOTSM.pho +{ +DOC_PLOT_TYPE Solder_Mask +DOC_DEVICE_TYPE Photo +DOC_OUTPUT_FILE BOTSM.pho +DOC_LAYER_NAMES Bottom Solder_Mask_Bottom +DOC_LAYER_NUMBERS 2 128 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +DOC_LAYER_TYPES Component SilkScreen +DOC_FABRICATION_LAYER_NUMBER 128 +DOC_SCALE 1 1 +DOC_ORIENTATION 0 +DOC_MIRROR N +DOC_JUSTIFICATION OO +DOC_OFFSET 150000000 150000000 +DOC_CLIP 0 +DOC_FIT_OUTPUT 0 +DOC_NO_PLANE_THERMALS 0 +DOC_ASSEMBLY_OPTION "" +DOC_CUSTOM_THERMALS 0 +DOC_BOARD Black +DOC_CONNECTIONS None +DOC_OUTLINES None None +DOC_SLOTS None None +DOC_REFDES None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_PARTTYPES None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_ATTRIBUTES None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_TESTPOINTS None Black None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_OUTLINE_LAYERS N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N +DOC_PADS Black Black None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_VIAS None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_ROUTES None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_COPPER None Black None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_LINES None Black None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_TEXT None Black None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_KEEPOUTS None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_PINS_ADV 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +DOC_PAD_OVERSIZE 381000 +DOC_PLOT_JOBNAME Y +DOC_PLOT_OLE N +DOC_MIRROR_REFS N +DOC_SUPRESS_PREFIXES "" +DOC_PLOT_QUALITY Filled +DOC_DRILL_CHART Y +DOC_CHART_OFFSET 0 0 +DOC_SUPRESS_EXCLUDE_PADS N +DOC_COLOR_BY_NET 0 +} +CAM_DOC_NAME TOPPM.pho +{ +DOC_PLOT_TYPE Paste_Mask +DOC_DEVICE_TYPE Photo +DOC_OUTPUT_FILE TOPPM.pho +DOC_LAYER_NAMES Top Paste_Mask_Top +DOC_LAYER_NUMBERS 1 123 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +DOC_LAYER_TYPES Component Drill +DOC_FABRICATION_LAYER_NUMBER 123 +DOC_SCALE 1 1 +DOC_ORIENTATION 0 +DOC_MIRROR N +DOC_JUSTIFICATION OO +DOC_OFFSET 150000000 150000000 +DOC_CLIP 0 +DOC_FIT_OUTPUT 0 +DOC_NO_PLANE_THERMALS 0 +DOC_ASSEMBLY_OPTION "" +DOC_CUSTOM_THERMALS 0 +DOC_BOARD Black +DOC_CONNECTIONS None +DOC_OUTLINES None None +DOC_SLOTS None None +DOC_REFDES None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_PARTTYPES None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_ATTRIBUTES None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_TESTPOINTS None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_OUTLINE_LAYERS N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N +DOC_PADS Black Black None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_VIAS None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_ROUTES None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_COPPER None Black None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_LINES None Black None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_TEXT None Black None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_KEEPOUTS None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_PINS_ADV 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +DOC_PAD_OVERSIZE 0 +DOC_PLOT_JOBNAME Y +DOC_PLOT_OLE N +DOC_MIRROR_REFS N +DOC_SUPRESS_PREFIXES T1,T2,S1,S2 +DOC_PLOT_QUALITY Filled +DOC_DRILL_CHART Y +DOC_CHART_OFFSET 0 0 +DOC_SUPRESS_EXCLUDE_PADS Y +DOC_COLOR_BY_NET 0 +} +CAM_DOC_NAME BOTPM.pho +{ +DOC_PLOT_TYPE Paste_Mask +DOC_DEVICE_TYPE Photo +DOC_OUTPUT_FILE BOTPM.pho +DOC_LAYER_NAMES Bottom Paste_Mask_Bottom +DOC_LAYER_NUMBERS 2 122 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +DOC_LAYER_TYPES Component Drill +DOC_FABRICATION_LAYER_NUMBER 122 +DOC_SCALE 1 1 +DOC_ORIENTATION 0 +DOC_MIRROR N +DOC_JUSTIFICATION OO +DOC_OFFSET 150000000 150000000 +DOC_CLIP 0 +DOC_FIT_OUTPUT 0 +DOC_NO_PLANE_THERMALS 0 +DOC_ASSEMBLY_OPTION "" +DOC_CUSTOM_THERMALS 0 +DOC_BOARD Black +DOC_CONNECTIONS None +DOC_OUTLINES None None +DOC_SLOTS None None +DOC_REFDES None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_PARTTYPES None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_ATTRIBUTES None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_TESTPOINTS None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_OUTLINE_LAYERS N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N +DOC_PADS Black Black None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_VIAS None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_ROUTES None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_COPPER None Black None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_LINES None Black None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_TEXT None Black None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_KEEPOUTS None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_PINS_ADV 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +DOC_PAD_OVERSIZE 0 +DOC_PLOT_JOBNAME Y +DOC_PLOT_OLE N +DOC_MIRROR_REFS N +DOC_SUPRESS_PREFIXES "" +DOC_PLOT_QUALITY Filled +DOC_DRILL_CHART Y +DOC_CHART_OFFSET 0 0 +DOC_SUPRESS_EXCLUDE_PADS Y +DOC_COLOR_BY_NET 0 +} +CAM_DOC_NAME TOPSILK.pho +{ +DOC_PLOT_TYPE Silkscreen +DOC_DEVICE_TYPE Photo +DOC_OUTPUT_FILE TOPSILK.pho +DOC_LAYER_NAMES Top Silkscreen_Top +DOC_LAYER_NUMBERS 1 126 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +DOC_LAYER_TYPES Component Plane +DOC_FABRICATION_LAYER_NUMBER 126 +DOC_SCALE 1 1 +DOC_ORIENTATION 0 +DOC_MIRROR N +DOC_JUSTIFICATION OO +DOC_OFFSET 150000000 150000000 +DOC_CLIP 0 +DOC_FIT_OUTPUT 0 +DOC_NO_PLANE_THERMALS 0 +DOC_ASSEMBLY_OPTION "" +DOC_CUSTOM_THERMALS 0 +DOC_BOARD Black +DOC_CONNECTIONS None +DOC_OUTLINES Black None +DOC_SLOTS None None +DOC_REFDES Black Black None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_PARTTYPES None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_ATTRIBUTES None Black None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_TESTPOINTS None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_OUTLINE_LAYERS Y Y N N N N N N N N N N N N N N N N N N N N N N N N N N N N +DOC_PADS None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_VIAS None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_ROUTES None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_COPPER None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_LINES None Black None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_TEXT Black Black None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_KEEPOUTS None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_PINS_ADV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +DOC_PAD_OVERSIZE 0 +DOC_PLOT_JOBNAME Y +DOC_PLOT_OLE N +DOC_MIRROR_REFS N +DOC_SUPRESS_PREFIXES "" +DOC_PLOT_QUALITY Filled +DOC_DRILL_CHART Y +DOC_CHART_OFFSET 0 0 +DOC_SUPRESS_EXCLUDE_PADS Y +DOC_COLOR_BY_NET 0 +} +CAM_DOC_NAME BOTSILK +{ +DOC_PLOT_TYPE Silkscreen +DOC_DEVICE_TYPE Photo +DOC_OUTPUT_FILE BOTSILK.pho +DOC_LAYER_NAMES Bottom Silkscreen_Bottom +DOC_LAYER_NUMBERS 2 129 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +DOC_LAYER_TYPES Component Plane +DOC_FABRICATION_LAYER_NUMBER 129 +DOC_SCALE 1 1 +DOC_ORIENTATION 0 +DOC_MIRROR N +DOC_JUSTIFICATION OO +DOC_OFFSET 150000000 150000000 +DOC_CLIP 0 +DOC_FIT_OUTPUT 0 +DOC_NO_PLANE_THERMALS 0 +DOC_ASSEMBLY_OPTION "" +DOC_CUSTOM_THERMALS 0 +DOC_BOARD Black +DOC_CONNECTIONS None +DOC_OUTLINES None Black +DOC_SLOTS None None +DOC_REFDES Black Black None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_PARTTYPES None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_ATTRIBUTES None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_TESTPOINTS None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_OUTLINE_LAYERS Y Y N N N N N N N N N N N N N N N N N N N N N N N N N N N N +DOC_PADS None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_VIAS None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_ROUTES None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_COPPER None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_LINES None Black None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_TEXT Black Black None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_KEEPOUTS None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_PINS_ADV 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +DOC_PAD_OVERSIZE 0 +DOC_PLOT_JOBNAME Y +DOC_PLOT_OLE N +DOC_MIRROR_REFS N +DOC_SUPRESS_PREFIXES "" +DOC_PLOT_QUALITY Filled +DOC_DRILL_CHART Y +DOC_CHART_OFFSET 0 0 +DOC_SUPRESS_EXCLUDE_PADS N +DOC_COLOR_BY_NET 0 +} +CAM_DOC_NAME Drill +{ +DOC_PLOT_TYPE Drill_Drawing +DOC_DEVICE_TYPE Photo +DOC_OUTPUT_FILE dd001124.pho +DOC_LAYER_NAMES Top Drill_Drawing +DOC_LAYER_NUMBERS 1 124 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +DOC_LAYER_TYPES Component Routing +DOC_FABRICATION_LAYER_NUMBER 0 +DOC_SCALE 1 1 +DOC_ORIENTATION 0 +DOC_MIRROR N +DOC_JUSTIFICATION OO +DOC_OFFSET 150000000 150000000 +DOC_CLIP 0 +DOC_FIT_OUTPUT 0 +DOC_NO_PLANE_THERMALS 0 +DOC_ASSEMBLY_OPTION "" +DOC_CUSTOM_THERMALS 0 +DOC_BOARD Black +DOC_CONNECTIONS None +DOC_OUTLINES None None +DOC_SLOTS None None +DOC_REFDES None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_PARTTYPES None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_ATTRIBUTES None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_TESTPOINTS None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_OUTLINE_LAYERS N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N +DOC_PADS Black None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_VIAS Black None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_ROUTES None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_COPPER None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_LINES Black Black None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_TEXT Black Black None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_KEEPOUTS None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None +DOC_PINS_ADV 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +DOC_PAD_OVERSIZE 0 +DOC_PLOT_JOBNAME Y +DOC_PLOT_OLE N +DOC_MIRROR_REFS N +DOC_SUPRESS_PREFIXES "" +DOC_PLOT_QUALITY Filled +DOC_DRILL_CHART Y +DOC_CHART_OFFSET 75000000 75000000 +DOC_SUPRESS_EXCLUDE_PADS Y +DOC_COLOR_BY_NET 0 +} +CAM_DOC_NAME NC +{ +DOC_PLOT_TYPE NC_Drill +DOC_DEVICE_TYPE Drill +DOC_OUTPUT_FILE drl001.drl +DOC_LAYER_NAMES Top +DOC_LAYER_NUMBERS 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 +DOC_LAYER_TYPES Component +DOC_FABRICATION_LAYER_NUMBER 0 +DOC_SCALE 1 1 +DOC_ORIENTATION 0 +DOC_MIRROR N +DOC_JUSTIFICATION OO +DOC_OFFSET 150000000 150000000 +DOC_CLIP 0 +DOC_FIT_OUTPUT 0 +DOC_NO_PLANE_THERMALS 0 +DOC_ASSEMBLY_OPTION "" +DOC_CUSTOM_THERMALS 0 +DOC_DRILL_PLATED Y +DOC_DRILL_NONPLATED Y +DOC_DRILL_THRU_VIA Y +DOC_DRILL_PARTIAL_VIA N +DOC_DRILL_TESTPOINTS N +DOC_REPEAT_COUNTS 0 0 +DOC_STEP_SIZES 0 0 +DOC_DRILL_LIST Y +DOC_DRILL_FILE Y +} +} +CAM_DRILL_SPEED_FEED_TABLE PARENT +{ +DRILL_RANGE_1 381000 761619 95 300 +DRILL_RANGE_2 762000 1523619 197 550 +DRILL_RANGE_3 1524000 1904619 139 550 +DRILL_RANGE_4 1905000 2285619 107 550 +DRILL_RANGE_5 2286000 2666619 89 550 +DRILL_RANGE_6 2667000 3047619 81 550 +DRILL_RANGE_7 3048000 3428619 74 550 +DRILL_RANGE_8 3429000 3809619 66 550 +DRILL_RANGE_9 3810000 4571619 69 658 +DRILL_RANGE_10 4572000 5333619 35 794 +DRILL_RANGE_11 5334000 6095619 35 900 +DRILL_RANGE_12 6096000 7619619 35 1033 +} +CAM_AUGMENT_ON_THE_FLY Y +CAM_APERTURE_TABLE PARENT +{ +APERTURE_1 10 6000000 0 RND +APERTURE_2 11 1350000 0 SQR +APERTURE_3 12 1500000 0 SQR +APERTURE_4 13 750000 0 SQR +APERTURE_5 14 2476500 0 SQR +APERTURE_6 15 2476500 0 RND +APERTURE_7 16 2667000 0 RND +APERTURE_8 17 1500000 0 RND +APERTURE_9 18 2286000 0 RND +APERTURE_10 19 4500000 0 RND +APERTURE_11 20 900000 0 RND +APERTURE_12 21 381000 0 RND +APERTURE_13 22 1350000 0 RND +APERTURE_14 23 525000 0 RND +APERTURE_15 24 750000 0 RND +APERTURE_16 25 2362200 0 RND +APERTURE_17 26 375000 0 SQR +APERTURE_18 27 1200000 0 SQR +APERTURE_19 28 1447800 0 SQR +APERTURE_20 29 900000 0 SQR +APERTURE_21 30 375000 0 RND +APERTURE_22 31 3000000 0 SQR +APERTURE_23 32 2700000 0 SQR +APERTURE_24 33 1714500 0 SQR +APERTURE_25 34 600000 0 RND +APERTURE_26 35 630000 0 RND +APERTURE_27 36 300000 0 RND +APERTURE_28 37 225000 0 RND +APERTURE_29 38 190500 0 RND +APERTURE_30 39 150000 0 RND +APERTURE_31 40 152400 0 RND +APERTURE_32 41 304800 0 RND +APERTURE_33 42 228600 0 RND +APERTURE_34 43 6381000 0 RND +APERTURE_35 44 1731000 0 SQR +APERTURE_36 45 1881000 0 SQR +APERTURE_37 46 1131000 0 SQR +APERTURE_38 47 2857500 0 SQR +APERTURE_39 48 2857500 0 RND +APERTURE_40 49 3048000 0 RND +APERTURE_41 50 1881000 0 RND +APERTURE_42 51 4881000 0 RND +APERTURE_43 52 1281000 0 RND +APERTURE_44 53 756000 0 SQR +APERTURE_45 54 762000 0 RND +APERTURE_46 55 1581000 0 SQR +APERTURE_47 56 1828800 0 SQR +APERTURE_48 57 2743200 0 RND +APERTURE_49 58 1281000 0 SQR +APERTURE_50 59 756000 0 RND +APERTURE_51 60 3381000 0 SQR +APERTURE_52 61 3081000 0 SQR +APERTURE_53 62 2095500 0 SQR +APERTURE_54 63 981000 0 RND +APERTURE_55 64 1011000 0 RND +APERTURE_56 65 38100 0 RND +APERTURE_57 66 2250000 0 RND +APERTURE_58 67 1200000 0 RND +APERTURE_59 68 450000 0 SQR +APERTURE_60 69 3900000 0 SQR +APERTURE_61 70 1125000 0 SQR +APERTURE_62 71 450000 0 RND +APERTURE_63 72 1275000 0 RND +APERTURE_64 73 150114 0 RND +APERTURE_65 74 266700 0 RND +APERTURE_66 75 2631000 0 RND +APERTURE_67 76 1581000 0 RND +APERTURE_68 77 831000 0 SQR +APERTURE_69 78 4281000 0 SQR +APERTURE_70 79 1506000 0 SQR +APERTURE_71 80 6750000 0 RND +APERTURE_72 81 3750000 0 SQR +APERTURE_73 82 3238500 0 RND +APERTURE_74 83 2850000 0 RND +APERTURE_75 84 975000 0 SQR +APERTURE_76 85 2286000 0 SQR +APERTURE_77 86 3810 0 RND +APERTURE_78 87 3238500 0 SQR +APERTURE_79 88 2400000 0 SQR +APERTURE_80 89 3150000 0 SQR +APERTURE_81 90 1800000 0 SQR +APERTURE_82 91 76200 0 RND +APERTURE_83 92 120000 0 RND +APERTURE_84 93 7131000 0 RND +APERTURE_85 94 4131000 0 SQR +APERTURE_86 95 3619500 0 RND +APERTURE_87 96 3231000 0 RND +APERTURE_88 97 1356000 0 SQR +APERTURE_89 98 2667000 0 SQR +APERTURE_90 99 3619500 0 SQR +APERTURE_91 100 2781000 0 SQR +APERTURE_92 101 3531000 0 SQR +APERTURE_93 102 2181000 0 SQR +APERTURE_94 103 771000 0 SQR +APERTURE_95 104 1431000 0 SQR +APERTURE_96 105 360000 0 SQR +APERTURE_97 106 1275000 0 SQR +APERTURE_98 107 675000 0 RND +APERTURE_99 108 1050000 0 RND +APERTURE_100 109 1656000 0 SQR +APERTURE_101 110 195000 0 RND +APERTURE_102 111 2095500 0 RND +APERTURE_103 112 1524000 0 SQR +APERTURE_104 113 1143000 0 SQR +APERTURE_105 114 1499997 1799844 RECT +APERTURE_106 115 1200000 1350000 RECT +APERTURE_107 116 1605000 945000 RECT +APERTURE_108 117 1605000 1050000 RECT +APERTURE_109 118 1200000 375000 RECT +APERTURE_110 119 375000 1200000 RECT +APERTURE_111 120 1447800 1143000 RECT +APERTURE_112 121 1800000 750000 OVAL +APERTURE_113 122 2025000 600000 RECT +APERTURE_114 123 2850000 3450000 RECT +APERTURE_115 124 2850000 2700000 RECT +APERTURE_116 125 1050000 1800000 RECT +APERTURE_117 126 1650000 1200000 ANNL +APERTURE_118 127 2400000 1050000 RECT +APERTURE_119 128 2100000 2400000 RECT +APERTURE_120 129 3300000 2100000 RECT +APERTURE_121 130 1350000 1200000 RECT +APERTURE_122 131 975000 2025000 RECT +APERTURE_123 132 1650000 900000 RECT +APERTURE_124 133 1880997 2180844 RECT +APERTURE_125 134 1986000 1326000 RECT +APERTURE_126 135 1986000 1431000 RECT +APERTURE_127 136 1581000 756000 RECT +APERTURE_128 137 756000 1581000 RECT +APERTURE_129 138 1828800 1524000 RECT +APERTURE_130 139 2181000 1131000 OVAL +APERTURE_131 140 2406000 981000 RECT +APERTURE_132 141 3231000 3831000 RECT +APERTURE_133 142 3231000 3081000 RECT +APERTURE_134 143 1431000 2181000 RECT +APERTURE_135 144 2031000 1581000 ANNL +APERTURE_136 145 2781000 1431000 RECT +APERTURE_137 146 2481000 2781000 RECT +APERTURE_138 147 3681000 2481000 RECT +APERTURE_139 148 1731000 1581000 RECT +APERTURE_140 149 1356000 2406000 RECT +APERTURE_141 150 2031000 1281000 RECT +APERTURE_142 151 1281000 1581000 RECT +APERTURE_143 152 900000 1200000 RECT +APERTURE_144 153 225165 0 RND +APERTURE_145 154 299850 0 RND +APERTURE_146 155 187500 0 RND +APERTURE_147 156 1800000 450000 RECT +APERTURE_148 157 450000 1800000 RECT +APERTURE_149 158 3450000 750000 ANNL +APERTURE_150 159 1143000 1447800 RECT +APERTURE_151 160 1143000 1524000 RECT +APERTURE_152 161 600000 3000000 RECT +APERTURE_153 162 3000000 0 RND +APERTURE_154 163 3314700 1790700 RECT +APERTURE_155 164 6096000 0 SQR +APERTURE_156 165 390000 0 RND +APERTURE_157 166 525000 2325000 RECT +APERTURE_158 167 2835000 2355000 RECT +APERTURE_159 168 7500000 0 RND +APERTURE_160 169 945000 1605000 RECT +APERTURE_161 170 1050000 1605000 RECT +APERTURE_162 171 5334000 0 SQR +APERTURE_163 172 1447800 2095500 RECT +APERTURE_164 173 2667000 5334000 RECT +APERTURE_165 174 2249999 1200001 RECT +APERTURE_166 175 600000 450000 RECT +APERTURE_167 176 427500 900000 RECT +APERTURE_168 177 2175000 0 RND +APERTURE_169 178 750000 3750000 RECT +APERTURE_170 179 3000000 3750000 RECT +APERTURE_171 180 457200 0 RND +APERTURE_172 181 1350000 381000 OVAL +APERTURE_173 182 381000 1350000 OVAL +APERTURE_174 183 1800000 900000 RECT +APERTURE_175 184 900000 1800000 RECT +APERTURE_176 185 750000 5700000 RECT +APERTURE_177 186 2400000 1050000 ANNL +APERTURE_178 187 2100000 1800000 RECT +APERTURE_179 188 1524000 1143000 RECT +APERTURE_180 189 375000 450000 RECT +APERTURE_181 190 1500000 1066800 RECT +APERTURE_182 191 450000 375000 RECT +APERTURE_183 192 3750000 750000 RECT +APERTURE_184 193 3750000 3000000 RECT +APERTURE_185 194 975000 1800000 RECT +APERTURE_186 195 1800000 975000 RECT +APERTURE_187 196 2181000 831000 RECT +APERTURE_188 197 831000 2181000 RECT +APERTURE_189 198 1731000 762000 OVAL +APERTURE_190 199 762000 1731000 OVAL +APERTURE_191 200 2181000 1281000 RECT +APERTURE_192 201 1281000 2181000 RECT +APERTURE_193 202 1131000 6081000 RECT +APERTURE_194 203 2781000 1431000 ANNL +APERTURE_195 204 2481000 2181000 RECT +APERTURE_196 205 771000 0 RND +APERTURE_197 206 3381000 0 RND +APERTURE_198 207 808500 1281000 RECT +APERTURE_199 208 2556000 0 RND +APERTURE_200 209 1905000 1524000 RECT +APERTURE_201 210 1524000 1905000 RECT +APERTURE_202 211 756000 831000 RECT +APERTURE_203 212 1881000 1447800 RECT +APERTURE_204 213 831000 756000 RECT +APERTURE_205 214 1326000 1986000 RECT +APERTURE_206 215 1431000 1986000 RECT +APERTURE_207 216 861000 936000 RECT +APERTURE_208 217 936000 861000 RECT +APERTURE_209 218 4131000 1131000 RECT +APERTURE_210 219 4131000 3381000 RECT +APERTURE_211 220 1356000 2181000 RECT +APERTURE_212 221 2181000 1356000 RECT +APERTURE_213 222 187455 0 RND +APERTURE_214 223 150120 0 RND +APERTURE_215 224 2667000 495300 OVAL +APERTURE_216 225 2095500 1447800 RECT +APERTURE_217 226 1066800 1500000 RECT +APERTURE_218 227 900000 2400000 OVAL +APERTURE_219 228 2250000 1800000 RECT +APERTURE_220 229 1800000 2250000 RECT +APERTURE_221 230 900000 427500 RECT +APERTURE_222 231 3048000 876300 OVAL +APERTURE_223 232 2476500 1828800 RECT +APERTURE_224 233 1447800 1881000 RECT +APERTURE_225 234 1281000 2781000 OVAL +APERTURE_226 235 2631000 2181000 RECT +APERTURE_227 236 2181000 2631000 RECT +APERTURE_228 237 1281000 808500 RECT +APERTURE_229 238 2325000 525000 RECT +APERTURE_230 239 2355000 2835000 RECT +APERTURE_231 240 609600 0 RND +APERTURE_232 241 876300 0 RND +APERTURE_233 242 1143000 0 RND +APERTURE_234 243 3150000 4200000 RECT +APERTURE_235 244 750000 2400000 RECT +APERTURE_236 245 2706000 906000 RECT +APERTURE_237 246 2736000 3216000 RECT +APERTURE_238 247 906000 2706000 RECT +APERTURE_239 248 3216000 2736000 RECT +APERTURE_240 249 3531000 4581000 RECT +APERTURE_241 250 1131000 2781000 RECT +APERTURE_242 251 225171 0 RND +APERTURE_243 252 194310 0 RND +APERTURE_244 253 299847 0 RND +APERTURE_245 254 914400 2819400 OVAL +APERTURE_246 255 6743700 0 RND +APERTURE_247 256 3750000 1500000 RECT +APERTURE_248 257 4500000 2250000 RECT +APERTURE_249 258 3750000 7500000 OVAL +APERTURE_250 259 7500000 3750000 OVAL +APERTURE_251 260 2100000 3000000 RECT +APERTURE_252 261 3000000 2100000 RECT +APERTURE_253 262 1714500 3048000 RECT +APERTURE_254 263 4495800 2476500 RECT +APERTURE_255 264 2700000 4725000 RECT +APERTURE_256 265 1200001 1500000 OVAL +APERTURE_257 266 2400000 0 RND +APERTURE_258 267 1200000 360000 RECT +APERTURE_259 268 1200000 330000 RECT +APERTURE_260 269 360000 1200000 RECT +APERTURE_261 270 8250000 8250000 RECT +APERTURE_262 271 342900 0 RND +APERTURE_263 272 1295400 3200400 OVAL +APERTURE_264 273 7124700 0 RND +APERTURE_265 274 1581000 1731000 RECT +APERTURE_266 275 3831000 1131000 ANNL +APERTURE_267 276 1524000 1828800 RECT +APERTURE_268 277 4131000 1881000 RECT +APERTURE_269 278 4881000 2631000 RECT +APERTURE_270 279 4131000 7881000 OVAL +APERTURE_271 280 7881000 4131000 OVAL +APERTURE_272 281 2481000 3381000 RECT +APERTURE_273 282 3381000 2481000 RECT +APERTURE_274 283 1828800 2476500 RECT +APERTURE_275 284 2095500 3429000 RECT +APERTURE_276 285 4876800 2857500 RECT +APERTURE_277 286 3081000 5106000 RECT +APERTURE_278 287 1581001 1881000 OVAL +APERTURE_279 288 2781000 0 RND +APERTURE_280 289 1581000 741000 RECT +APERTURE_281 290 1581000 711000 RECT +APERTURE_282 291 741000 1581000 RECT +APERTURE_283 292 8631000 8631000 RECT +APERTURE_284 293 1581000 1281000 RECT +APERTURE_285 294 1200000 900000 RECT +APERTURE_286 295 1305000 435000 RECT +APERTURE_287 296 224999 0 RND +APERTURE_288 297 255000 0 RND +APERTURE_289 298 23241 0 RND +APERTURE_290 299 2286000 1905000 RECT +APERTURE_291 300 2819400 914400 OVAL +APERTURE_292 301 375000 1200000 OVAL +APERTURE_293 302 1200000 375000 OVAL +APERTURE_294 303 4050000 0 SQR +APERTURE_295 304 1714500 2476500 RECT +APERTURE_296 305 1800000 0 RND +APERTURE_297 306 462600 0 RND +APERTURE_298 307 571500 0 RND +APERTURE_299 308 2667000 2286000 RECT +APERTURE_300 309 3200400 1295400 OVAL +APERTURE_301 310 756000 1581000 OVAL +APERTURE_302 311 1581000 756000 OVAL +APERTURE_303 312 4431000 0 SQR +APERTURE_304 313 2095500 2857500 RECT +APERTURE_305 314 2181000 0 RND +APERTURE_306 315 4500000 0 SQR +APERTURE_307 316 4725000 2700000 RECT +APERTURE_308 317 2100000 0 RND +APERTURE_309 318 2174999 0 RND +APERTURE_310 319 2024999 599998 RECT +APERTURE_311 320 2849998 2249999 RECT +APERTURE_312 321 1349998 0 RND +APERTURE_313 322 1500000 4500000 RECT +APERTURE_314 323 4200000 3450000 RECT +APERTURE_315 324 1066800 762000 RECT +APERTURE_316 325 4881000 0 SQR +APERTURE_317 326 5106000 3081000 RECT +APERTURE_318 327 2481000 0 RND +APERTURE_319 328 2555999 0 RND +APERTURE_320 329 2405999 980998 RECT +APERTURE_321 330 1731000 0 RND +APERTURE_322 331 3230998 2630999 RECT +APERTURE_323 332 1730998 0 RND +APERTURE_324 333 1881000 4881000 RECT +APERTURE_325 334 4581000 3831000 RECT +APERTURE_326 335 15000 0 RND +APERTURE_327 336 240000 0 RND +APERTURE_328 337 824998 1200001 RECT +APERTURE_329 338 3450000 6600000 RECT +APERTURE_330 339 3450000 6000000 RECT +APERTURE_331 340 899998 0 SQR +APERTURE_332 341 4500000 1200000 RECT +APERTURE_333 342 2286000 38100 ANNL +APERTURE_334 343 2324100 0 SQR +APERTURE_335 344 750000 4650000 RECT +APERTURE_336 345 3000000 4950000 RECT +APERTURE_337 346 3900000 1575000 RECT +APERTURE_338 347 3450000 4200000 RECT +APERTURE_339 348 2400300 457200 OVAL +APERTURE_340 349 457200 2400300 OVAL +APERTURE_341 350 2100000 1050000 RECT +APERTURE_342 351 762000 1066800 RECT +APERTURE_343 352 2362200 0 SQR +APERTURE_344 353 2700000 0 RND +APERTURE_345 354 2436000 0 RND +APERTURE_346 355 1205998 1581001 RECT +APERTURE_347 356 3831000 6981000 RECT +APERTURE_348 357 3831000 6381000 RECT +APERTURE_349 358 1280998 0 SQR +APERTURE_350 359 4881000 1581000 RECT +APERTURE_351 360 2667000 419100 ANNL +APERTURE_352 361 2705100 0 SQR +APERTURE_353 362 1131000 5031000 RECT +APERTURE_354 363 3381000 5331000 RECT +APERTURE_355 364 3381000 4131000 RECT +APERTURE_356 365 3831000 4581000 RECT +APERTURE_357 366 2781300 838200 OVAL +APERTURE_358 367 838200 2781300 OVAL +APERTURE_359 368 2743200 0 SQR +APERTURE_360 369 3081000 0 RND +APERTURE_361 370 4281000 1956000 RECT +APERTURE_362 371 2331000 1206000 RECT +APERTURE_363 372 2631000 1341000 RECT +APERTURE_364 373 2817000 0 RND +APERTURE_365 374 270135 0 RND +APERTURE_366 375 75000 0 RND +APERTURE_367 376 231000 0 RND +APERTURE_368 377 45000 0 RND +APERTURE_369 378 5250000 3300000 OVAL +APERTURE_370 379 6600000 3450000 RECT +APERTURE_371 380 6000000 3450000 RECT +APERTURE_372 381 3000000 3000000 RECT +APERTURE_373 382 1650000 0 RND +APERTURE_374 383 4800000 0 RND +APERTURE_375 384 4650000 750000 RECT +APERTURE_376 385 4950000 3000000 RECT +APERTURE_377 386 1335000 1050000 RECT +APERTURE_378 387 1050000 1335000 RECT +APERTURE_379 388 180000 0 RND +APERTURE_380 389 5631000 3681000 OVAL +APERTURE_381 390 6981000 3831000 RECT +APERTURE_382 391 6381000 3831000 RECT +APERTURE_383 392 3381000 3381000 RECT +APERTURE_384 393 2031000 0 RND +APERTURE_385 394 5181000 0 RND +APERTURE_386 395 5031000 1131000 RECT +APERTURE_387 396 5331000 3381000 RECT +APERTURE_388 397 1716000 1431000 RECT +APERTURE_389 398 1431000 1716000 RECT +APERTURE_390 399 1350000 1050000 RECT +APERTURE_391 400 1275000 1050000 RECT +APERTURE_392 401 1050000 1350000 RECT +APERTURE_393 402 1050000 1275000 RECT +APERTURE_394 403 120015 0 RND +APERTURE_395 404 270000 0 RND +APERTURE_396 405 3300000 5250000 OVAL +APERTURE_397 406 1200001 824998 RECT +APERTURE_398 407 3681000 5631000 OVAL +APERTURE_399 408 1905000 2286000 RECT +APERTURE_400 409 1581001 1205998 RECT +APERTURE_401 410 210000 0 RND +APERTURE_402 411 2286000 381000 OVAL +APERTURE_403 412 381000 2286000 OVAL +APERTURE_404 413 1830000 1365000 RECT +APERTURE_405 414 1575000 3900000 RECT +APERTURE_406 415 1500000 2250000 RECT +APERTURE_407 416 4950000 2250000 RECT +APERTURE_408 417 2667000 762000 OVAL +APERTURE_409 418 762000 2667000 OVAL +APERTURE_410 419 2211000 1746000 RECT +APERTURE_411 420 1881000 2631000 RECT +APERTURE_412 421 5331000 2631000 RECT +APERTURE_413 422 1956000 4281000 RECT +APERTURE_414 423 329184 0 RND +APERTURE_415 424 2286000 457200 OVAL +APERTURE_416 425 457200 2286000 OVAL +APERTURE_417 426 15000000 15000000 RECT +APERTURE_418 427 2667000 838200 OVAL +APERTURE_419 428 838200 2667000 OVAL +APERTURE_420 429 315000 0 RND +APERTURE_421 430 681000 0 RND +APERTURE_422 431 4050000 2100000 RECT +APERTURE_423 432 450000 525000 RECT +APERTURE_424 433 4431000 2481000 RECT +APERTURE_425 434 831000 906000 RECT +} +CAM_DRILL_SYMBOL_TABLE_EXTENDED PARENT +{ +MARKER_SIZE 3048000 +MARKER_LINE_WIDTH 381000 +MARKER_CHAR_HEIGHT 1905000 +CHART_TEXT_HEIGHT 4572000 +CHART_LINE_WIDTH 381000 +SIZE_VALUES_SORTING_ORDER 0 +QUANTITY_VALUES_SORTING_ORDER 0 +PLATED_VALUES_SORTING_ORDER 0 +DEFAULT_TOLERANCE +/-0.0 +DRILL_UNIT 1 +THROUGH_PARTIAL N +} +} + +*MISC* MISCELLANEOUS PARAMETERS + +*REMARK* PARENT_KEYWORD PARENT_VALUE +*REMARK* [ { +*REMARK* CHILD_KEYWORD CHILD_VALUE +*REMARK* [ CHILD_KEYWORD CHILD_VALUE +*REMARK* [ { +*REMARK* GRAND_CHILD_KEYWORD GRAND_CHILD_VALUE [...] +*REMARK* } ]] +*REMARK* } ] + + +*MISC* MISCELLANEOUS PARAMETERS + +ATTRIBUTES DICTIONARY +{ +ATTRIBUTE Rules.Fanout.Alignment +{ +TYPE LIST N +{ +Aligned +Alternate +} +INHERITANCE PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.Fanout.Alignment.Multi-Row +{ +TYPE BOOLEAN +INHERITANCE PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.Fanout.Direction +{ +TYPE LIST N +{ +Inside +Outside +Both Sides +} +INHERITANCE PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.Fanout.ViaSpacing +{ +TYPE LIST N +{ +Use Grid +1 Trace +2 Trace +} +INHERITANCE PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.Fanout.Sharing.Pin +{ +TYPE BOOLEAN +INHERITANCE PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.Fanout.Sharing.SMD +{ +TYPE BOOLEAN +INHERITANCE PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.Fanout.Sharing.Via +{ +TYPE BOOLEAN +INHERITANCE PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.Fanout.Sharing.Trace +{ +TYPE BOOLEAN +INHERITANCE PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.Fanout.Nets.Plane +{ +TYPE BOOLEAN +INHERITANCE PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.Fanout.Nets.Signal +{ +TYPE BOOLEAN +INHERITANCE PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.Fanout.Nets.UnusedPins +{ +TYPE BOOLEAN +INHERITANCE PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.Fanout.Length.Unlimited +{ +TYPE BOOLEAN +INHERITANCE PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.Fanout.Length.Maximum +{ +TYPE QUANTITY +QUANTITY Size/Dimension +ABBR +UNIT +MIN 0dbunit +MAX 76200000dbunit +INHERITANCE PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.Fanout.AlignmentBGA +{ +TYPE LIST N +{ +Diagonal +Quadrant +X-pattern +} +INHERITANCE PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.Fanout.DirectionBGA +{ +TYPE LIST N +{ +45 +135 +225 +315 +Clockwise +Counterclockwise +} +INHERITANCE PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.Fanout.DirectionBGAstaggered +{ +TYPE LIST N +{ +Horizontal +Vertical +} +INHERITANCE PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.PadEntry.Side +{ +TYPE BOOLEAN +INHERITANCE PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.PadEntry.Corner +{ +TYPE BOOLEAN +INHERITANCE PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.PadEntry.AnyAngle +{ +TYPE BOOLEAN +INHERITANCE PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.PadEntry.Soft +{ +TYPE BOOLEAN +INHERITANCE PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.ViaAtSMD +{ +TYPE BOOLEAN +INHERITANCE PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.ViaAtSMD.FitInside +{ +TYPE BOOLEAN +INHERITANCE PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.ViaAtSMD.Center +{ +TYPE BOOLEAN +INHERITANCE PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.ViaAtSMD.Ends +{ +TYPE BOOLEAN +INHERITANCE PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.Clearance.Trace.Trace +{ +TYPE QUANTITY +QUANTITY Size/Dimension +ABBR +UNIT +MIN 0dbunit +MAX 38100000dbunit +INHERITANCE PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.Clearance.Via.Trace +{ +TYPE QUANTITY +QUANTITY Size/Dimension +ABBR +UNIT +MIN 0dbunit +MAX 38100000dbunit +INHERITANCE PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.Clearance.Via.Via +{ +TYPE QUANTITY +QUANTITY Size/Dimension +ABBR +UNIT +MIN 0dbunit +MAX 38100000dbunit +INHERITANCE PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.Clearance.Pad.Trace +{ +TYPE QUANTITY +QUANTITY Size/Dimension +ABBR +UNIT +MIN 0dbunit +MAX 38100000dbunit +INHERITANCE PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.Clearance.Pad.Via +{ +TYPE QUANTITY +QUANTITY Size/Dimension +ABBR +UNIT +MIN 0dbunit +MAX 38100000dbunit +INHERITANCE PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.Clearance.Pad.Pad +{ +TYPE QUANTITY +QUANTITY Size/Dimension +ABBR +UNIT +MIN 0dbunit +MAX 38100000dbunit +INHERITANCE PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.Clearance.SMD.Trace +{ +TYPE QUANTITY +QUANTITY Size/Dimension +ABBR +UNIT +MIN 0dbunit +MAX 38100000dbunit +INHERITANCE PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.Clearance.SMD.Via +{ +TYPE QUANTITY +QUANTITY Size/Dimension +ABBR +UNIT +MIN 0dbunit +MAX 38100000dbunit +INHERITANCE PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.Clearance.SMD.Pad +{ +TYPE QUANTITY +QUANTITY Size/Dimension +ABBR +UNIT +MIN 0dbunit +MAX 38100000dbunit +INHERITANCE PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.Clearance.SMD.SMD +{ +TYPE QUANTITY +QUANTITY Size/Dimension +ABBR +UNIT +MIN 0dbunit +MAX 38100000dbunit +INHERITANCE PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.Clearance.Copper.Trace +{ +TYPE QUANTITY +QUANTITY Size/Dimension +ABBR +UNIT +MIN 0dbunit +MAX 38100000dbunit +INHERITANCE PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.Clearance.Copper.Via +{ +TYPE QUANTITY +QUANTITY Size/Dimension +ABBR +UNIT +MIN 0dbunit +MAX 38100000dbunit +INHERITANCE PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.Clearance.Copper.Pad +{ +TYPE QUANTITY +QUANTITY Size/Dimension +ABBR +UNIT +MIN 0dbunit +MAX 38100000dbunit +INHERITANCE PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.Clearance.Copper.SMD +{ +TYPE QUANTITY +QUANTITY Size/Dimension +ABBR +UNIT +MIN 0dbunit +MAX 38100000dbunit +INHERITANCE PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.Clearance.Copper.Copper +{ +TYPE QUANTITY +QUANTITY Size/Dimension +ABBR +UNIT +MIN 0dbunit +MAX 38100000dbunit +INHERITANCE PART +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.Clearance.Text.Trace +{ +TYPE QUANTITY +QUANTITY Size/Dimension +ABBR +UNIT +MIN 0dbunit +MAX 38100000dbunit +INHERITANCE PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.Clearance.Text.Via +{ +TYPE QUANTITY +QUANTITY Size/Dimension +ABBR +UNIT +MIN 0dbunit +MAX 38100000dbunit +INHERITANCE PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.Clearance.Text.Pad +{ +TYPE QUANTITY +QUANTITY Size/Dimension +ABBR +UNIT +MIN 0dbunit +MAX 38100000dbunit +INHERITANCE PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.Clearance.Text.SMD +{ +TYPE QUANTITY +QUANTITY Size/Dimension +ABBR +UNIT +MIN 0dbunit +MAX 38100000dbunit +INHERITANCE PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.Clearance.Board.Trace +{ +TYPE QUANTITY +QUANTITY Size/Dimension +ABBR +UNIT +MIN 0dbunit +MAX 38100000dbunit +INHERITANCE PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.Clearance.Board.Via +{ +TYPE QUANTITY +QUANTITY Size/Dimension +ABBR +UNIT +MIN 0dbunit +MAX 38100000dbunit +INHERITANCE PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.Clearance.Board.Pad +{ +TYPE QUANTITY +QUANTITY Size/Dimension +ABBR +UNIT +MIN 0dbunit +MAX 38100000dbunit +INHERITANCE PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.Clearance.Board.SMD +{ +TYPE QUANTITY +QUANTITY Size/Dimension +ABBR +UNIT +MIN 0dbunit +MAX 38100000dbunit +INHERITANCE PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.Clearance.Board.Copper +{ +TYPE QUANTITY +QUANTITY Size/Dimension +ABBR +UNIT +MIN 0dbunit +MAX 38100000dbunit +INHERITANCE PART +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.Clearance.Drill.Trace +{ +TYPE QUANTITY +QUANTITY Size/Dimension +ABBR +UNIT +MIN 0dbunit +MAX 38100000dbunit +INHERITANCE PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.Clearance.Drill.Via +{ +TYPE QUANTITY +QUANTITY Size/Dimension +ABBR +UNIT +MIN 0dbunit +MAX 38100000dbunit +INHERITANCE PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.Clearance.Drill.Pad +{ +TYPE QUANTITY +QUANTITY Size/Dimension +ABBR +UNIT +MIN 0dbunit +MAX 38100000dbunit +INHERITANCE PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.Clearance.Drill.SMD +{ +TYPE QUANTITY +QUANTITY Size/Dimension +ABBR +UNIT +MIN 0dbunit +MAX 38100000dbunit +INHERITANCE PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.SameNet.SMD.Via +{ +TYPE QUANTITY +QUANTITY Size/Dimension +ABBR +UNIT +MIN 0dbunit +MAX 38100000dbunit +INHERITANCE PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.SameNet.SMD.Crn +{ +TYPE QUANTITY +QUANTITY Size/Dimension +ABBR +UNIT +MIN 0dbunit +MAX 38100000dbunit +INHERITANCE PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.SameNet.Via.Via +{ +TYPE QUANTITY +QUANTITY Size/Dimension +ABBR +UNIT +MIN 0dbunit +MAX 38100000dbunit +INHERITANCE PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.SameNet.Pad.Crn +{ +TYPE QUANTITY +QUANTITY Size/Dimension +ABBR +UNIT +MIN 0dbunit +MAX 38100000dbunit +INHERITANCE PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.SameNet.Trace.Crn +{ +TYPE QUANTITY +QUANTITY Size/Dimension +ABBR +UNIT +MIN 0dbunit +MAX 38100000dbunit +INHERITANCE PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.Width.Minimum +{ +TYPE QUANTITY +QUANTITY Size/Dimension +ABBR +UNIT +MIN 0dbunit +MAX 9525000dbunit +INHERITANCE PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.Width.Recommended +{ +TYPE QUANTITY +QUANTITY Size/Dimension +ABBR +UNIT +MIN 0dbunit +MAX 9525000dbunit +INHERITANCE PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.Width.Maximum +{ +TYPE QUANTITY +QUANTITY Size/Dimension +ABBR +UNIT +MIN 0dbunit +MAX 9525000dbunit +INHERITANCE PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Rules.Routing.RestrictedVias.00000 +{ +TYPE FREETEXT N +INHERITANCE NET PCB +INHERITANCE PART DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Value +{ +TYPE FREETEXT N +INHERITANCE NET +INHERITANCE PART PARTTYPE +ECO_REGISTRATION Y +READONLY N +SYSTEM Y +HIDDEN N +} +ATTRIBUTE Tolerance +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION Y +READONLY N +SYSTEM Y +HIDDEN N +} +ATTRIBUTE Part Number +{ +TYPE FREETEXT N +INHERITANCE NET +INHERITANCE PART PARTTYPE +ECO_REGISTRATION Y +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE Description +{ +TYPE FREETEXT N +INHERITANCE NET +INHERITANCE PART PARTTYPE +ECO_REGISTRATION Y +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE Cost +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION Y +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE Manufacturer #1 +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION Y +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE Manufacturer #2 +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION Y +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE ASSEMBLY_OPTIONS +{ +TYPE FREETEXT N +INHERITANCE PCB +INHERITANCE PART +INHERITANCE JUMPER +ECO_REGISTRATION Y +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE PowerGround +{ +TYPE BOOLEAN +INHERITANCE NET NETCLASS PCB +ECO_REGISTRATION Y +READONLY N +SYSTEM Y +HIDDEN N +} +ATTRIBUTE Voltage +{ +TYPE QUANTITY +QUANTITY Voltage +ABBR V +UNIT Volt +MIN -100kV +MAX 100kV +INHERITANCE NET NETCLASS +ECO_REGISTRATION Y +READONLY N +SYSTEM Y +HIDDEN N +} +ATTRIBUTE Geometry.Height +{ +TYPE QUANTITY +QUANTITY Size/Dimension +ABBR +UNIT +MIN 0dbunit +MAX 952500000dbunit +INHERITANCE PCB +INHERITANCE PART PARTTYPE DECAL +ECO_REGISTRATION N +READONLY N +SYSTEM Y +HIDDEN N +} +ATTRIBUTE DFT.Nail Count Per Net +{ +TYPE INTEGER +MIN 0 +MAX 1000 +INHERITANCE NET NETCLASS PCB +ECO_REGISTRATION Y +READONLY N +SYSTEM Y +HIDDEN N +} +ATTRIBUTE DFT.Nail Diameter +{ +TYPE FREETEXT N +INHERITANCE PIN +INHERITANCE VIA +ECO_REGISTRATION N +READONLY N +SYSTEM Y +HIDDEN N +} +ATTRIBUTE DFT.Nail Number +{ +TYPE FREETEXT N +INHERITANCE PIN +INHERITANCE VIA +ECO_REGISTRATION N +READONLY N +SYSTEM Y +HIDDEN N +} +ATTRIBUTE DFT.Probe to Trace Clearance +{ +TYPE QUANTITY +QUANTITY Size/Dimension +ABBR +UNIT +MIN 0dbunit +MAX 38100000dbunit +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE DFT.Probe to Pad Clearance +{ +TYPE QUANTITY +QUANTITY Size/Dimension +ABBR +UNIT +MIN 0dbunit +MAX 38100000dbunit +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE DFT.Generate Test Points +{ +TYPE BOOLEAN +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE DFT.Allow Stubs +{ +TYPE BOOLEAN +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE DFT.Stub Length +{ +TYPE QUANTITY +QUANTITY Size/Dimension +ABBR +UNIT +MIN 0dbunit +MAX 76200000dbunit +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE DFT.Use Via Grid +{ +TYPE BOOLEAN +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE DFT.Grid X-Coordinate +{ +TYPE QUANTITY +QUANTITY Size/Dimension +ABBR +UNIT +MIN 0dbunit +MAX 76200000dbunit +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE DFT.Grid Y-Coordinate +{ +TYPE QUANTITY +QUANTITY Size/Dimension +ABBR +UNIT +MIN 0dbunit +MAX 76200000dbunit +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE DFT.Preserve Test Points +{ +TYPE BOOLEAN +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE DFT.Insert Test Point Vias +{ +TYPE BOOLEAN +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE DFT.Probe Pins +{ +TYPE BOOLEAN +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE HyperLynx.Model +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION Y +READONLY N +SYSTEM Y +HIDDEN N +} +ATTRIBUTE HyperLynx.Model File +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION Y +READONLY N +SYSTEM Y +HIDDEN N +} +ATTRIBUTE HyperLynx.Sim Direction +{ +TYPE LIST N +{ +SIM_BOTH +SIM_IN +SIM_OUT +} +INHERITANCE PIN +ECO_REGISTRATION Y +READONLY N +SYSTEM Y +HIDDEN N +} +ATTRIBUTE HyperLynx.Frequency +{ +TYPE QUANTITY +QUANTITY Frequency +ABBR Hz +UNIT Hertz +MIN 0Hz +MAX 1000GHz +INHERITANCE NET NETCLASS +ECO_REGISTRATION Y +READONLY N +SYSTEM Y +HIDDEN N +} +ATTRIBUTE HyperLynx.Duty Cycle +{ +TYPE QUANTITY +QUANTITY +ABBR % +UNIT percent +MIN 0% +MAX 100% +INHERITANCE NET NETCLASS +ECO_REGISTRATION Y +READONLY N +SYSTEM Y +HIDDEN N +} +ATTRIBUTE HyperLynx.Signal Type +{ +TYPE LIST N +{ +Address +Analog High Speed +Analog Low Speed +Clock +Data +Do Not Analyze +Power Supply +Strobe +} +INHERITANCE NET NETCLASS +ECO_REGISTRATION Y +READONLY N +SYSTEM Y +HIDDEN N +} +ATTRIBUTE HyperLynx.Default IC.Model +{ +TYPE FREETEXT N +INHERITANCE NET NETCLASS +ECO_REGISTRATION Y +READONLY N +SYSTEM Y +HIDDEN N +} +ATTRIBUTE HyperLynx.Default IC.Model File +{ +TYPE FREETEXT N +INHERITANCE NET NETCLASS +ECO_REGISTRATION Y +READONLY N +SYSTEM Y +HIDDEN N +} +ATTRIBUTE HyperLynx.Default IC.Model Pin +{ +TYPE FREETEXT N +INHERITANCE NET NETCLASS +ECO_REGISTRATION Y +READONLY N +SYSTEM Y +HIDDEN N +} +ATTRIBUTE Strategy.Fanout.Pass +{ +TYPE LIST N +{ +No +Yes +Done +} +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.Fanout.Protect +{ +TYPE BOOLEAN +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.Fanout.Pause +{ +TYPE BOOLEAN +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.Fanout.Intensity +{ +TYPE LIST N +{ +Low +Medium +High +} +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.Fanout.Priority +{ +TYPE INTEGER +MIN 0 +INHERITANCE NET NETCLASS PCB +INHERITANCE PART +INHERITANCE PINPAIR +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.Fanout.PlanePriority +{ +TYPE INTEGER +MIN 0 +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.Fanout.DiffPairPriority +{ +TYPE INTEGER +MIN 0 +INHERITANCE NET +INHERITANCE PINPAIR +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.Fanout.MLGPriority +{ +TYPE INTEGER +MIN 0 +INHERITANCE NET NETCLASS PCB +INHERITANCE PINPAIR GROUP +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.Patterns.Pass +{ +TYPE LIST N +{ +No +Yes +Done +} +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.Patterns.Protect +{ +TYPE BOOLEAN +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.Patterns.Pause +{ +TYPE BOOLEAN +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.Patterns.Intensity +{ +TYPE LIST N +{ +Low +Medium +High +} +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.Patterns.Priority +{ +TYPE INTEGER +MIN 0 +INHERITANCE NET NETCLASS PCB +INHERITANCE PART +INHERITANCE PINPAIR +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.Patterns.PlanePriority +{ +TYPE INTEGER +MIN 0 +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.Patterns.DiffPairPriority +{ +TYPE INTEGER +MIN 0 +INHERITANCE NET +INHERITANCE PINPAIR +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.Patterns.MLGPriority +{ +TYPE INTEGER +MIN 0 +INHERITANCE NET NETCLASS PCB +INHERITANCE PINPAIR GROUP +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.Route.Pass +{ +TYPE LIST N +{ +No +Yes +Done +} +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.Route.Protect +{ +TYPE BOOLEAN +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.Route.Pause +{ +TYPE BOOLEAN +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.Route.Intensity +{ +TYPE LIST N +{ +Low +Medium +High +} +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.Route.Priority +{ +TYPE INTEGER +MIN 0 +INHERITANCE NET NETCLASS PCB +INHERITANCE PART +INHERITANCE PINPAIR +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.Route.PlanePriority +{ +TYPE INTEGER +MIN 0 +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.Route.DiffPairPriority +{ +TYPE INTEGER +MIN 0 +INHERITANCE NET +INHERITANCE PINPAIR +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.Route.MLGPriority +{ +TYPE INTEGER +MIN 0 +INHERITANCE NET NETCLASS PCB +INHERITANCE PINPAIR GROUP +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.Optimize.Pass +{ +TYPE LIST N +{ +No +Yes +Done +} +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.Optimize.Protect +{ +TYPE BOOLEAN +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.Optimize.Pause +{ +TYPE BOOLEAN +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.Optimize.Intensity +{ +TYPE LIST N +{ +Low +Medium +High +} +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.Optimize.Priority +{ +TYPE INTEGER +MIN 0 +INHERITANCE NET NETCLASS PCB +INHERITANCE PART +INHERITANCE PINPAIR +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.Optimize.PlanePriority +{ +TYPE INTEGER +MIN 0 +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.Optimize.DiffPairPriority +{ +TYPE INTEGER +MIN 0 +INHERITANCE NET +INHERITANCE PINPAIR +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.Optimize.MLGPriority +{ +TYPE INTEGER +MIN 0 +INHERITANCE NET NETCLASS PCB +INHERITANCE PINPAIR GROUP +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.Miters.Pass +{ +TYPE LIST N +{ +No +Yes +Done +} +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.Miters.Protect +{ +TYPE BOOLEAN +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.Miters.Pause +{ +TYPE BOOLEAN +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.Miters.Intensity +{ +TYPE LIST N +{ +Low +Medium +High +} +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.Miters.Priority +{ +TYPE INTEGER +MIN 0 +INHERITANCE NET NETCLASS PCB +INHERITANCE PART +INHERITANCE PINPAIR +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.Miters.PlanePriority +{ +TYPE INTEGER +MIN 0 +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.Miters.DiffPairPriority +{ +TYPE INTEGER +MIN 0 +INHERITANCE NET +INHERITANCE PINPAIR +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.Miters.MLGPriority +{ +TYPE INTEGER +MIN 0 +INHERITANCE NET NETCLASS PCB +INHERITANCE PINPAIR GROUP +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.TestPoint.Pass +{ +TYPE LIST N +{ +No +Yes +Done +} +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.TestPoint.Protect +{ +TYPE BOOLEAN +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.TestPoint.Pause +{ +TYPE BOOLEAN +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.TestPoint.Intensity +{ +TYPE LIST N +{ +Low +Medium +High +} +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.TestPoint.Priority +{ +TYPE INTEGER +MIN 0 +INHERITANCE NET NETCLASS PCB +INHERITANCE PART +INHERITANCE PINPAIR +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.TestPoint.PlanePriority +{ +TYPE INTEGER +MIN 0 +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.TestPoint.DiffPairPriority +{ +TYPE INTEGER +MIN 0 +INHERITANCE NET +INHERITANCE PINPAIR +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.TestPoint.MLGPriority +{ +TYPE INTEGER +MIN 0 +INHERITANCE NET NETCLASS PCB +INHERITANCE PINPAIR GROUP +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.Center.Pass +{ +TYPE LIST N +{ +No +Yes +Done +} +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.Center.Protect +{ +TYPE BOOLEAN +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.Center.Pause +{ +TYPE BOOLEAN +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.Center.Intensity +{ +TYPE LIST N +{ +Low +Medium +High +} +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.Center.PlanePriority +{ +TYPE INTEGER +MIN 0 +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.Center.Priority +{ +TYPE INTEGER +MIN 0 +INHERITANCE NET NETCLASS PCB +INHERITANCE PART +INHERITANCE PINPAIR +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.Center.DiffPairPriority +{ +TYPE INTEGER +MIN 0 +INHERITANCE NET +INHERITANCE PINPAIR +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.Center.MLGPriority +{ +TYPE INTEGER +MIN 0 +INHERITANCE NET NETCLASS PCB +INHERITANCE PINPAIR GROUP +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.Tune.Pass +{ +TYPE LIST N +{ +No +Yes +Done +} +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.Tune.Protect +{ +TYPE BOOLEAN +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.Tune.Pause +{ +TYPE BOOLEAN +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.Tune.Intensity +{ +TYPE LIST N +{ +Low +Medium +High +} +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.Tune.PlanePriority +{ +TYPE INTEGER +MIN 0 +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.Tune.Priority +{ +TYPE INTEGER +MIN 0 +INHERITANCE NET NETCLASS PCB +INHERITANCE PART +INHERITANCE PINPAIR +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.Tune.DiffPairPriority +{ +TYPE INTEGER +MIN 0 +INHERITANCE NET +INHERITANCE PINPAIR +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Strategy.Tune.MLGPriority +{ +TYPE INTEGER +MIN 0 +INHERITANCE NET NETCLASS PCB +INHERITANCE PINPAIR GROUP +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE DIE.FormatId +{ +TYPE FREETEXT N +INHERITANCE DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE DIE.ChipLength +{ +TYPE FREETEXT N +INHERITANCE DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE DIE.ChipWidth +{ +TYPE FREETEXT N +INHERITANCE DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE DIE.ChipHeight +{ +TYPE FREETEXT N +INHERITANCE DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE DIE.WBRules.MinLength +{ +TYPE FREETEXT N +INHERITANCE DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE DIE.WBRules.MaxLength +{ +TYPE FREETEXT N +INHERITANCE DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE DIE.WBRules.WToWDistance +{ +TYPE FREETEXT N +INHERITANCE DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE DIE.WBRules.WBtoPad +{ +TYPE FREETEXT N +INHERITANCE DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE DIE.WBRules.MaxAngle +{ +TYPE FREETEXT N +INHERITANCE DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE DIE.SBPCount +{ +TYPE FREETEXT N +INHERITANCE DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE DIE.SBP1 +{ +TYPE FREETEXT N +INHERITANCE DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE DIE.CBPCount +{ +TYPE FREETEXT N +INHERITANCE DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE DIE.CBP1 +{ +TYPE FREETEXT N +INHERITANCE DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE DIE.WBCount +{ +TYPE FREETEXT N +INHERITANCE DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE DIE.WB1 +{ +TYPE FREETEXT N +INHERITANCE DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE DIE.SBPGuideCount +{ +TYPE FREETEXT N +INHERITANCE DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE DIE.SBPGuide1 +{ +TYPE FREETEXT N +INHERITANCE DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE DIE.CBPAssignment1 +{ +TYPE FREETEXT N +INHERITANCE DECAL +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE AutoDimensioning.Marker_Shape +{ +TYPE FREETEXT N +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE AutoDimensioning.Text_NumberPrecision +{ +TYPE FREETEXT N +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE AutoDimensioning.Text_AngularPrecision +{ +TYPE FREETEXT N +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE AutoDimensioning.Text_Suffix +{ +TYPE FREETEXT N +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE AutoDimensioning.Text_Layer +{ +TYPE INTEGER +MIN 0 +MAX 250 +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE AutoDimensioning.Line_Layer +{ +TYPE INTEGER +MIN 0 +MAX 250 +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE AutoDimensioning.Preview_Type +{ +TYPE INTEGER +MIN 1 +MAX 5 +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE AutoDimensioning.Text_DisplacementValue +{ +TYPE INTEGER +MIN 0 +MAX 38100000 +INHERITANCE PCB +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE Placement.Grid.Use +{ +TYPE BOOLEAN +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Placement.Grid.X +{ +TYPE QUANTITY +QUANTITY Size/Dimension +ABBR +UNIT +MIN 0dbunit +MAX 76200000dbunit +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Placement.Grid.Y +{ +TYPE QUANTITY +QUANTITY Size/Dimension +ABBR +UNIT +MIN 0dbunit +MAX 76200000dbunit +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Accordion.Amplitude.Min +{ +TYPE INTEGER +MIN 3 +MAX 300 +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Accordion.Amplitude.Max +{ +TYPE INTEGER +MIN 4 +MAX 300 +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Accordion.Gap.Min +{ +TYPE INTEGER +MIN 1 +MAX 10 +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Accordion.HierarchyLevel +{ +TYPE INTEGER +MIN 1 +MAX 8 +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Accordion.Miters.Arcs +{ +TYPE BOOLEAN +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Accordion.Miters.Ratio +{ +TYPE FLOAT +MIN 0.5 +MAX 250 +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Routing.MaxChannelWidth +{ +TYPE QUANTITY +QUANTITY Size/Dimension +ABBR +UNIT +MIN 0dbunit +MAX 381000000dbunit +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Routing.SoftLengthRrules +{ +TYPE BOOLEAN +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Routing.MeanderBeforeTune +{ +TYPE BOOLEAN +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Routing.ExtraLengthPercent +{ +TYPE INTEGER +MIN 0 +MAX 100 +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE MatchLength.Name +{ +TYPE FREETEXT N +INHERITANCE NET NETCLASS +INHERITANCE PINPAIR GROUP +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Planning.Scheduled +{ +TYPE BOOLEAN +INHERITANCE NET +ECO_REGISTRATION Y +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Library.Timestamp +{ +TYPE FREETEXT N +INHERITANCE DECAL +INHERITANCE PARTTYPE +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Design.Timestamp +{ +TYPE FREETEXT N +INHERITANCE DECAL +INHERITANCE PARTTYPE +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE DiffPair.RestrictPairTuneInGap +{ +TYPE BOOLEAN +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE DiffPair.RestrictSmallAccordionsInPairs +{ +TYPE BOOLEAN +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE DiffPair.TunePairsToZeroTolerance +{ +TYPE BOOLEAN +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE DiffPair.MinControlledLength +{ +TYPE FLOAT +MIN 20 +MAX 100 +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE DiffPair.MaxIrregularLength +{ +TYPE QUANTITY +QUANTITY Size/Dimension +ABBR +UNIT +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE CAM.Solder mask.Adjust +{ +TYPE QUANTITY +QUANTITY Size/Dimension +ABBR +UNIT +MIN -9525000dbunit +MAX 9525000dbunit +INHERITANCE PCB +INHERITANCE PART DECAL +INHERITANCE VIA +ECO_REGISTRATION N +READONLY N +SYSTEM Y +HIDDEN N +} +ATTRIBUTE CAM.Paste mask.Adjust +{ +TYPE QUANTITY +QUANTITY Size/Dimension +ABBR +UNIT +MIN -9525000dbunit +MAX 9525000dbunit +INHERITANCE PCB +INHERITANCE PART DECAL +INHERITANCE VIA +ECO_REGISTRATION N +READONLY N +SYSTEM Y +HIDDEN N +} +ATTRIBUTE CAM.Apply Oversize To All Pads +{ +TYPE BOOLEAN +INHERITANCE PCB +ECO_REGISTRATION N +READONLY N +SYSTEM Y +HIDDEN N +} +ATTRIBUTE CHK.Use Visible Workspace Box for Latium Checking +{ +TYPE BOOLEAN +INHERITANCE PCB +ECO_REGISTRATION N +READONLY N +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Single Sided Board +{ +TYPE BOOLEAN +INHERITANCE PCB +ECO_REGISTRATION N +READONLY N +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE DxDesigner.ProjectFilePath +{ +TYPE FREETEXT N +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE iCDB.DesignName +{ +TYPE FREETEXT N +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE iCDB.RootBlock +{ +TYPE FREETEXT N +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE iCDB.MainSnapshotName +{ +TYPE FREETEXT N +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE iCDB.TempSnapshotName +{ +TYPE FREETEXT N +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Bridges +{ +TYPE FREETEXT N +INHERITANCE NET +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE Guard.BandColor +{ +TYPE INTEGER +MIN 0 +INHERITANCE PCB +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE Blaze.Thermal.Color +{ +TYPE INTEGER +MIN 0 +INHERITANCE PCB +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE Blaze.TestPoint.Color +{ +TYPE INTEGER +MIN 0 +INHERITANCE PCB +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE Voltage Rating +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE Sim.Analog.Prefix +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE Sim.Analog.Order +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE Sim.Analog.Model +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE ZTEPN +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE TOL +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE FOOTPRINT +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE PACKAGE +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE MFR +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE DESC +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE MPN +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE Comment +{ +TYPE FREETEXT N +INHERITANCE PART DECAL PARTTYPE +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE MFG #1 +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE PART DESC +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE PART NB +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE DECAL +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE ASSEMBLY +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE 1ST_PART_DESCRIPTION +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE SOURCE_PATH +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE MFG#1 +{ +TYPE FREETEXT N +INHERITANCE PART +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE Current Rating +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE Spil Part # +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE Marking +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE Manufacturer +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE Code +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE Value1 +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE DXLED# +{ +TYPE FREETEXT N +INHERITANCE NET +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE Source Path +{ +TYPE FREETEXT N +INHERITANCE NET +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE Name +{ +TYPE FREETEXT N +INHERITANCE NET +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE CD5V +{ +TYPE FREETEXT N +INHERITANCE NET +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE CD +{ +TYPE FREETEXT N +INHERITANCE NET +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE v +{ +TYPE FREETEXT N +INHERITANCE NET +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE VAR +{ +TYPE FREETEXT N +INHERITANCE NET +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE V+ +{ +TYPE FREETEXT N +INHERITANCE NET +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE AGND +{ +TYPE FREETEXT N +INHERITANCE NET +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE GND +{ +TYPE FREETEXT N +INHERITANCE NET +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE SLEEP_XTAL_IN +{ +TYPE FREETEXT N +INHERITANCE NET +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE GND_a +{ +TYPE FREETEXT N +INHERITANCE NET +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE VBATR +{ +TYPE FREETEXT N +INHERITANCE NET +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE dnd +{ +TYPE FREETEXT N +INHERITANCE NET +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE DGND +{ +TYPE FREETEXT N +INHERITANCE NET +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE CD_CMD +{ +TYPE FREETEXT N +INHERITANCE NET +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE UGND +{ +TYPE FREETEXT N +INHERITANCE NET +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE V-CLK +{ +TYPE FREETEXT N +INHERITANCE NET +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE GND_BT +{ +TYPE FREETEXT N +INHERITANCE NET +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE System_Gnd +{ +TYPE FREETEXT N +INHERITANCE NET +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE CARDVCC +{ +TYPE FREETEXT N +INHERITANCE NET +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE DESCRIPTION_2 +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE AMBIQ_PN +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE Package_Type +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE MFG_NAME +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE MFG_PN +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE Manufacturer_Datasheet +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE ROHS +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE HEIGHT +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE LEAD_FREE +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE PART_TYPE +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE STATUS +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE Package_Size +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE Number_Of_Contact_Rows +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE Number_Of_Contacts +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE PCB_Contact_Spacing +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE Contact_Plating +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE PEAK_REFLOW_TEMP +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE Type +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE Number_Of_Connectors +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE IBIS +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE ASSY_NOTE +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE ALT_SYMBOLS +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE SYMBOL_PDF_LOCATION +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE LOCAL_DATASHEET_LOCATION +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE FOOTPRINT_PDF_LOCATION +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE DEVICE +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE NOTES +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE DISTRIBUTOR_PN +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE DISTRIBUTOR +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE INFO +{ +TYPE FREETEXT N +INHERITANCE PART +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE SYM.OLB +{ +TYPE FREETEXT N +INHERITANCE NET +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE M.OLB +{ +TYPE FREETEXT N +INHERITANCE NET +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE VAUL +{ +TYPE FREETEXT N +INHERITANCE NET +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE FSDS +{ +TYPE FREETEXT N +INHERITANCE NET +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE AUDIO_CLK +{ +TYPE FREETEXT N +INHERITANCE NET +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE RFGND +{ +TYPE FREETEXT N +INHERITANCE NET +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE D-GND +{ +TYPE FREETEXT N +INHERITANCE NET +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE GND-FM +{ +TYPE FREETEXT N +INHERITANCE NET +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE CHGND +{ +TYPE FREETEXT N +INHERITANCE NET +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE RA +{ +TYPE FREETEXT N +INHERITANCE NET +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE DG +{ +TYPE FREETEXT N +INHERITANCE NET +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE BGND +{ +TYPE FREETEXT N +INHERITANCE NET +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE P_GND +{ +TYPE FREETEXT N +INHERITANCE NET +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE IF_GND +{ +TYPE FREETEXT N +INHERITANCE NET +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE NET NAME +{ +TYPE FREETEXT N +INHERITANCE NET +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE RF GND +{ +TYPE FREETEXT N +INHERITANCE NET +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE TGND +{ +TYPE FREETEXT N +INHERITANCE NET +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE GND-S +{ +TYPE FREETEXT N +INHERITANCE NET +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE P30 +{ +TYPE FREETEXT N +INHERITANCE NET +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE PGND +{ +TYPE FREETEXT N +INHERITANCE NET +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE IPGND +{ +TYPE FREETEXT N +INHERITANCE NET +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE vcc +{ +TYPE FREETEXT N +INHERITANCE NET +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE DCDIS +{ +TYPE FREETEXT N +INHERITANCE NET +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE 3502_1.8V +{ +TYPE FREETEXT N +INHERITANCE NET +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE EXT GND +{ +TYPE FREETEXT N +INHERITANCE NET +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE GNDD +{ +TYPE FREETEXT N +INHERITANCE NET +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE GND(2) +{ +TYPE FREETEXT N +INHERITANCE NET +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE VBAT +{ +TYPE FREETEXT N +INHERITANCE NET +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE GND_SIGNAL +{ +TYPE FREETEXT N +INHERITANCE NET +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE OLB +{ +TYPE FREETEXT N +INHERITANCE NET +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE Data to ipod +{ +TYPE FREETEXT N +INHERITANCE NET +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE GNDPA +{ +TYPE FREETEXT N +INHERITANCE NET +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE VDD +{ +TYPE FREETEXT N +INHERITANCE NET +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE GFGF +{ +TYPE FREETEXT N +INHERITANCE NET +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE 1ST_PART_FOOTPRINT +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE PAGE +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE Mating Spil Part # +{ +TYPE FREETEXT N +INHERITANCE PART PARTTYPE +ECO_REGISTRATION N +READONLY N +SYSTEM N +HIDDEN N +} +ATTRIBUTE LaserDrillOversize +{ +TYPE FLOAT +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE ViaLaserData +{ +TYPE FREETEXT N +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE PreservePadsOnNoPlaneLayers +{ +TYPE BOOLEAN +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE DFF.Silkscreen To Copper Pad Minimum Gap +{ +TYPE INTEGER +MIN 0 +MAX 38100000 +INHERITANCE PCB +ECO_REGISTRATION N +READONLY Y +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE PADS3D.Objects.Silkscreen.Refresh +{ +TYPE FREETEXT N +INHERITANCE PCB +ECO_REGISTRATION N +READONLY N +SYSTEM Y +HIDDEN Y +} +ATTRIBUTE PADS3D.Objects.SolderMask.Refresh +{ +TYPE FREETEXT N +INHERITANCE PCB +ECO_REGISTRATION N +READONLY N +SYSTEM Y +HIDDEN Y +} +} +ATTRIBUTE VALUES +{ +NET DM_NSLINK +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET DP_NSLINK +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET $$$24935 +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET $$$24997 +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET GND +{ +3502_1.8V +AGND +AUDIO_CLK +BGND +CARDVCC +CD GND +CD5V 50 +CD_CMD +CHGND +D-GND +"Data to ipod" 111 +DCDIS +Description +"DFT.Nail Count Per Net" +DG +DGND +dnd +DXLED# DXLED# +"EXT GND" +FSDS AM4 +GND +GND(2) GND(2) +GND-FM +GND-S +GND_a +GND_BT +GND_SIGNAL +GNDD +GNDPA GNDPA +IF_GND GND +IPGND +M.OLB +Name AGND_IN +"NET NAME" D +OLB +P30 ACC +P_GND +"Part Number" +PGND PGND +RA +"RF GND" RF GND +RFGND +Rules.Routing.RestrictedVias.00000 PTH18 STANDARDVIA +SLEEP_XTAL_IN +"Source Path" C:\WIN95\ORCAD\CAPTURE\LIBRARY\CAPSYM.OLB +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +SYM.OLB +System_Gnd +TGND +UGND +v A-GND +V+ 10V +V-CLK +Value GNDTFT +VAR 10V +VAUL AUDIO-GND +VBAT +VBATR +vcc +} +NET VDD_MCU +{ +CARDVCC +DCDIS +Description VCC +GFGF +"Part Number" +Rules.Routing.RestrictedVias.00000 VIA12 VIA18 VIA27 VIA78 +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +Value 3V +VBAT VBAT +vcc d +VDD 3.0V +} +NET $$$6153 +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET VDD_LINK +{ +CARDVCC +DCDIS +Description VCC +GFGF +"Part Number" +Rules.Routing.RestrictedVias.00000 VIA12 VIA18 VIA27 VIA78 +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +Value 3V +VBAT VBAT +vcc d +VDD 3.0V +} +NET PB0/RST +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET $$$16580 +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET $$$18572 +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET $$$2340 +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET $$$2339 +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET PA14/TCK/SWCLK +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET $$$13609 +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET $$$13607 +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET $$$13605 +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET $$$29264 +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET $$$26932 +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET $$$26931 +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET $$$14362 +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET LED_RUN/PA8 +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET NSLINK_USART1_TX +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET NSLINK_USART1_RX +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET NSLINK_TCK_SWCLK +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET PA13/TMS/SWDIO +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET $$$18547 +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET NSLINK_TMS_SWDIO +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET $$$4465 +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET 5V +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET $$$23084 +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET LED_CON/PB6 +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET $$$3902 +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET $$$32474 +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET $$$32494 +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET $$$32275 +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET $$$32273 +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET PA7 +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET PA5 +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET PA15 +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET PA13 +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET PA1 +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET PA2/TX1 +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET PA11 +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET PA14 +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET $$$13829 +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET PA3/RX1 +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET PA9/SWDCK +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET PA10 +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET PB0 +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET PB1 +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET PA0 +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET PA4 +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET PA6 +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET PA8/SWDIO +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET $$$1153 +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET $$$14234 +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET $$$14321 +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET $$$27316 +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET $$$27329 +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET $$$28366 +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET $$$28367 +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET $$$29131 +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET $$$29134 +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET PA12 +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET $$$1150 +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET $$$6884 +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET $$$6886 +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET $$$6888 +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET $$$7234 +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +NET $$$7236 +{ +Strategy.Center.Priority 1 +Strategy.Fanout.Priority 1 +Strategy.Miters.Priority 1 +Strategy.Optimize.Priority 1 +Strategy.Patterns.Priority 1 +Strategy.Route.Priority 1 +Strategy.TestPoint.Priority 1 +Strategy.Tune.Priority 1 +} +PART J4 +{ +DECAL +Description 6 pin header +} +PART R4 +{ +Description SURFACE MOUNT RESISTOR 0.031 X 0.061 INCHES, 1/10W +"Manufacturer #1" IPC SM-782 STD. +"Part Number" +Sim.Analog.Model +Sim.Analog.Order +Sim.Analog.Prefix R +Tolerance +Value 10K +} +PART Y1 +{ +Value 8MHz +} +PART J12 +{ +Marking +} +PART R24 +{ +Description SURFACE MOUNT RESISTOR 0.031 X 0.061 INCHES, 1/10W +"Manufacturer #1" IPC SM-782 STD. +"Part Number" +Sim.Analog.Model +Sim.Analog.Order +Sim.Analog.Prefix R +Tolerance +Value 4.7K +} +PART D5 +{ +Value SS14L +} +PART J8 +{ +Description Rechargeable Battery +Value +} +PART J15 +{ +Description Rechargeable Battery +Value +} +PART J5 +{ +Cost +Description 7 X 2 PIN POLARIZED HEADER, 0.1" CENTERS +"Manufacturer #1" +"Mating Spil Part #" ??? +"Part Number" +Sim.Analog.Model +Sim.Analog.Order Model$ +Sim.Analog.Prefix +"Spil Part #" 34-117 +} +PART R22 +{ +Description SURFACE MOUNT RESISTOR 0.031 X 0.061 INCHES, 1/10W +"Manufacturer #1" IPC SM-782 STD. +"Part Number" +Sim.Analog.Model +Sim.Analog.Order +Sim.Analog.Prefix R +Tolerance +Value 4.7K +} +PART R23 +{ +Description SURFACE MOUNT RESISTOR 0.031 X 0.061 INCHES, 1/10W +"Manufacturer #1" IPC SM-782 STD. +"Part Number" +Sim.Analog.Model +Sim.Analog.Order +Sim.Analog.Prefix R +Tolerance +Value 4.7K +} +PART R25 +{ +Description SURFACE MOUNT RESISTOR 0.031 X 0.061 INCHES, 1/10W +"Manufacturer #1" IPC SM-782 STD. +"Part Number" +Sim.Analog.Model +Sim.Analog.Order +Sim.Analog.Prefix R +Tolerance +Value 4.7K +} +PART R26 +{ +Description SURFACE MOUNT RESISTOR 0.031 X 0.061 INCHES, 1/10W +"Manufacturer #1" IPC SM-782 STD. +"Part Number" +Sim.Analog.Model +Sim.Analog.Order +Sim.Analog.Prefix R +Tolerance +Value 4.7K +} +PART C3 +{ +"Part Number" +Value 4.7uF +"Voltage Rating" +} +PART C30 +{ +"Part Number" +Value 12pF +"Voltage Rating" +} +PART C32 +{ +"Part Number" +Value 12pF +"Voltage Rating" +} +PART C14 +{ +"Part Number" +Value 0.1uF +"Voltage Rating" +} +PART C18 +{ +"Part Number" +Value 0.1uF +"Voltage Rating" +} +PART C19 +{ +"Part Number" +Value 4.7uF +"Voltage Rating" +} +PART C20 +{ +"Part Number" +Value 0.1uF +"Voltage Rating" +} +PART C5 +{ +"Part Number" +Value 0.1uF +"Voltage Rating" +} +PART C9 +{ +"Part Number" +Value 0.1uF +"Voltage Rating" +} +PART C1 +{ +"Part Number" +Value 0.1uF +"Voltage Rating" +} +PART C11 +{ +"Part Number" +Value 0.1uF +"Voltage Rating" +} +PART C2 +{ +"Part Number" +Value 0.1uF +"Voltage Rating" +} +PART C37 +{ +"Part Number" +Value 0.1uF +"Voltage Rating" +} +PART C22 +{ +ASSEMBLY SMT +DECAL O805,0805MIL +Description SURFACE MOUNT CAPACITOR 0.080 X 0.180 INCHES +"Manufacturer #1" IPC SM-782 STD. +"MFG #1" +"PART DESC" SURFACE MOUNT CAPACITOR 0.048 X 0.079 INCHES +"PART NB" +"Part Number" +Sim.Analog.Model +Sim.Analog.Order Model$ +Sim.Analog.Prefix +Tolerance +Value 10uF +"Voltage Rating" 6.3V +} +PART C31 +{ +ASSEMBLY SMT +DECAL O805,0805MIL +Description SURFACE MOUNT CAPACITOR 0.080 X 0.180 INCHES +"Manufacturer #1" IPC SM-782 STD. +"MFG #1" +"PART DESC" SURFACE MOUNT CAPACITOR 0.048 X 0.079 INCHES +"PART NB" +"Part Number" +Sim.Analog.Model +Sim.Analog.Order Model$ +Sim.Analog.Prefix +Tolerance +Value 10uF +"Voltage Rating" 6.3V +} +PART C7 +{ +ASSEMBLY SMT +DECAL O805,0805MIL +Description SURFACE MOUNT CAPACITOR 0.080 X 0.180 INCHES +"Manufacturer #1" IPC SM-782 STD. +"MFG #1" +"PART DESC" SURFACE MOUNT CAPACITOR 0.048 X 0.079 INCHES +"PART NB" +"Part Number" +Sim.Analog.Model +Sim.Analog.Order Model$ +Sim.Analog.Prefix +Tolerance +Value 10uF +"Voltage Rating" 6.3V +} +PART J6 +{ +Description Rechargeable Battery +Value +} +PART U4 +{ +Geometry.Height 2400000dbunit +Value N32G452CCL7 +} +PART U1 +{ +Geometry.Height 1800000dbunit +Value NS3603_OTS_20(28) +} +PART R1 +{ +Description SURFACE MOUNT RESISTOR 0.031 X 0.061 INCHES, 1/10W +"Manufacturer #1" IPC SM-782 STD. +"Part Number" +Sim.Analog.Model +Sim.Analog.Order +Sim.Analog.Prefix R +Tolerance +Value 4.7K +} +PART R10 +{ +Description SURFACE MOUNT RESISTOR 0.031 X 0.061 INCHES, 1/10W +"Manufacturer #1" IPC SM-782 STD. +"Part Number" +Sim.Analog.Model +Sim.Analog.Order +Sim.Analog.Prefix R +Tolerance +Value 10K +} +PART R11 +{ +Description SURFACE MOUNT RESISTOR 0.031 X 0.061 INCHES, 1/10W +"Manufacturer #1" IPC SM-782 STD. +"Part Number" +Sim.Analog.Model +Sim.Analog.Order +Sim.Analog.Prefix R +Tolerance +Value 33R +} +PART R12 +{ +Description SURFACE MOUNT RESISTOR 0.031 X 0.061 INCHES, 1/10W +"Manufacturer #1" IPC SM-782 STD. +"Part Number" +Sim.Analog.Model +Sim.Analog.Order +Sim.Analog.Prefix R +Tolerance +Value 33R +} +PART R13 +{ +Description SURFACE MOUNT RESISTOR 0.031 X 0.061 INCHES, 1/10W +"Manufacturer #1" IPC SM-782 STD. +"Part Number" +Sim.Analog.Model +Sim.Analog.Order +Sim.Analog.Prefix R +Tolerance +Value 4.7K +} +PART R14 +{ +Description SURFACE MOUNT RESISTOR 0.031 X 0.061 INCHES, 1/10W +"Manufacturer #1" IPC SM-782 STD. +"Part Number" +Sim.Analog.Model +Sim.Analog.Order +Sim.Analog.Prefix R +Tolerance +Value 4.7K +} +PART R15 +{ +Description SURFACE MOUNT RESISTOR 0.031 X 0.061 INCHES, 1/10W +"Manufacturer #1" IPC SM-782 STD. +"Part Number" +Sim.Analog.Model +Sim.Analog.Order +Sim.Analog.Prefix R +Tolerance +Value 4.7K +} +PART R16 +{ +Description SURFACE MOUNT RESISTOR 0.031 X 0.061 INCHES, 1/10W +"Manufacturer #1" IPC SM-782 STD. +"Part Number" +Sim.Analog.Model +Sim.Analog.Order +Sim.Analog.Prefix R +Tolerance +Value 4.7K +} +PART R17 +{ +Description SURFACE MOUNT RESISTOR 0.031 X 0.061 INCHES, 1/10W +"Manufacturer #1" IPC SM-782 STD. +"Part Number" +Sim.Analog.Model +Sim.Analog.Order +Sim.Analog.Prefix R +Tolerance +Value 4.7K +} +PART R18 +{ +Description SURFACE MOUNT RESISTOR 0.031 X 0.061 INCHES, 1/10W +"Manufacturer #1" IPC SM-782 STD. +"Part Number" +Sim.Analog.Model +Sim.Analog.Order +Sim.Analog.Prefix R +Tolerance +Value 10K +} +PART R19 +{ +Description SURFACE MOUNT RESISTOR 0.031 X 0.061 INCHES, 1/10W +"Manufacturer #1" IPC SM-782 STD. +"Part Number" +Sim.Analog.Model +Sim.Analog.Order +Sim.Analog.Prefix R +Tolerance +Value 100R +} +PART R2 +{ +Description SURFACE MOUNT RESISTOR 0.031 X 0.061 INCHES, 1/10W +"Manufacturer #1" IPC SM-782 STD. +"Part Number" +Sim.Analog.Model +Sim.Analog.Order +Sim.Analog.Prefix R +Tolerance +Value 4.7K +} +PART R20 +{ +Description SURFACE MOUNT RESISTOR 0.031 X 0.061 INCHES, 1/10W +"Manufacturer #1" IPC SM-782 STD. +"Part Number" +Sim.Analog.Model +Sim.Analog.Order +Sim.Analog.Prefix R +Tolerance +Value 4.7K +} +PART R21 +{ +Description SURFACE MOUNT RESISTOR 0.031 X 0.061 INCHES, 1/10W +"Manufacturer #1" IPC SM-782 STD. +"Part Number" +Sim.Analog.Model +Sim.Analog.Order +Sim.Analog.Prefix R +Tolerance +Value 4.7K +} +PART R3 +{ +Description SURFACE MOUNT RESISTOR 0.031 X 0.061 INCHES, 1/10W +"Manufacturer #1" IPC SM-782 STD. +"Part Number" +Sim.Analog.Model +Sim.Analog.Order +Sim.Analog.Prefix R +Tolerance +Value 4.7K +} +PART R5 +{ +Description SURFACE MOUNT RESISTOR 0.031 X 0.061 INCHES, 1/10W +"Manufacturer #1" IPC SM-782 STD. +"Part Number" +Sim.Analog.Model +Sim.Analog.Order +Sim.Analog.Prefix R +Tolerance +Value 1K +} +PART R6 +{ +Description SURFACE MOUNT RESISTOR 0.031 X 0.061 INCHES, 1/10W +"Manufacturer #1" IPC SM-782 STD. +"Part Number" +Sim.Analog.Model +Sim.Analog.Order +Sim.Analog.Prefix R +Tolerance +Value 10K +} +PART R7 +{ +Description SURFACE MOUNT RESISTOR 0.031 X 0.061 INCHES, 1/10W +"Manufacturer #1" IPC SM-782 STD. +"Part Number" +Sim.Analog.Model +Sim.Analog.Order +Sim.Analog.Prefix R +Tolerance +Value 10K +} +PART R8 +{ +Description SURFACE MOUNT RESISTOR 0.031 X 0.061 INCHES, 1/10W +"Manufacturer #1" IPC SM-782 STD. +"Part Number" +Sim.Analog.Model +Sim.Analog.Order +Sim.Analog.Prefix R +Tolerance +Value 10K +} +PART R9 +{ +Description SURFACE MOUNT RESISTOR 0.031 X 0.061 INCHES, 1/10W +"Manufacturer #1" IPC SM-782 STD. +"Part Number" +Sim.Analog.Model +Sim.Analog.Order +Sim.Analog.Prefix R +Tolerance +Value 10K +} +PART C52 +{ +"Part Number" +Value 0.1uF +"Voltage Rating" +} +PART J11 +{ +Description Rechargeable Battery +Value +} +PART J13 +{ +Description Rechargeable Battery +Value +} +PART J14 +{ +Description Rechargeable Battery +Value +} +PART J16 +{ +Description Rechargeable Battery +Value +} +PART J17 +{ +Description Rechargeable Battery +Value +} +PART J3 +{ +Description Rechargeable Battery +Value +} +PART J7 +{ +Description Rechargeable Battery +Value +} +PART J9 +{ +Description Rechargeable Battery +Value +} +PART J18 +{ +Description Rechargeable Battery +Value +} +DECAL CON_254_2P +{ +Design.Timestamp 2019.10.09.07.24.44 +} +DECAL CONDIP2_BAT +{ +Design.Timestamp 2019.02.13.10.21.10 +} +DECAL CONDIP2_A +{ +Design.Timestamp 2018.10.26.01.11.31 +} +DECAL CON_MINIUSB +{ +Design.Timestamp 2017.04.17.08.05.19 +} +DECAL CAPC5025X71L +{ +Design.Timestamp 2019.10.17.05.08.53 +Geometry.Height 1065000dbunit +} +DECAL 0805_LED_2 +{ +Design.Timestamp 2018.10.29.01.38.29 +} +DECAL 0805_LED-1 +{ +Design.Timestamp 2019.02.01.02.10.16 +} +DECAL 0805_LED-3 +{ +Design.Timestamp 2019.02.01.02.12.32 +} +DECAL 0805-LED +{ +Design.Timestamp 2019.02.01.02.45.47 +} +DECAL R0402 +{ +Design.Timestamp 2019.10.12.01.14.32 +} +DECAL SOT223 +{ +Design.Timestamp 2013.09.15.05.20.28 +} +DECAL SKPM +{ +Design.Timestamp 2019.01.05.10.49.51 +} +DECAL SIP-4P +{ +Design.Timestamp 2016.08.24.02.23.56 +} +DECAL CON_254_4P +{ +Design.Timestamp 2019.04.15.09.48.40 +} +DECAL SPX1117-3V3 +{ +Design.Timestamp 2013.04.28.00.47.45 +} +DECAL SOD123 +{ +Design.Timestamp 2019.12.01.15.51.33 +} +DECAL 2.54MM_CON3P +{ +Design.Timestamp 2019.12.01.16.48.56 +} +DECAL HEADER16 +{ +Design.Timestamp 1999.08.31.15.20.17 +} +DECAL SMD3225 +{ +Design.Timestamp 2020.04.25.07.49.23 +} +DECAL RES0402 +{ +Design.Timestamp 2022.07.11.06.14.24 +} +DECAL CAP0603 +{ +Design.Timestamp 2012.03.13.01.52.00 +} +DECAL CAP0402 +{ +Design.Timestamp 2022.07.11.03.22.45 +} +DECAL CAP0805 +{ +Design.Timestamp 2012.03.13.01.53.37 +} +DECAL 2.54MM_CON2X16P +{ +Design.Timestamp 2022.10.24.07.52.45 +} +DECAL NS-LQFP48-50P900X900X160 +{ +Design.Timestamp 2022.10.24.08.00.46 +Geometry.Height 2400000dbunit +} +DECAL NS-TSSOP20-65P650X640 +{ +Design.Timestamp 2022.10.24.08.00.46 +Geometry.Height 1800000dbunit +} +PARTTYPE CONDIP2_A +{ +Description Rechargeable Battery +Design.Timestamp 2018.10.26.01.10.15 +Value 4.2V/0.5A +} +PARTTYPE CRYSTAL_2PIN +{ +Design.Timestamp 2019.09.11.10.54.21 +Value 8MHz +} +PARTTYPE LED0805 +{ +Design.Timestamp 2019.01.18.06.40.34 +} +PARTTYPE R0402 +{ +Design.Timestamp 2017.09.01.11.30.47 +Value 0R +} +PARTTYPE SW_2P +{ +Design.Timestamp 2019.01.05.10.52.56 +} +PARTTYPE CON-SIP-4P +{ +Design.Timestamp 2019.01.03.10.25.02 +} +PARTTYPE DIODE_2 +{ +Design.Timestamp 2019.12.01.15.48.43 +} +PARTTYPE CON1X3 +{ +Design.Timestamp 2019.12.01.16.15.04 +Marking +} +PARTTYPE MINIUSB +{ +DECAL +Description 6 pin header +Design.Timestamp 2019.12.11.09.21.39 +} +PARTTYPE AMS1117-3.3 +{ +Design.Timestamp 2019.12.11.09.57.22 +} +PARTTYPE HEADER-8X2 +{ +Cost +Description 7 X 2 PIN POLARIZED HEADER, 0.1" CENTERS +Design.Timestamp 2019.03.12.09.21.05 +"Manufacturer #1" +"Mating Spil Part #" ??? +"Part Number" +Sim.Analog.Model +Sim.Analog.Order Model$ +Sim.Analog.Prefix +"Spil Part #" 34-117 +} +PARTTYPE RES0402 +{ +Description SURFACE MOUNT RESISTOR 0.031 X 0.061 INCHES, 1/10W +Design.Timestamp 2022.10.24.07.10.50 +"Manufacturer #1" IPC SM-782 STD. +"Part Number" +Sim.Analog.Model +Sim.Analog.Order +Sim.Analog.Prefix R +Tolerance +Value 10K +} +PARTTYPE CAP0603 +{ +Design.Timestamp 2022.10.24.06.32.20 +"Part Number" +Value 4.7uF +"Voltage Rating" +} +PARTTYPE CAP0402 +{ +Design.Timestamp 2022.10.24.07.10.28 +"Part Number" +Value 0.1uF +"Voltage Rating" +} +PARTTYPE CAP0805 +{ +ASSEMBLY SMT +DECAL O805,0805MIL +Description SURFACE MOUNT CAPACITOR 0.080 X 0.180 INCHES +Design.Timestamp 2022.10.24.07.07.39 +"Manufacturer #1" IPC SM-782 STD. +"MFG #1" +"PART DESC" SURFACE MOUNT CAPACITOR 0.048 X 0.079 INCHES +"PART NB" +"Part Number" +Sim.Analog.Model +Sim.Analog.Order Model$ +Sim.Analog.Prefix +Tolerance +Value 10uF +"Voltage Rating" 6.3V +} +PARTTYPE HEAD2X16 +{ +Design.Timestamp 2022.10.24.07.53.38 +} +PARTTYPE N32G452CCL7 +{ +Design.Timestamp 2022.10.24.07.55.59 +Value N32G455CCL7 +} +PARTTYPE N32G003F5S7 +{ +Design.Timestamp 2022.10.24.07.36.32 +Value NS3603_OTS_20(28) +} +PCB DEFAULT +{ +Accordion.HierarchyLevel 8 +Accordion.Amplitude.Max 30 +Accordion.Amplitude.Min 3 +Accordion.Gap.Min 1 +Accordion.Miters.Arcs No +Accordion.Miters.Ratio 1.5 +AutoDimensioning.Line_Layer 124 +AutoDimensioning.Marker_Shape YYNNNY +AutoDimensioning.Preview_Type 1 +AutoDimensioning.Text_AngularPrecision 0 0 0 +AutoDimensioning.Text_DisplacementValue 0 +AutoDimensioning.Text_Layer 124 +AutoDimensioning.Text_NumberPrecision 0 1 2 +AutoDimensioning.Text_Suffix mil##mm##" +Blaze.TestPoint.Color 8 +Blaze.Thermal.Color 8 +"CAM.Apply Oversize To All Pads" Yes +"DFT.Allow Stubs" Yes +"DFT.Generate Test Points" No +"DFT.Grid X-Coordinate" 1500dbunit +"DFT.Grid Y-Coordinate" 1500dbunit +"DFT.Insert Test Point Vias" No +"DFT.Preserve Test Points" No +"DFT.Probe Pins" Yes +"DFT.Probe to Pad Clearance" 228600dbunit +"DFT.Probe to Trace Clearance" 228600dbunit +"DFT.Stub Length" 19050000dbunit +"DFT.Use Via Grid" Yes +DiffPair.MaxIrregularLength 19050000dbunit +DiffPair.MinControlledLength 80 +DiffPair.RestrictPairTuneInGap No +DiffPair.RestrictSmallAccordionsInPairs No +DiffPair.TunePairsToZeroTolerance Yes +Guard.BandColor 0 +LaserDrillOversize 114300 +PADS3D.Objects.Silkscreen.Refresh 21 +PADS3D.Objects.SolderMask.Refresh 21 +Placement.Grid.Use Yes +Placement.Grid.X 1500dbunit +Placement.Grid.Y 1500dbunit +PreservePadsOnNoPlaneLayers No +Routing.ExtraLengthPercent 100 +Routing.MaxChannelWidth 3810000dbunit +Routing.MeanderBeforeTune Yes +Routing.SoftLengthRrules Yes +Rules.ViaAtSMD No +Rules.Fanout.Alignment Alternate +Rules.Fanout.AlignmentBGA Quadrant +Rules.Fanout.Direction Both Sides +Rules.Fanout.DirectionBGA 45 +Rules.Fanout.DirectionBGAstaggered Horizontal +Rules.Fanout.ViaSpacing Use Grid +Rules.Fanout.Alignment.Multi-Row Yes +Rules.Fanout.Length.Maximum 9525000dbunit +Rules.Fanout.Length.Unlimited Yes +Rules.Fanout.Nets.Plane Yes +Rules.Fanout.Nets.Signal No +Rules.Fanout.Nets.UnusedPins No +Rules.Fanout.Sharing.Pin Yes +Rules.Fanout.Sharing.SMD Yes +Rules.Fanout.Sharing.Trace No +Rules.Fanout.Sharing.Via Yes +Rules.PadEntry.AnyAngle Yes +Rules.PadEntry.Corner Yes +Rules.PadEntry.Side Yes +Rules.PadEntry.Soft Yes +Rules.ViaAtSMD.Center Yes +Rules.ViaAtSMD.Ends Yes +Rules.ViaAtSMD.FitInside Yes +"Single Sided Board" No +Strategy.Center.Intensity Low +Strategy.Center.Pass No +Strategy.Center.Pause No +Strategy.Center.PlanePriority 0 +Strategy.Center.Priority 1 +Strategy.Center.Protect No +Strategy.Fanout.Intensity Medium +Strategy.Fanout.Pass No +Strategy.Fanout.Pause No +Strategy.Fanout.PlanePriority 0 +Strategy.Fanout.Priority 1 +Strategy.Fanout.Protect No +Strategy.Miters.Intensity Low +Strategy.Miters.Pass No +Strategy.Miters.Pause No +Strategy.Miters.PlanePriority 0 +Strategy.Miters.Priority 1 +Strategy.Miters.Protect No +Strategy.Optimize.Intensity Low +Strategy.Optimize.Pass Yes +Strategy.Optimize.Pause No +Strategy.Optimize.PlanePriority 0 +Strategy.Optimize.Priority 1 +Strategy.Optimize.Protect No +Strategy.Patterns.Intensity Medium +Strategy.Patterns.Pass No +Strategy.Patterns.Pause No +Strategy.Patterns.PlanePriority 0 +Strategy.Patterns.Priority 1 +Strategy.Patterns.Protect No +Strategy.Route.Intensity Medium +Strategy.Route.Pass Done +Strategy.Route.Pause No +Strategy.Route.PlanePriority 0 +Strategy.Route.Priority 1 +Strategy.Route.Protect No +Strategy.TestPoint.Intensity Low +Strategy.TestPoint.Pass No +Strategy.TestPoint.Pause No +Strategy.TestPoint.PlanePriority 0 +Strategy.TestPoint.Priority 1 +Strategy.TestPoint.Protect No +Strategy.Tune.Intensity Medium +Strategy.Tune.Pass No +Strategy.Tune.Pause No +Strategy.Tune.PlanePriority 0 +Strategy.Tune.Priority 1 +Strategy.Tune.Protect No +} +} + +*END* OF ASCII OUTPUT FILE diff --git a/docs/N32G003F5S7-STB_V1.0/N32G003F5S7-STB_V1.0.pcb b/docs/N32G003F5S7-STB_V1.0/N32G003F5S7-STB_V1.0.pcb new file mode 100644 index 0000000..746e530 Binary files /dev/null and b/docs/N32G003F5S7-STB_V1.0/N32G003F5S7-STB_V1.0.pcb differ diff --git a/docs/N32G003F5S7-STB_V1.0/N32G003F5S7-STB_V1.0.pdf b/docs/N32G003F5S7-STB_V1.0/N32G003F5S7-STB_V1.0.pdf new file mode 100644 index 0000000..25fe55c Binary files /dev/null and b/docs/N32G003F5S7-STB_V1.0/N32G003F5S7-STB_V1.0.pdf differ diff --git a/docs/N32G003F5S7-STB_V1.0/N32G003F5S7-STB_V1.0.sch b/docs/N32G003F5S7-STB_V1.0/N32G003F5S7-STB_V1.0.sch new file mode 100644 index 0000000..b16a812 Binary files /dev/null and b/docs/N32G003F5S7-STB_V1.0/N32G003F5S7-STB_V1.0.sch differ diff --git a/docs/N32G003F5S7-STB_V1.0/N32G003F5S7-STB_V1.0.txt b/docs/N32G003F5S7-STB_V1.0/N32G003F5S7-STB_V1.0.txt new file mode 100644 index 0000000..afb0a18 --- /dev/null +++ b/docs/N32G003F5S7-STB_V1.0/N32G003F5S7-STB_V1.0.txt @@ -0,0 +1,9100 @@ +*PADS-LOGIC-V9.0-CP936* DESIGN EXPORT FILE FROM PADS LOGIC VVX.2.7 +*SCH* GENERAL PARAMETERS OF THE SCHEMATIC DESIGN" + +CUR SHEET 1 Current Active Sheet +USERGRID 2 10 Design and Label/Text grid settings +LINEWIDTH 10 Width items will be created with +CONNWIDTH 10 Width used to plot connections +BUSWIDTH 25 Width used to plot buses +BUSANGLE 25 Angle used when plotting buses +NNVISPWRGND 4 Pwr/Gnd netname visibility default flag +PCBFLAGS 1039 PCB Netlist and ECO options +PINNAMESIZE 97 10 Height and LineWidth used by pin names +TEXTSIZE 97 10 Height and LineWidth text will be created width +JOBTIME 0 Amount of time spent on this LOGIC design +DOTGRID 10 Space in thous/inch between graphic dots +BACKUPTIME 5 Number of minutes between database backups +TIEDOTSIZE 75 Diameter of tiedot point +REFNAMESIZE 100 10 Height and LineWidth used by part ref. names +PARTNAMESIZE 100 10 Height and LineWidth used by part type names +PINNOSIZE 97 10 Height and LineWidth used by pin numbers +NETNAMESIZE 100 10 Height and LineWidth used by net names +REAL WIDTH 36 Widths greater then this are displayed real size +SHEET SIZE A4 +UNITS 0 Rules units type +JOBNAME N32G003F5S7-STB_V1.0.sch +NTXCOL 11 9 +HIRCOL 14 +LINCOL 4 +TXTCOL 0 15 +CONCOL 4 +BUSCOL 14 +PTXCOL 0 15 +COMCOL 9 +NMCOL 12 15 +PNMCOL 12 15 +PINCOL 0 15 +NETCOL 1 15 +FBGCOL 12 15 +OFFREFVIEW 0 Offsheet references visibility default flag +OFFREFNUM 0 Offsheet references per line +SHEETNUMSEP [] Sheet Number separators +FONT MODE System +DEFAULT FONT "Regular Tahoma" +BORDER NAME DRW_NATIONS_A4 +FIELDCOL 1 15 + +*CAM* PLOTTER SETTINGS +*REMARK* PARENT_KEYWORD PARENT_VALUE +*REMARK* [ { +*REMARK* CHILD_KEYWORD CHILD_VALUE +*REMARK* [ CHILD_KEYWORD CHILD_VALUE +*REMARK* [ { +*REMARK* GRAND_CHILD_KEYWORD GRAND_CHILD_VALUE [...] +*REMARK* } ]] +*REMARK* } ] + +PLOT_SECTION 5.0 +{ +PLOT_DEFAULTS_PHOTO_PLOTTER NULL +{ +DEFAULT_FILE_PREFIX Z32HUA_MPOS_V1 +DEFAULT_SCALE 1 1 +DEFAULT_ORIENTATION 0 +DEFAULT_JUSTIFICATION SF +DEFAULT_OFFSETS 0 0 +DEFAULT_WINDOW_PLOT N +DEFAULT_PLOT_JOBNAME N +DEFAULT_PLOT_OLE N +DEFAULT_SHEET Current +DEFAULT_CONNECTIONS 1 +DEFAULT_BUSSES 1 +DEFAULT_LINES 1 +DEFAULT_TEXT 1 +DEFAULT_PARTS 1 +DEFAULT_REFDES 1 +DEFAULT_PARTTYPES 1 +DEFAULT_PARTEXT 1 +DEFAULT_PINNUMBERS 1 +DEFAULT_PINNAMES 1 +DEFAULT_NETNAMES 1 +DEFAULT_HIERSYMS 1 +} +PLOT_DEFAULTS_PEN_PLOTTER NULL +{ +DEFAULT_FILE_PREFIX Z32HUA_FNT_V0 +DEFAULT_SCALE 1 1 +DEFAULT_ORIENTATION 0 +DEFAULT_JUSTIFICATION SF +DEFAULT_OFFSETS 0 0 +DEFAULT_WINDOW_PLOT N +DEFAULT_PLOT_JOBNAME Y +DEFAULT_PLOT_OLE N +DEFAULT_SHEET Selected +DEFAULT_SHEET_LIST NULL +{ +SHEET_1 2 +SHEET_2 4 +SHEET_3 5 +SHEET_4 6 +SHEET_5 8 +SHEET_6 1 +SHEET_7 7 +} +DEFAULT_CONNECTIONS 1 +DEFAULT_BUSSES 1 +DEFAULT_LINES 1 +DEFAULT_TEXT 1 +DEFAULT_PARTS 1 +DEFAULT_REFDES 1 +DEFAULT_PARTTYPES 1 +DEFAULT_PARTEXT 1 +DEFAULT_PINNUMBERS 1 +DEFAULT_PINNAMES 1 +DEFAULT_NETNAMES 1 +DEFAULT_HIERSYMS 1 +} +PLOT_DEFAULTS_PRINTER NULL +{ +DEFAULT_FILE_PREFIX NZ3101_FNT_BCM_0 +DEFAULT_SCALE 1 1 +DEFAULT_ORIENTATION 0 +DEFAULT_JUSTIFICATION SF +DEFAULT_OFFSETS 0 0 +DEFAULT_WINDOW_PLOT N +DEFAULT_PLOT_JOBNAME N +DEFAULT_PLOT_OLE N +DEFAULT_SHEET All +DEFAULT_CONNECTIONS 1 +DEFAULT_BUSSES 1 +DEFAULT_LINES 1 +DEFAULT_TEXT 1 +DEFAULT_PARTS 1 +DEFAULT_REFDES 1 +DEFAULT_PARTTYPES 1 +DEFAULT_PARTEXT 1 +DEFAULT_PINNUMBERS 1 +DEFAULT_PINNAMES 1 +DEFAULT_NETNAMES 1 +DEFAULT_HIERSYMS 1 +} +PLOT_AUGMENT_ON_THE_FLY Y +} + +*MISC* MISCELLANEOUS PARAMETERS +*REMARK* PARENT_KEYWORD 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October 2015 + ******************************************************************************/ +/* Copyright (c) 2009 - 2015 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ + + +#if (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1U) && (__FPU_USED == 1U) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04U) || (__CORTEX_M == 0x07U) */ + + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in integer value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in two unsigned short values. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + +/** + \brief Reverse byte order in signed short value + \details Reverses the byte order in a signed short value with sign extension to integer. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] value Value to rotate + \param [in] value Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + int32_t s = 4 /*sizeof(v)*/ * 8 - 1; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return(result); +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#endif /* (__CORTEX_M >= 0x03U) || (__CORTEX_SC >= 300U) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (__CORTEX_M >= 0x04U) /* only for Cortex-M4 and above */ + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* (__CORTEX_M >= 0x04) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/firmware/CMSIS/core/core_cm0.h b/firmware/CMSIS/core/core_cm0.h new file mode 100644 index 0000000..9d7a19f --- /dev/null +++ b/firmware/CMSIS/core/core_cm0.h @@ -0,0 +1,665 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V2.10 + * @date 19. July 2011 + * + * @note + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + + +/** \mainpage CMSIS Cortex-M0 + + This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer. + It consists of: + + - Cortex-M Core Register Definitions + - Cortex-M functions + - Cortex-M instructions + + The CMSIS Cortex-M0 Core Peripheral Access Layer contains C and assembly functions that ease + access to the Cortex-M Core + */ + +/** \defgroup CMSIS_MISRA_Exceptions CMSIS MISRA-C:2004 Compliance Exceptions + CMSIS violates following MISRA-C2004 Rules: + + - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** \defgroup CMSIS_core_definitions CMSIS Core Definitions + This file defines all structures and symbols for CMSIS core: + - CMSIS version number + - Cortex-M core + - Cortex-M core Revision Number + @{ + */ + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (0x02) /*!< [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (0x10) /*!< [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ + +#define __CORTEX_M (0x00) /*!< Cortex core */ + + +#if defined ( __CC_ARM ) + #define __ASM __asm /*!< asm keyword for ARM Compiler */ + #define __INLINE __inline /*!< inline keyword for ARM Compiler */ + +#elif defined ( __ICCARM__ ) + #define __ASM __asm /*!< asm keyword for IAR Compiler */ + #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ + +#elif defined ( __GNUC__ ) + #define __ASM __asm /*!< asm keyword for GNU Compiler */ + #define __INLINE inline /*!< inline keyword for GNU Compiler */ + +#elif defined ( __TASKING__ ) + #define __ASM __asm /*!< asm keyword for TASKING Compiler */ + #define __INLINE inline /*!< inline keyword for TASKING Compiler */ + +#endif + +/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */ +#define __FPU_USED 0 + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + /* add preprocessor checks */ +#endif + +#include /*!< standard types definitions */ +#include "core_cmInstr.h" /*!< Core Instruction Access */ +#include "core_cmFunc.h" /*!< Core Function Access */ + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000 + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2 + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0 + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +#ifdef __cplusplus + #define __I volatile /*!< defines 'read only' permissions */ +#else + #define __I volatile const /*!< defines 'read only' permissions */ +#endif +#define __O volatile /*!< defines 'write only' permissions */ +#define __IO volatile /*!< defines 'read / write' permissions */ + +/*@} end of group CMSIS_core_definitions */ + + + +/******************************************************************************* + * Register Abstraction + ******************************************************************************/ +/** \defgroup CMSIS_core_register CMSIS Core Register + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register +*/ + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CORE CMSIS Core + Type definitions for the Cortex-M Core Registers + @{ + */ + +/** \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ +#else + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ +#endif + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + + +/** \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + + +/** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ +#if (__CORTEX_M != 0x04) + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ +#else + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ +#endif + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + + +/** \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/*@} end of group CMSIS_CORE */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC CMSIS NVIC + Type definitions for the Cortex-M NVIC Registers + @{ + */ + +/** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31]; + __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31]; + __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31]; + __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31]; + uint32_t RESERVED4[64]; + __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SCB CMSIS SCB + Type definitions for the Cortex-M System Control Block Registers + @{ + */ + +/** \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick CMSIS SysTick + Type definitions for the Cortex-M System Timer Registers + @{ + */ + +/** \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug CMSIS Core Debug + Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP + and not via processor. Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** \ingroup CMSIS_core_register + @{ + */ + +/* Memory mapping of Cortex-M0 Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + ******************************************************************************/ +/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions +*/ + + + +/* ########################## NVIC functions #################################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions + @{ + */ + +/* Interrupt Priorities are WORD accessible only under ARMv6M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 ) +#define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) ) +#define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) ) + + +/** \brief Enable External Interrupt + + This function enables a device specific interrupt in the NVIC interrupt controller. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the external interrupt to enable + */ +static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Disable External Interrupt + + This function disables a device specific interrupt in the NVIC interrupt controller. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the external interrupt to disable + */ +static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Get Pending Interrupt + + This function reads the pending register in the NVIC and returns the pending bit + for the specified interrupt. + + \param [in] IRQn Number of the interrupt for get pending + \return 0 Interrupt status is not pending + \return 1 Interrupt status is pending + */ +static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + + +/** \brief Set Pending Interrupt + + This function sets the pending bit for the specified interrupt. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the interrupt for set pending + */ +static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + + +/** \brief Clear Pending Interrupt + + This function clears the pending bit for the specified interrupt. + The interrupt number cannot be a negative value. + + \param [in] IRQn Number of the interrupt for clear pending + */ +static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ +} + + +/** \brief Set Interrupt Priority + + This function sets the priority for the specified interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + Note: The priority cannot be set for every core interrupt. + + \param [in] IRQn Number of the interrupt for set priority + \param [in] priority Priority to set + */ +static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if(IRQn < 0) { + SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } + else { + NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) | + (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); } +} + + +/** \brief Get Interrupt Priority + + This function reads the priority for the specified interrupt. The interrupt + number can be positive to specify an external (device specific) + interrupt, or negative to specify an internal (core) interrupt. + + The returned priority value is automatically aligned to the implemented + priority bits of the microcontroller. + + \param [in] IRQn Number of the interrupt for get priority + \return Interrupt Priority + */ +static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) +{ + + if(IRQn < 0) { + return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */ + else { + return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ +} + + +/** \brief System Reset + + This function initiate a system reset request to reset the MCU. + */ +static __INLINE void NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + while(1); /* wait until reset */ +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions + @{ + */ + +#if (__Vendor_SysTickConfig == 0) + +/** \brief System Tick Configuration + + This function initialises the system tick timer and its interrupt and start the system tick timer. + Counter is in free running mode to generate periodical interrupts. + + \param [in] ticks Number of ticks between two interrupts + \return 0 Function succeeded + \return 1 Function failed + */ +static __INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ + + SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Cortex-M0 System Interrupts */ + SysTick->VAL = 0; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ + +#ifdef __cplusplus +} +#endif diff --git a/firmware/CMSIS/core/core_cmFunc.h b/firmware/CMSIS/core/core_cmFunc.h new file mode 100644 index 0000000..88819f9 --- /dev/null +++ b/firmware/CMSIS/core/core_cmFunc.h @@ -0,0 +1,609 @@ +/**************************************************************************//** + * @file core_cmFunc.h + * @brief CMSIS Cortex-M Core Function Access Header File + * @version V2.10 + * @date 26. July 2011 + * + * @note + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CORE_CMFUNC_H +#define __CORE_CMFUNC_H + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + +/* intrinsic void __enable_irq(); */ +/* intrinsic void __disable_irq(); */ + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +static __INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +static __INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** \brief Get ISPR Register + + This function returns the content of the ISPR Register. + + \return ISPR Register value + */ +static __INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +static __INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +static __INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +static __INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +static __INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +static __INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +static __INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +static __INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +static __INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +static __INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +static __INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xff); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +static __INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +static __INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +static __INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +static __INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief Enable IRQ Interrupts + + This function enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i"); +} + + +/** \brief Disable IRQ Interrupts + + This function disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i"); +} + + +/** \brief Get Control Register + + This function returns the content of the Control Register. + + \return Control Register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +/** \brief Set Control Register + + This function writes the given value to the Control Register. + + \param [in] control Control Register value to set + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) ); +} + + +/** \brief Get ISPR Register + + This function returns the content of the ISPR Register. + + \return ISPR Register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get APSR Register + + This function returns the content of the APSR Register. + + \return APSR Register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get xPSR Register + + This function returns the content of the xPSR Register. + + \return xPSR Register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** \brief Get Process Stack Pointer + + This function returns the current value of the Process Stack Pointer (PSP). + + \return PSP Register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, psp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Process Stack Pointer + + This function assigns the given value to the Process Stack Pointer (PSP). + + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) ); +} + + +/** \brief Get Main Stack Pointer + + This function returns the current value of the Main Stack Pointer (MSP). + + \return MSP Register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void) +{ + register uint32_t result; + + __ASM volatile ("MRS %0, msp\n" : "=r" (result) ); + return(result); +} + + +/** \brief Set Main Stack Pointer + + This function assigns the given value to the Main Stack Pointer (MSP). + + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) ); +} + + +/** \brief Get Priority Mask + + This function returns the current state of the priority mask bit from the Priority Mask Register. + + \return Priority Mask value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Priority Mask + + This function assigns the given value to the Priority Mask Register. + + \param [in] priMask Priority Mask + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) ); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Enable FIQ + + This function enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f"); +} + + +/** \brief Disable FIQ + + This function disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f"); +} + + +/** \brief Get Base Priority + + This function returns the current value of the Base Priority register. + + \return Base Priority register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_max" : "=r" (result) ); + return(result); +} + + +/** \brief Set Base Priority + + This function assigns the given value to the Base Priority register. + + \param [in] basePri Base Priority value to set + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (value) ); +} + + +/** \brief Get Fault Mask + + This function returns the current value of the Fault Mask register. + + \return Fault Mask register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +/** \brief Set Fault Mask + + This function assigns the given value to the Fault Mask register. + + \param [in] faultMask Fault Mask value to set + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) ); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + +#if (__CORTEX_M == 0x04) + +/** \brief Get FPSCR + + This function returns the current value of the Floating Point Status/Control register. + + \return Floating Point Status/Control register value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#else + return(0); +#endif +} + + +/** \brief Set FPSCR + + This function assigns the given value to the Floating Point Status/Control register. + + \param [in] fpscr Floating Point Status/Control value to set + */ +__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) ); +#endif +} + +#endif /* (__CORTEX_M == 0x04) */ + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all instrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +#endif /* __CORE_CMFUNC_H */ diff --git a/firmware/CMSIS/core/core_cmInstr.h b/firmware/CMSIS/core/core_cmInstr.h new file mode 100644 index 0000000..78d2ef8 --- /dev/null +++ b/firmware/CMSIS/core/core_cmInstr.h @@ -0,0 +1,585 @@ +/**************************************************************************//** + * @file core_cmInstr.h + * @brief CMSIS Cortex-M Core Instruction Access Header File + * @version V2.10 + * @date 19. July 2011 + * + * @note + * Copyright (C) 2009-2011 ARM Limited. All rights reserved. + * + * @par + * ARM Limited (ARM) is supplying this software for use with Cortex-M + * processor based microcontrollers. This file can be freely distributed + * within development tools that are supporting such ARM based processors. + * + * @par + * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED + * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. + * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR + * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. + * + ******************************************************************************/ + +#ifndef __CORE_CMINSTR_H +#define __CORE_CMINSTR_H + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/ +/* ARM armcc specific functions */ + +#if (__ARMCC_VERSION < 400677) + #error "Please use ARM Compiler Toolchain V4.0.677 or later!" +#endif + + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +#define __ISB() __isb(0xF) + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __dsb(0xF) + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __dmb(0xF) + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +static __INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +static __INLINE __ASM int32_t __REVSH(int32_t value) +{ + revsh r0, r0 + bx lr +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __rbit + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH(value, ptr) __strex(value, ptr) + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW(value, ptr) __strex(value, ptr) + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +#define __CLREX __clrex + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + +#endif /* (__CORTEX_M >= 0x03) */ + + + +#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/ +/* IAR iccarm specific functions */ + +#include + + +#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/ +/* GNU gcc specific functions */ + +/** \brief No Operation + + No Operation does nothing. This instruction can be used for code alignment purposes. + */ +__attribute__( ( always_inline ) ) static __INLINE void __NOP(void) +{ + __ASM volatile ("nop"); +} + + +/** \brief Wait For Interrupt + + Wait For Interrupt is a hint instruction that suspends execution + until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) static __INLINE void __WFI(void) +{ + __ASM volatile ("wfi"); +} + + +/** \brief Wait For Event + + Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +__attribute__( ( always_inline ) ) static __INLINE void __WFE(void) +{ + __ASM volatile ("wfe"); +} + + +/** \brief Send Event + + Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +__attribute__( ( always_inline ) ) static __INLINE void __SEV(void) +{ + __ASM volatile ("sev"); +} + + +/** \brief Instruction Synchronization Barrier + + Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or + memory, after the instruction has been completed. + */ +__attribute__( ( always_inline ) ) static __INLINE void __ISB(void) +{ + __ASM volatile ("isb"); +} + + +/** \brief Data Synchronization Barrier + + This function acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__attribute__( ( always_inline ) ) static __INLINE void __DSB(void) +{ + __ASM volatile ("dsb"); +} + + +/** \brief Data Memory Barrier + + This function ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__attribute__( ( always_inline ) ) static __INLINE void __DMB(void) +{ + __ASM volatile ("dmb"); +} + + +/** \brief Reverse byte order (32 bit) + + This function reverses the byte order in integer value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief Reverse byte order (16 bit) + + This function reverses the byte order in two unsigned short values. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief Reverse byte order in signed short value + + This function reverses the byte order in a signed short value with sign extension to integer. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value) +{ + uint32_t result; + + __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +#if (__CORTEX_M >= 0x03) + +/** \brief Reverse bit order of value + + This function reverses the bit order of the given value. + + \param [in] value Value to reverse + \return Reversed value + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + + +/** \brief LDR Exclusive (8 bit) + + This function performs a exclusive LDR command for 8 bit value. + + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint8_t result; + + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + + +/** \brief LDR Exclusive (16 bit) + + This function performs a exclusive LDR command for 16 bit values. + + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint16_t result; + + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + + +/** \brief LDR Exclusive (32 bit) + + This function performs a exclusive LDR command for 32 bit values. + + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) ); + return(result); +} + + +/** \brief STR Exclusive (8 bit) + + This function performs a exclusive STR command for 8 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (16 bit) + + This function performs a exclusive STR command for 16 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +/** \brief STR Exclusive (32 bit) + + This function performs a exclusive STR command for 32 bit values. + + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) ); + return(result); +} + + +/** \brief Remove the exclusive lock + + This function removes the exclusive lock which is created by LDREX. + + */ +__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void) +{ + __ASM volatile ("clrex"); +} + + +/** \brief Signed Saturate + + This function saturates a signed value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Unsigned Saturate + + This function saturates an unsigned value. + + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** \brief Count leading zeros + + This function counts the number of leading zeros of a data value. + + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value) +{ + uint8_t result; + + __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) ); + return(result); +} + +#endif /* (__CORTEX_M >= 0x03) */ + + + + +#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/ +/* TASKING carm specific functions */ + +/* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + +#endif + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + +#endif /* __CORE_CMINSTR_H */ diff --git a/firmware/CMSIS/device/n32g003.h b/firmware/CMSIS/device/n32g003.h new file mode 100644 index 0000000..8b268c0 --- /dev/null +++ b/firmware/CMSIS/device/n32g003.h @@ -0,0 +1,2510 @@ +/** +* Copyright (c) 2022, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** +*\*\file n32g003.h +*\*\author Nations +*\*\version v1.0.0 +*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. +**/ +#ifndef __N32G003_H__ +#define __N32G003_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +/*** N32G003_Library_Basic ***/ + +#if !defined USE_STDPERIPH_DRIVER +/** Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers **/ +#define USE_STDPERIPH_DRIVER +#endif + + +#define HSI_VALUE ((uint32_t)48000000) /* Value of the Internal oscillator in Hz*/ +#define HSI_40M ((uint32_t)40000000) +#define HSI_STARTUP_TIMEOUT ((uint16_t)0x0500) /* Time out for HSI start up */ + +/** n32g003 Standard Peripheral Library version number **/ +#define __n32g003_STDPERIPH_VERSION_MAIN (0x01) /* [31:24] main version */ +#define __n32g003_STDPERIPH_VERSION_SUB1 (0x00) /* [23:16] sub1 version */ +#define __n32g003_STDPERIPH_VERSION_SUB2 (0x00) /* [15:8] sub2 version */ +#define __n32g003_STDPERIPH_VERSION_RC (0x00) /* [7:0] release candidate */ +#define __n32g003_STDPERIPH_VERSION ( (__n32g003_STDPERIPH_VERSION_MAIN << 24)\ + |(__n32g003_STDPERIPH_VERSION_SUB1 << 16)\ + |(__n32g003_STDPERIPH_VERSION_SUB2 << 8)\ + |(__n32g003_STDPERIPH_VERSION_RC)) + +/** Configuration of the Cortex-M0 Processor and Core Peripherals **/ +#define __NVIC_PRIO_BITS 2 /* N32G003 uses 2 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ + +/*** N32G003 Interrupt Number Definition ***/ + +typedef enum IRQn +{ + /** Cortex-M0 Processor Exceptions Numbers **/ + NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /* 3 Cortex-M0 Hard Fault Interrupt */ + SVC_IRQn = -5, /* 11 Cortex-M0 SV Call Interrupt */ + PendSV_IRQn = -2, /* 14 Cortex-M0 Pend SV Interrupt */ + SysTick_IRQn = -1, /* 15 Cortex-M0 System Tick Interrupt */ + + /** N32G003 specific Interrupt Numbers **/ + PVD_IRQn = 0, /* PVD through EXTI Line 18 detect Interrupt */ + FLASH_IRQn = 1, /* FLASH Interrupt */ + EXTI0_1_IRQn = 2, /* EXTI Line 0 and 1 Interrupts */ + EXTI2_3_IRQn = 3, /* EXTI Line 2 and 3 Interrupts */ + EXTI4_17_IRQn = 4, /* EXTI Line 4 to 17 Interrupts */ + TIM1_BRK_UP_TRG_COM_IRQn = 5, /* TIM1 Break, Update, Trigger and Commutation Interrupts */ + TIM1_CC_IRQn = 6, /* TIM1 Capture Compare Interrupt */ + TIM3_IRQn = 7, /* TIM3 Interrupt */ + TIM6_IRQn = 8, /* TIM6 through EXTI Line 19 Interrupt */ + ADC_IRQn = 9, /* ADC global Interrupt */ + I2C_EV_IRQn = 10, /* I2C event Interrupt */ + I2C_ER_IRQn = 11, /* I2C error Interrupt */ + SPI_IRQn = 12, /* SPI Interrupt */ + UART1_IRQn = 13, /* UART1 Interrupt */ + UART2_IRQn = 14, /* UART2 Interrupt */ + COMP_IRQn = 15 /* COMP Interrupt */ +} IRQn_Type; + +#include "core_cm0.h" +#include "system_n32g003.h" +#include +#include + +/* n32g003 Standard Peripheral Library old types (maintained for legacy purpose) */ +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef const int32_t sc32; /* Read Only */ +typedef const int16_t sc16; /* Read Only */ +typedef const int8_t sc8; /* Read Only */ + +typedef __IO int32_t vs32; +typedef __IO int16_t vs16; +typedef __IO int8_t vs8; + +typedef __I int32_t vsc32; /* Read Only */ +typedef __I int16_t vsc16; /* Read Only */ +typedef __I int8_t vsc8; /* Read Only */ + +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +typedef const uint32_t uc32; /* Read Only */ +typedef const uint16_t uc16; /* Read Only */ +typedef const uint8_t uc8; /* Read Only */ + +typedef __IO uint32_t vu32; +typedef __IO uint16_t vu16; +typedef __IO uint8_t vu8; + +typedef __I uint32_t vuc32; /* Read Only */ +typedef __I uint16_t vuc16; /* Read Only */ +typedef __I uint8_t vuc8; /* Read Only */ + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus; + +/* n32g003 Standard Peripheral Library definitions (maintained for legacy purpose) */ +#define HSI_Value HSI_VALUE + +/*** Analog to Digital Converter ***/ +typedef struct +{ + __IO uint32_t STS; + __IO uint32_t CTRL1; + __IO uint32_t CTRL2; + __IO uint32_t CTRL3; + __IO uint32_t SAMPT; + __IO uint32_t WDGHIGH; + __IO uint32_t WDGLOW; + __IO uint32_t DAT0; + __IO uint32_t DAT1; + __IO uint32_t DAT2; + __IO uint32_t DAT3; + __IO uint32_t DAT4; + +} ADC_Module; + + +/*** CRC calculation unit ***/ +typedef struct +{ + uint32_t RESERVED0; + uint32_t RESERVED1; + uint32_t RESERVED2; + __IO uint8_t CRC16CTRL; + uint8_t RESERVED3; + uint16_t RESERVED4; + __IO uint8_t CRC16DAT; + uint8_t RESERVED5; + uint16_t RESERVED6; + __IO uint16_t CRC16D; + uint16_t RESERVED7; + __IO uint8_t LRC; + uint8_t RESERVED8; + uint16_t RESERVED9; +} CRC_Module; + + + +/*** External Interrupt/Event Controller ***/ + +typedef struct +{ + __IO uint32_t IMASK; + __IO uint32_t EMASK; + __IO uint32_t RT_CFG; + __IO uint32_t FT_CFG; + __IO uint32_t SWIE; + __IO uint32_t PEND; +} EXTI_Module; + +/*** FLASH Registers ***/ + +typedef struct +{ + __IO uint32_t AC; + __IO uint32_t KEY; + __IO uint32_t OPTKEY; + __IO uint32_t STS; + __IO uint32_t CTRL; + __IO uint32_t ADD; + __IO uint32_t RESERVED0; + __IO uint32_t OB; + __IO uint32_t USER; + __IO uint32_t VTOR; +} FLASH_Module; + +/*** Option Bytes Registers ***/ + +typedef struct +{ + __IO uint32_t USER_RDP; + __IO uint32_t Data1_Data0; + __IO uint32_t USER3_USER2; + __IO uint32_t USER4_RDP2; +} OB_Module; + +/** General Purpose I/O **/ + +typedef struct +{ + __IO uint32_t PMODE; + __IO uint32_t POTYPE; + __IO uint32_t SR; + __IO uint32_t PUPD; + __IO uint32_t PID; + __IO uint32_t POD; + __IO uint32_t PBSC; + __IO uint32_t PLOCK; + __IO uint32_t AFL; + __IO uint32_t AFH; + __IO uint32_t PBC; + __IO uint32_t DS; +} GPIO_Module; + +/** Alternate Function I/O **/ + +typedef struct +{ + __IO uint32_t CFG; +} AFIO_Module; + + +/*** Inter Integrated Circuit Interface ***/ + +typedef struct +{ + __IO uint16_t CTRL1; + uint16_t RESERVED0; + __IO uint16_t CTRL2; + uint16_t RESERVED1; + __IO uint16_t OADDR1; + uint16_t RESERVED2; + __IO uint16_t OADDR2; + uint16_t RESERVED3; + __IO uint16_t DAT; + uint16_t RESERVED4; + __IO uint16_t STS1; + uint16_t RESERVED5; + __IO uint16_t STS2; + uint16_t RESERVED6; + __IO uint16_t CLKCTRL; + uint16_t RESERVED7; + __IO uint16_t TMRISE; + uint16_t RESERVED8; + __IO uint16_t GFLTRCTRL; + uint16_t RESERVED9; + __IO uint16_t BYTENUM; +} I2C_Module; + + +/*** Beeper ***/ + +typedef struct +{ + __IO uint32_t CTRL; +} BEEPER_Module; + + +/*** Independent watchdog ***/ + +typedef struct +{ + __IO uint32_t KEY; + __IO uint32_t PREDIV; + __IO uint32_t RELV; + __IO uint32_t STS; + __IO uint32_t FREEZE; +} IWDG_Module; + +/*** Power Control ***/ +typedef struct +{ + __IO uint32_t CTRL; + __IO uint32_t CTRLSTS; + __IO uint32_t CTRL2; + uint32_t RESERVED0; + uint32_t RESERVED1; + __IO uint32_t CTRL3; + uint32_t RESERVED2; + uint32_t RESERVED3; + __IO uint32_t CTRL4; + __IO uint32_t CTRL5; + __IO uint32_t CTRL6; + uint32_t RESERVED4; + __IO uint32_t DBG_CTRL; +} PWR_Module; + +/*** Reset and Clock Control ***/ + +typedef struct +{ + __IO uint32_t HSICTRL; + __IO uint32_t CFG; + __IO uint32_t Reserve0; + __IO uint32_t PRST; + __IO uint32_t AHBPCLKEN; + __IO uint32_t APBPCLKEN; + __IO uint32_t LSICTRL; + __IO uint32_t CTRLSTS; + __IO uint32_t CFG2; + __IO uint32_t EMCCTRL; +} RCC_Module; + + +/*** compare ***/ + +typedef struct +{ + __IO uint32_t INTEN; + __IO uint32_t INTSTS; + uint32_t RESERVED0; + __IO uint32_t LOCK; + __IO uint32_t CTRL; + __IO uint32_t FILC; + __IO uint32_t FILP; +}COMP_Module; + + + +/*** Serial Peripheral Interface ***/ + +typedef struct +{ + __IO uint16_t CTRL1; + uint16_t RESERVED0; + __IO uint16_t CTRL2; + uint16_t RESERVED1; + __IO uint16_t STS; + uint16_t RESERVED2; + __IO uint16_t DAT; + uint16_t RESERVED3; +} SPI_Module; + + +/*** TIM ***/ + +typedef struct +{ + __IO uint32_t CTRL1; + __IO uint32_t CTRL2; + __IO uint16_t SMCTRL; + uint16_t RESERVED1; + __IO uint16_t DINTEN; + uint16_t RESERVED2; + __IO uint32_t STS; + __IO uint16_t EVTGEN; + uint16_t RESERVED3; + __IO uint16_t CCMOD1; + uint16_t RESERVED4; + __IO uint16_t CCMOD2; + uint16_t RESERVED5; + __IO uint32_t CCEN; + __IO uint16_t CNT; + uint16_t RESERVED6; + __IO uint16_t PSC; + uint16_t RESERVED7; + __IO uint16_t AR; + uint16_t RESERVED8; + __IO uint16_t REPCNT; + uint16_t RESERVED9; + __IO uint16_t CCDAT1; + uint16_t RESERVED10; + __IO uint16_t CCDAT2; + uint16_t RESERVED11; + __IO uint16_t CCDAT3; + uint16_t RESERVED12; + __IO uint16_t CCDAT4; + uint16_t RESERVED13; + __IO uint16_t BKDT; + uint16_t RESERVED14; + uint32_t RESERVED15; + uint32_t RESERVED16; + uint32_t RESERVED17; + __IO uint16_t CCMOD3; + uint16_t RESERVED18; + __IO uint16_t CCDAT5; + uint16_t RESERVED19; + uint32_t RESERVED20; +} TIM_Module; + + + +/*** Universal Asynchronous Receiver Transmitter ***/ +typedef struct +{ + __IO uint16_t STS; + uint16_t RESERVED0; + __IO uint16_t DAT; + uint16_t RESERVED1; + __IO uint16_t BRCF; + uint16_t RESERVED2; + __IO uint16_t CTRL1; + uint16_t RESERVED3; + __IO uint16_t CTRL2; + uint16_t RESERVED4; + __IO uint16_t CTRL3; + uint16_t RESERVED5; +} UART_Module; + + + + +/*** Peripheral memory map ***/ + +#define FLASH_BASE ((uint32_t)0x08000000) /* FLASH base address in the alias region */ +#define SRAM_BASE ((uint32_t)0x20000000) /* SRAM base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /* Peripheral base address in the alias region */ + +#define UCID_BASE ((uint32_t)0x1FFFF4D0) /* UCID Address : 0x1FFF_F7C0 */ +#define UCID_LENGTH ((uint32_t)0x10) /* UCID Length : 16 Bytes */ +#define UID_BASE ((uint32_t)0x1FFFF4FC) /* UID Address : 0x1FFF_F7F0 */ +#define UID_LENGTH ((uint32_t)0x0C) /* UID Length : 12 Bytes */ +#define DBGMCU_ID_BASE ((uint32_t)0x1FFFF508) /* DBGMCU_ID Address :0x1FFF_F508 */ +#define DBGMCU_ID_LENGTH ((uint8_t)0x04) /* DBGMCU_ID Length : 4 Bytes */ + + +/** Peripheral memory map **/ +#define APBPERIPH_BASE (PERIPH_BASE) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) + +/** APB1 **/ +#define TIM3_BASE (APBPERIPH_BASE + 0x0400) +#define TIM1_BASE (APBPERIPH_BASE + 0x0C00) +#define TIM6_BASE (APBPERIPH_BASE + 0x1000) +#define AFIO_BASE (APBPERIPH_BASE + 0x1400) +#define GPIOA_BASE (APBPERIPH_BASE + 0x1C00) +#define GPIOB_BASE (APBPERIPH_BASE + 0x2000) +#define COMP_BASE (APBPERIPH_BASE + 0x2400) +#define IWDG_BASE (APBPERIPH_BASE + 0x2C00) +#define EXTI_BASE (APBPERIPH_BASE + 0x3400) +#define BEEPER_BASE (APBPERIPH_BASE + 0x3800) +#define UART1_BASE (APBPERIPH_BASE + 0x4400) +#define UART2_BASE (APBPERIPH_BASE + 0x4800) +#define I2C_BASE (APBPERIPH_BASE + 0x5400) +#define SPI_BASE (APBPERIPH_BASE + 0x5800) +#define PWR_BASE (APBPERIPH_BASE + 0x7000) + + +/** AHB **/ +#define ADC_BASE (AHBPERIPH_BASE + 0x0800) +#define RCC_BASE (AHBPERIPH_BASE + 0x1000) +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /* Flash registers base address */ +#define OB_BASE ((uint32_t)0x1FFFF600) /* Flash Option Bytes base address */ +#define CRC_BASE (AHBPERIPH_BASE + 0x3000) + + +/** Peripheral_declaration **/ + +#define BEEPER ((BEEPER_Module *) BEEPER_BASE) +#define TIM1 ((TIM_Module *) TIM1_BASE) +#define TIM3 ((TIM_Module *) TIM3_BASE) +#define TIM6 ((TIM_Module *) TIM6_BASE) +#define COMP ((COMP_Module *) COMP_BASE) +#define IWDG ((IWDG_Module *) IWDG_BASE) +#define SPI ((SPI_Module *) SPI_BASE) +#define UART1 ((UART_Module *) UART1_BASE) +#define UART2 ((UART_Module *) UART2_BASE) +#define I2C ((I2C_Module *) I2C_BASE) +#define PWR ((PWR_Module *) PWR_BASE) + +#define AFIO ((AFIO_Module *) AFIO_BASE) +#define EXTI ((EXTI_Module *) EXTI_BASE) +#define GPIOA ((GPIO_Module *) GPIOA_BASE) +#define GPIOB ((GPIO_Module *) GPIOB_BASE) +#define ADC ((ADC_Module *) ADC_BASE) +#define RCC ((RCC_Module *) RCC_BASE) +#define FLASH ((FLASH_Module *) FLASH_R_BASE) +#define OBT ((OB_Module *) OB_BASE) +#define CRC ((CRC_Module *) CRC_BASE) + + + +/******************************************************************************/ +/* Peripheral Registers_Bits_Definition */ +/******************************************************************************/ + +/*** CRC calculation unit ***/ +/** Bit definition for CRC_CRC16CTRL register **/ +#define CRC16_CTRL_ENDHL ((uint8_t)0x02) +#define CRC16_CTRL_LITTLE ((uint8_t)0x02) +#define CRC16_CTRL_BIG ((uint8_t)0xFD) + +#define CRC16_CTRL_CLR ((uint8_t)0x04) +#define CRC16_CTRL_RESET ((uint8_t)0x04) +#define CRC16_CTRL_NO_RESET ((uint8_t)0xFB) + +/** Bit definition for CRC_CRC16DAT register **/ +#define CRC16_CRC16DAT ((uint8_t)0xFF) + +/** Bit definition for CRC_CRC16D register **/ +#define CRC16_CRC16D ((uint16_t)0xFFFF) + +/** Bit definition for CRC_LRC register **/ +#define CRC_LRC_LRCDAT ((uint8_t)0xFF) + + +/*** Power Control ***/ +/** Bit definition for PWR_CTRL register **/ +#define PWR_CTRL_IWDGRSTEN ((uint16_t)0x0001) /* IWDG reset request causes a system reset */ +#define PWR_CTRL_PDSTP ((uint16_t)0x0002) /* 0: CPU output DEEPSLEEP is 1, and the chip enters STOP mode,*/ + /*1: CPU output DEEPSLEEP is 1, and the chip enters PD mode */ +#define PWR_CTRL_CLRWKUPF ((uint16_t)0x0004) /* Clear Wakeup Flag */ +#define PWR_CTRL_CLRDBGPDF ((uint16_t)0x0008) /* Clear DBGPDF flag */ +#define PWR_CTRL_PVDEN ((uint16_t)0x0010) /* PVD Enables control */ + +#define PWR_CTRL_PLS ((uint16_t)0x01E0) /* PLS[3:0] bits (PVD Level Selection) */ +#define PWR_CTRL_PLS_0 ((uint16_t)0x0020) /* Bit 0 */ +#define PWR_CTRL_PLS_1 ((uint16_t)0x0040) /* Bit 1 */ +#define PWR_CTRL_PLS_2 ((uint16_t)0x0080) /* Bit 2 */ +#define PWR_CTRL_PLS_3 ((uint16_t)0x0100) /* Bit 3 */ + +#define PWR_CTRL_PDRS ((uint16_t)0x0600) /* PDRS[2:0] bits (VDDD PDR trigger level in STOP mode) */ +#define PWR_CTRL_PDRS_0 ((uint16_t)0x0200) /* Bit 0 */ +#define PWR_CTRL_PDRS_1 ((uint16_t)0x0400) /* Bit 1 */ + +#define PWR_CTRL_NRSTPOL ((uint16_t)0x0800) /* NRST polarity selection */ + +#define PWR_CTRL_PVDCNT ((uint32_t)0x01FE0000) /* PVD count */ +#define PWR_CTRL_PVDFILEN ((uint32_t)0x02000000) /* Enable PVD filter */ +#define PWR_CTRL_PVDITEN ((uint32_t)0x04000000) /* Enable PVD interrupt */ + +/** Bit definition for PWR_CTRLSTS register **/ +#define PWR_CTRLSTS_WKUPF ((uint16_t)0x0001) /* Wakeup Flag */ +#define PWR_CTRLSTS_DBGPDF ((uint16_t)0x0002) /* DBGPDF Flag */ +#define PWR_CTRLSTS_PVDO ((uint16_t)0x0004) /* PVD Output */ +#define PWR_CTRLSTS_WKUP0EN ((uint16_t)0x0100) /* Enable WKUP pin PA1 */ +#define PWR_CTRLSTS_WKUP1EN ((uint16_t)0x0200) /* Enable WKUP pin PA2 */ +#define PWR_CTRLSTS_WKUPPOL ((uint16_t)0x0400) /* Polarity of WKUP pin PA1/PA2,0:Falling edge,1:Rising edge */ + +/** Bit definition for PWR_CTRL2 register **/ +#define PWR_CTRL2_LVRCNT ((uint16_t)0x00FF) /* LVR filter control counts */ +#define PWR_CTRL2_LVRFILEN ((uint16_t)0x0100) /* Enable LVR filter */ +#define PWR_CTRL2_LVRRSTEN ((uint16_t)0x0200) /* Enable LVR reset */ +#define PWR_CTRL2_LVREN ((uint16_t)0x0400) /* Enable LVR */ + +#define PWR_CTRL2_LVRLS ((uint16_t)0x7800) /* LVRLS[3:0] bits (LVR Level Selection) */ +#define PWR_CTRL2_LVRLS_0 ((uint16_t)0x0800) /* Bit 0 */ +#define PWR_CTRL2_LVRLS_1 ((uint16_t)0x1000) /* Bit 1 */ +#define PWR_CTRL2_LVRLS_2 ((uint16_t)0x2000) /* Bit 2 */ +#define PWR_CTRL2_LVRLS_3 ((uint16_t)0x4000) /* Bit 3 */ + +#define PWR_CTRL2_LVRO ((uint16_t)0x8000) /* LVR Output */ + +#define PWR_CTRL2_LVRKEY ((uint32_t)0xFF000000) /* LVR key */ + +/** Bit definition for PWR_CTRL3 register **/ +#define PWR_CTRL3_MRPWR ((uint16_t)0x0001) /* MR is controlled by PWR */ +#define PWR_CTRL3_LPMRPWR ((uint16_t)0x0002) /* MR low power is controlled by PWR */ +#define PWR_CTRL3_SLPFLHPWR ((uint16_t)0x0004) /* Flash sleep is controlled by PWR */ +#define PWR_CTRL3_PDFLHPWR ((uint16_t)0x0008) /* Flash power down is controlled by PWR */ +#define PWR_CTRL3_HSIPWR ((uint16_t)0x0020) /* HSI is controlled by PWR */ +#define PWR_CTRL3_HSISEL ((uint16_t)0x0040) /* HSI frequency selection, 0: 48M, 1: 40M */ +#define PWR_CTRL3_LSIEN ((uint16_t)0x0080) /* Control PWR Enables the LSI */ +#define PWR_CTRL3_PDRSEL ((uint16_t)0x0200) /* VDDD PDR select signal is controlled by PWR */ +#define PWR_CTRL3_LSISTPCNT ((uint16_t)0x1C00) /* LSI stop count */ + +/** Bit definition for PWR_CTRL4 register **/ +#define PWR_CTRL4_FLHWKUP ((uint16_t)0x0001) /* Flash quick Wake up */ +#define PWR_CTRL4_STBFLH ((uint16_t)0x0002) /* Flash Deep standby mode */ +#define PWR_CTRL4_RUNF ((uint16_t)0x0004) /* System in RUN mode */ + +/** Bit definition for PWR_CTRL5 register **/ +#define PWR_CTRL5_STPMRSEL ((uint16_t)0x000C) /* STPMRSEL[1:0] bits (After enter STOP mode, VDDD output voltage select) */ +#define PWR_CTRL5_STPMRSEL_0 ((uint16_t)0x0004) /* Bit 0 */ +#define PWR_CTRL5_STPMRSEL_1 ((uint16_t)0x0008) /* Bit 1 */ + +/** Bit definition for PWR_CTRL6 register **/ +#define PWR_CTRL6_STPMREN ((uint16_t)0x000C) /* STPMREN[1:0] bits (After enter STOP mode, Enable VDDD output voltage select) */ +#define PWR_CTRL6_STPMREN_0 ((uint16_t)0x0004) /* Bit 0 */ +#define PWR_CTRL6_STPMREN_1 ((uint16_t)0x0008) /* Bit 1 */ + +/** Bit definition for DBG_CTRL register **/ +#define DBG_CTRL_STOP ((uint16_t)0x0002) /* Debug STOP mode control */ +#define DBG_CTRL_PD ((uint16_t)0x0004) /* Debug PD mode control */ +#define DBG_CTRL_IWDGSTP ((uint16_t)0x0020) /* Debug LWDG mode control */ +#define DBG_CTRL_TIM1STP ((uint16_t)0x0040) /* Debug TIM1 mode control */ +#define DBG_CTRL_TIM3STP ((uint16_t)0x0080) /* Debug TIM3 mode control */ +#define DBG_CTRL_TIM6STP ((uint16_t)0x0100) /* Debug TIM6 mode control */ + + +/*** Reset and Clock Control ***/ + +/** Bit definition for RCC_HSICTRL register **/ +#define RCC_HSICTRL_HSI40MRDF ((uint32_t)0x00000001) /* Internal High Speed clock 40M ready flag */ +#define RCC_HSICTRL_HSI48MRDF ((uint32_t)0x00000002) /* Internal High Speed clock 48M ready flag */ +#define RCC_HSICTRL_HSITRIM ((uint32_t)0x000000F0) /* Internal High Speed clock trimming */ + +/** Bit definition for RCC_CFG register **/ + +/** AHBPRES configuration */ +#define RCC_CFG_AHBPRES ((uint32_t)0x000000F0) /* AHBPRES[3:0] bits (AHB prescaler) */ +#define RCC_CFG_AHBPRES_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define RCC_CFG_AHBPRES_1 ((uint32_t)0x00000020) /* Bit 1 */ +#define RCC_CFG_AHBPRES_2 ((uint32_t)0x00000040) /* Bit 2 */ +#define RCC_CFG_AHBPRES_3 ((uint32_t)0x00000080) /* Bit 3 */ + +#define RCC_CFG_AHBPRES_DIV1 ((uint32_t)0x00000000) /* SYSCLK not divided */ +#define RCC_CFG_AHBPRES_DIV2 ((uint32_t)0x00000080) /* SYSCLK divided by 2 */ +#define RCC_CFG_AHBPRES_DIV4 ((uint32_t)0x00000090) /* SYSCLK divided by 4 */ +#define RCC_CFG_AHBPRES_DIV8 ((uint32_t)0x000000A0) /* SYSCLK divided by 8 */ +#define RCC_CFG_AHBPRES_DIV12 ((uint32_t)0x000000B0) /* SYSCLK divided by 12 */ +#define RCC_CFG_AHBPRES_DIV16 ((uint32_t)0x000000C0) /* SYSCLK divided by 16 */ +#define RCC_CFG_AHBPRES_DIV24 ((uint32_t)0x000000D0) /* SYSCLK divided by 24 */ + +/** PPRE configuration **/ +/** APBPRES configuration */ +#define RCC_CFG_APBPRES ((uint32_t)0x00000700) /* APB1PRES[2:0] bits (APB1 prescaler) */ +#define RCC_CFG_APBPRES_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define RCC_CFG_APBPRES_1 ((uint32_t)0x00000200) /* Bit 1 */ +#define RCC_CFG_APBPRES_2 ((uint32_t)0x00000400) /* Bit 2 */ + +#define RCC_CFG_APBPRES_DIV1 ((uint32_t)0x00000000) /* HCLK not divided */ +#define RCC_CFG_APBPRES_DIV2 ((uint32_t)0x00000400) /* HCLK divided by 2 */ +#define RCC_CFG_APBPRES_DIV4 ((uint32_t)0x00000500) /* HCLK divided by 4 */ +#define RCC_CFG_APBPRES_DIV8 ((uint32_t)0x00000600) /* HCLK divided by 8 */ +#define RCC_CFG_APBPRES_DIV16 ((uint32_t)0x00000700) /* HCLK divided by 16 */ + +/** SYSPRES configuration **/ +#define RCC_CFG_SYSPRES ((uint32_t)0x00003000) /* PRE1[2:0] bits (SYSCLk prescaler) */ +#define RCC_CFG_SYSPRES_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define RCC_CFG_SYSPRES_1 ((uint32_t)0x00002000) /* Bit 1 */ + +#define RCC_CFG_SYSPRES_DIV1 ((uint32_t)0x00000000) /* HSICLK not divided */ +#define RCC_CFG_SYSPRES_DIV2 ((uint32_t)0x00001000) /* HSICLK divided by 2 */ +#define RCC_CFG_SYSPRES_DIV5 ((uint32_t)0x00003000) /* HSICLK divided by 5 */ +#define RCC_CFG_SYSPRES_DIV6 ((uint32_t)0x00003000) /* HSICLK divided by 6 */ + + +/** MCO configuration **/ +#define RCC_CFG_MCO ((uint32_t)0x06000000) /* MCO[1:0] bits (Microcontroller Clock Output) */ +#define RCC_CFG_MCO_0 ((uint32_t)0x02000000) /* Bit 0 */ +#define RCC_CFG_MCO_1 ((uint32_t)0x04000000) /* Bit 1 */ + +#define RCC_CFG_MCO_NOCLK ((uint32_t)0x00000000) /* No clock */ +#define RCC_CFG_MCO_LSI ((uint32_t)0x02000000) /* LSI clock selected as MCO source */ +#define RCC_CFG_MCO_HSI ((uint32_t)0x04000000) /* HSI clock selected as MCO source */ + +/** MCOPRE configuration **/ +#define RCC_CFG_MCOPRES ((uint32_t)0xF0000000)/* MCOPRE[3:0] bits ( Microcontroller Clock Output prescaler.) */ +#define RCC_CFG_MCOPRES_0 ((uint32_t)0x10000000) /* Bit 0 */ +#define RCC_CFG_MCOPRES_1 ((uint32_t)0x20000000) /* Bit 1 */ +#define RCC_CFG_MCOPRES_2 ((uint32_t)0x40000000) /* Bit 2 */ +#define RCC_CFG_MCOPRES_3 ((uint32_t)0x80000000) /* Bit 3 */ + +#define RCC_CFG_MCOPRES_DIV1 ((uint32_t)0x00000000) /* LSI clock is divided by 1,HSI clock is divided by 2 */ +#define RCC_CFG_MCOPRES_DIV2 ((uint32_t)0x10000000) /* LSI/HSI clock is divided by 2 */ +#define RCC_CFG_MCOPRES_DIV3 ((uint32_t)0x20000000) /* LSI/HSI clock is divided by 3 */ +#define RCC_CFG_MCOPRES_DIV4 ((uint32_t)0x30000000) /* LSI/HSI clock is divided by 4 */ +#define RCC_CFG_MCOPRES_DIV5 ((uint32_t)0x40000000) /* LSI/HSI clock is divided by 5 */ +#define RCC_CFG_MCOPRES_DIV6 ((uint32_t)0x50000000) /* LSI/HSI clock is divided by 6 */ +#define RCC_CFG_MCOPRES_DIV7 ((uint32_t)0x60000000) /* LSI/HSI clock is divided by 7 */ +#define RCC_CFG_MCOPRES_DIV8 ((uint32_t)0x70000000) /* LSI/HSI clock is divided by 8 */ +#define RCC_CFG_MCOPRES_DIV9 ((uint32_t)0x80000000) /* LSI/HSI clock is divided by 9 */ +#define RCC_CFG_MCOPRES_DIV10 ((uint32_t)0x90000000) /* LSI/HSI clock is divided by 10 */ +#define RCC_CFG_MCOPRES_DIV11 ((uint32_t)0xA0000000) /* LSI/HSI clock is divided by 11 */ +#define RCC_CFG_MCOPRES_DIV12 ((uint32_t)0xB0000000) /* LSI/HSI clock is divided by 12 */ +#define RCC_CFG_MCOPRES_DIV13 ((uint32_t)0xC0000000) /* LSI/HSI clock is divided by 13 */ +#define RCC_CFG_MCOPRES_DIV14 ((uint32_t)0xD0000000) /* LSI/HSI clock is divided by 14 */ +#define RCC_CFG_MCOPRES_DIV15 ((uint32_t)0xE0000000) /* LSI/HSI clock is divided by 15 */ +#define RCC_CFG_MCOPRES_DIV32 ((uint32_t)0xF0000000) /* LSI/HSI clock is divided by 32 */ + +/** Bit definition for RCC_PRST register **/ +#define RCC_PRST_AFIORST ((uint32_t)0x00000001) /* Alternate Function I/O reset */ +#define RCC_PRST_BEEPRST ((uint32_t)0x00000002) /* Beeper reset */ +#define RCC_PRST_GPIOARST ((uint32_t)0x00000004) /* GPIOA reset */ +#define RCC_PRST_GPIOBRST ((uint32_t)0x00000008) /* GPIOB reset */ +#define RCC_PRST_UART1RST ((uint32_t)0x00000010) /* UART 1 reset */ +#define RCC_PRST_UART2RST ((uint32_t)0x00000020) /* UART 2 reset */ +#define RCC_PRST_I2CRST ((uint32_t)0x00000040) /* I2C reset */ +#define RCC_PRST_PWRRST ((uint32_t)0x00000080) /* Power interface reset */ +#define RCC_PRST_ADCRST ((uint32_t)0x00000100) /* ADC reset */ +#define RCC_PRST_SPIRST ((uint32_t)0x00000400) /* SPI reset */ +#define RCC_PRST_TIM1RST ((uint32_t)0x00000800) /* Timer 1 reset */ +#define RCC_PRST_TIM3RST ((uint32_t)0x00001000) /* Timer 3 reset */ +#define RCC_PRST_TIM6RST ((uint32_t)0x00002000) /* Timer 6 reset */ +#define RCC_PRST_COMPRST ((uint32_t)0x00004000) /* COMP reset */ + + +/** Bit definition for RCC_AHBPCLKEN register **/ +#define RCC_AHBPCLKEN_CRCEN ((uint32_t)0x00000040) /* CRC clock enable */ +#define RCC_AHBPCLKEN_ADCEN ((uint32_t)0x00001000) /* ADC clock enable */ + +/** Bit definition for RCC_APBPCLKEN register **/ +#define RCC_APBPCLKEN_AFIOEN ((uint32_t)0x00000001) /* Alternate Function I/O enable */ +#define RCC_APBPCLKEN_BEEPEREN ((uint32_t)0x00000002) /* Beeper enable */ +#define RCC_APBPCLKEN_IOPAEN ((uint32_t)0x00000004) /* I/O port A clock enable */ +#define RCC_APBPCLKEN_IOPBEN ((uint32_t)0x00000008) /* I/O port B clock enable */ +#define RCC_APBPCLKEN_COMPEN ((uint32_t)0x00000010) /* COMP enable */ +#define RCC_APBPCLKEN_COMPFILTEN ((uint32_t)0x00000020) /* COMPFILT enable */ +#define RCC_APBPCLKEN_UART1EN ((uint32_t)0x00000040) /* UART 1 enable */ +#define RCC_APBPCLKEN_UART2EN ((uint32_t)0x00000080) /* UART 2 enable */ +#define RCC_APBPCLKEN_I2CEN ((uint32_t)0x00000100) /* I2C enable */ +#define RCC_APBPCLKEN_PWREN ((uint32_t)0x00000200) /* Power enable */ +#define RCC_APBPCLKEN_SPIEN ((uint32_t)0x00000400) /* SPI enable */ +#define RCC_APBPCLKEN_TIM1EN ((uint32_t)0x00000800) /* Timer 1 enable */ +#define RCC_APBPCLKEN_TIM3EN ((uint32_t)0x00001000) /* Timer 3 enable */ +#define RCC_APBPCLKEN_TIM6EN ((uint32_t)0x00002000) /* Timer 6 enable */ +#define RCC_APBPCLKEN_IWDGEN ((uint32_t)0x00004000) /* Independent Watchdog enable */ + +/** Bit definition for RCC_LSICTRL register **/ +#define RCC_LSICTRL_LSIRDF ((uint32_t)0x00000002) /* Internal Low Speed clock ready flag */ +#define RCC_LSICTRL_LSITRIM ((uint32_t)0x0000007C) /* Internal Low Speed clock trimming */ +#define RCC_LSICTRL_LSIDETEN ((uint32_t)0x00000080) /* Internal Low Speed clock detect enable */ +#define RCC_LSICTRL_LSIFREQ ((uint32_t)0x00FFFF00) /* Internal Low Speed clock freq cnt */ +#define RCC_LSICTRL_LSIDETFF ((uint32_t)0x01000000) /* Internal Low Speed clock detect finish flag */ + +/** Bit definition for RCC_CTRLSTS register **/ +#define RCC_CTRLSTS_RMRSTF ((uint32_t)0x00000001) /* Remove reset flag */ +#define RCC_CTRLSTS_PINRSTF ((uint32_t)0x00000008) /* PIN reset flag */ +#define RCC_CTRLSTS_PORRSTF ((uint32_t)0x00000010) /* POR/PDR reset flag */ +#define RCC_CTRLSTS_SFTRSTF ((uint32_t)0x00000020) /* Software Reset flag */ +#define RCC_CTRLSTS_IWDGRSTF ((uint32_t)0x00000040) /* Independent Watchdog reset flag */ +#define RCC_CTRLSTS_LVRRSTF ((uint32_t)0x00000080) /* LVR reset flag */ +#define RCC_CTRLSTS_LPWRRSTF ((uint32_t)0x00000100) /* Low-Power reset flag */ +#define RCC_CTRLSTS_EMCRSTF ((uint32_t)0x00000800) /* EMC reset flag */ + +/** Bit definition for RCC_CFG2 register **/ +/** ADCPRES configuration **/ +#define RCC_CFG2_ADCPRES ((uint32_t)0x0000000F) /* ADCHSIPRE[3:0] bits */ +#define RCC_CFG2_ADCPRES_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define RCC_CFG2_ADCPRES_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define RCC_CFG2_ADCPRES_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define RCC_CFG2_ADCPRES_3 ((uint32_t)0x00000008) /* Bit 3 */ + +#define RCC_CFG2_ADCPRES_DIV1 ((uint32_t)0x00000000) /* HCLK clock divided by 1 */ +#define RCC_CFG2_ADCPRES_DIV2 ((uint32_t)0x00000001) /* HCLK clock divided by 2 */ +#define RCC_CFG2_ADCPRES_DIV3 ((uint32_t)0x00000002) /* HCLK clock divided by 3 */ +#define RCC_CFG2_ADCPRES_DIV4 ((uint32_t)0x00000003) /* HCLK clock divided by 4 */ +#define RCC_CFG2_ADCPRES_DIV6 ((uint32_t)0x00000004) /* HCLK clock divided by 6 */ +#define RCC_CFG2_ADCPRES_DIV8 ((uint32_t)0x00000005) /* HCLK clock divided by 8 */ +#define RCC_CFG2_ADCPRES_DIV10 ((uint32_t)0x00000006) /* HCLK clock divided by 10 */ +#define RCC_CFG2_ADCPRES_DIV12 ((uint32_t)0x00000007) /* HCLK clock divided by 12 */ +#define RCC_CFG2_ADCPRES_DIV24 ((uint32_t)0x00000008 /* HCLK clock divided by 24 */ +#define RCC_CFG2_ADCPRES_DIV32 ((uint32_t)0x00000009) /* HCLK clock divided by 32 */ +#define RCC_CFG2_ADCPRES_OTHERS ((uint32_t)0x0000000A) /* HCLK clock divided by 32 */ + +/** ADC1MSEL configuration **/ +#define RCC_CFG2_ADCCLK_SEL ((uint32_t)0x00000010) /* ADC1M clock source select */ +#define RCC_CFG2_ADCCLK_SEL_HSI ((uint32_t)0x00000000) /* HSI clock selected as ADC1M input clock */ +#define RCC_CFG2_ADCCLK_SEL_IOM ((uint32_t)0x00000010) /* IOM test clock selected as ADC1M input clock */ + +/** ADC1MPRES configuration **/ +#define RCC_CFG2_ADC1MPRES ((uint32_t)0x00000C00) /* ADC1MPRE[4:0] bits */ +#define RCC_CFG2_ADC1MPRES_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define RCC_CFG2_ADC1MPRES_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define RCC_CFG2_ADC1MPRES_DIV6 ((uint32_t)0x00000000) /* ADC1M source clock is divided by 6 */ +#define RCC_CFG2_ADC1MPRES_DIV12 ((uint32_t)0x00000400) /* ADC1M source clock is divided by 12 */ +#define RCC_CFG2_ADC1MPRES_DIV24 ((uint32_t)0x00000800) /* ADC1M source clock is divided by 24 */ +#define RCC_CFG2_ADC1MPRES_DIV40 ((uint32_t)0x00000C00) /* ADC1M source clock is divided by 40 */ +#define RCC_CFG2_ADC1MPRES_DIV48 ((uint32_t)0x00000C00) /* ADC1M source clock is divided by 48 */ + +/** TIM6CLKSEL configuration **/ +#define RCC_CFG2_TIM6CLKSEL ((uint32_t)0x40000000) /* Timer6 clock source select */ +#define RCC_CFG2_TIM6CLKSEL_PCLK ((uint32_t)0x00000000) /* Timer6 clock selected as APB input clock */ +#define RCC_CFG2_TIM6CLKSEL_LSI ((uint32_t)0x40000000) /* Timer6 clock selected as LSI clock */ + +/** TIM1CLKSEL configuration **/ +#define RCC_CFG2_TIM1CLKSEL ((uint32_t)0x80000000) /* Timer1 clock source select */ +#define RCC_CFG2_TIM1CLKSEL_PCLK ((uint32_t)0x00000000) /* Timer1 clock selected as APB input clock */ +#define RCC_CFG2_TIM1CLKSEL_SYSCLK ((uint32_t)0x80000000) /* Timer1 clock selected as System clock */ + +/** Bit definition for RCC_EMCCTRL register **/ +#define RCC_EMCCTRL_EMCDETEN ((uint32_t)0x00000001) /* EMC Clamp reset enable */ +#define RCC_EMCCTRL_EMCRSTEN ((uint32_t)0x00001000) /* EMC Clamp detect enable */ + +/*** General Purpose and Alternate Function I/O ***/ + +/** Bit definition for GPIO_PMODE register **/ +#define GPIO_PMODE0_Pos (0) +#define GPIO_PMODE0_Msk (0x3 << GPIO_PMODE0_Pos) /* 0x00000003 */ +#define GPIO_PMODE0 GPIO_PMODE0_Msk /* 0x00000003 */ +#define GPIO_PMODE0_0 (0x0 << GPIO_PMODE0_Pos) /* 0x00000000 */ +#define GPIO_PMODE0_1 (0x1 << GPIO_PMODE0_Pos) /* 0x00000001 */ +#define GPIO_PMODE0_2 (0x2 << GPIO_PMODE0_Pos) /* 0x00000002 */ +#define GPIO_PMODE0_3 (0x3 << GPIO_PMODE0_Pos) /* 0x00000003 */ + +#define GPIO_PMODE1_Pos (2) +#define GPIO_PMODE1_Msk (0x3 << GPIO_PMODE1_Pos) /* 0x0000000C */ +#define GPIO_PMODE1 GPIO_PMODE1_Msk /* 0x0000000C */ +#define GPIO_PMODE1_0 (0x0 << GPIO_PMODE1_Pos) /* 0x00000000 */ +#define GPIO_PMODE1_1 (0x1 << GPIO_PMODE1_Pos) /* 0x00000004 */ +#define GPIO_PMODE1_2 (0x2 << GPIO_PMODE1_Pos) /* 0x00000008 */ +#define GPIO_PMODE1_3 (0x3 << GPIO_PMODE1_Pos) /* 0x0000000C */ + +#define GPIO_PMODE2_Pos (4) +#define GPIO_PMODE2_Msk (0x3 << GPIO_PMODE2_Pos) /* 0x00000030 */ +#define GPIO_PMODE2 GPIO_PMODE2_Msk /* 0x00000030 */ +#define GPIO_PMODE2_0 (0x0 << GPIO_PMODE2_Pos) /* 0x00000000 */ +#define GPIO_PMODE2_1 (0x1 << GPIO_PMODE2_Pos) /* 0x00000010 */ +#define GPIO_PMODE2_2 (0x2 << GPIO_PMODE2_Pos) /* 0x00000020 */ +#define GPIO_PMODE2_3 (0x3 << GPIO_PMODE2_Pos) /* 0x00000030 */ + +#define GPIO_PMODE3_Pos (6) +#define GPIO_PMODE3_Msk (0x3 << GPIO_PMODE3_Pos) /* 0x000000C0 */ +#define GPIO_PMODE3 GPIO_PMODE3_Msk /* 0x000000C0 */ +#define GPIO_PMODE3_0 (0x0 << GPIO_PMODE3_Pos) /* 0x00000000 */ +#define GPIO_PMODE3_1 (0x1 << GPIO_PMODE3_Pos) /* 0x00000040 */ +#define GPIO_PMODE3_2 (0x2 << GPIO_PMODE3_Pos) /* 0x00000080 */ +#define GPIO_PMODE3_3 (0x3 << GPIO_PMODE3_Pos) /* 0x000000C0 */ + +#define GPIO_PMODE4_Pos (8) +#define GPIO_PMODE4_Msk (0x3 << GPIO_PMODE4_Pos) /* 0x00000300 */ +#define GPIO_PMODE4 GPIO_PMODE4_Msk /* 0x00000300 */ +#define GPIO_PMODE4_0 (0x0 << GPIO_PMODE4_Pos) /* 0x00000000 */ +#define GPIO_PMODE4_1 (0x1 << GPIO_PMODE4_Pos) /* 0x00000100 */ +#define GPIO_PMODE4_2 (0x2 << GPIO_PMODE4_Pos) /* 0x00000100 */ +#define GPIO_PMODE4_3 (0x3 << GPIO_PMODE4_Pos) /* 0x00000300 */ + +#define GPIO_PMODE5_Pos (10) +#define GPIO_PMODE5_Msk (0x3 << GPIO_PMODE5_Pos) /* 0x00000C00 */ +#define GPIO_PMODE5 GPIO_PMODE5_Msk /* 0x00000C00 */ +#define GPIO_PMODE5_0 (0x0 << GPIO_PMODE5_Pos) /* 0x00000000 */ +#define GPIO_PMODE5_1 (0x1 << GPIO_PMODE5_Pos) /* 0x00000400 */ +#define GPIO_PMODE5_2 (0x2 << GPIO_PMODE5_Pos) /* 0x00000800 */ +#define GPIO_PMODE5_3 (0x3 << GPIO_PMODE5_Pos) /* 0x00000C00 */ + +#define GPIO_PMODE6_Pos (12) +#define GPIO_PMODE6_Msk (0x3 << GPIO_PMODE6_Pos) /* 0x00003000 */ +#define GPIO_PMODE6 GPIO_PMODE6_Msk /* 0x00003000 */ +#define GPIO_PMODE6_0 (0x0 << GPIO_PMODE6_Pos) /* 0x00000000 */ +#define GPIO_PMODE6_1 (0x1 << GPIO_PMODE6_Pos) /* 0x00001000 */ +#define GPIO_PMODE6_2 (0x2 << GPIO_PMODE6_Pos) /* 0x00002000 */ +#define GPIO_PMODE6_3 (0x3 << GPIO_PMODE6_Pos) /* 0x00003000 */ + +#define GPIO_PMODE7_Pos (14) +#define GPIO_PMODE7_Msk (0x3 << GPIO_PMODE7_Pos) /* 0x0000C000 */ +#define GPIO_PMODE7 GPIO_PMODE7_Msk /* 0x0000C000 */ +#define GPIO_PMODE7_0 (0x0 << GPIO_PMODE7_Pos) /* 0x00000000 */ +#define GPIO_PMODE7_1 (0x1 << GPIO_PMODE7_Pos) /* 0x00004000 */ +#define GPIO_PMODE7_2 (0x2 << GPIO_PMODE7_Pos) /* 0x00008000 */ +#define GPIO_PMODE7_3 (0x3 << GPIO_PMODE7_Pos) /* 0x0000C000 */ + +#define GPIO_PMODE8_Pos (16) +#define GPIO_PMODE8_Msk (0x3 << GPIO_PMODE8_Pos) /* 0x00030000 */ +#define GPIO_PMODE8 GPIO_PMODE8_Msk /* 0x00030000 */ +#define GPIO_PMODE8_0 (0x0 << GPIO_PMODE8_Pos) /* 0x00000000 */ +#define GPIO_PMODE8_1 (0x1 << GPIO_PMODE8_Pos) /* 0x00010000 */ +#define GPIO_PMODE8_2 (0x2 << GPIO_PMODE8_Pos) /* 0x00020000 */ +#define GPIO_PMODE8_3 (0x3 << GPIO_PMODE8_Pos) /* 0x00030000 */ + +#define GPIO_PMODE9_Pos (18) +#define GPIO_PMODE9_Msk (0x3 << GPIO_PMODE9_Pos) /* 0x000C0000 */ +#define GPIO_PMODE9 GPIO_PMODE9_Msk /* 0x000C0000 */ +#define GPIO_PMODE9_0 (0x0 << GPIO_PMODE9_Pos) /* 0x00000000 */ +#define GPIO_PMODE9_1 (0x1 << GPIO_PMODE9_Pos) /* 0x00040000 */ +#define GPIO_PMODE9_2 (0x2 << GPIO_PMODE9_Pos) /* 0x00080000 */ +#define GPIO_PMODE9_3 (0x3 << GPIO_PMODE9_Pos) /* 0x000C0000 */ + +#define GPIO_PMODE10_Pos (20) +#define GPIO_PMODE10_Msk (0x3 << GPIO_PMODE10_Pos) /* 0x00300000 */ +#define GPIO_PMODE10 GPIO_PMODE10_Msk /* 0x00300000 */ +#define GPIO_PMODE10_0 (0x0 << GPIO_PMODE10_Pos) /* 0x00000000 */ +#define GPIO_PMODE10_1 (0x1 << GPIO_PMODE10_Pos) /* 0x00100000 */ +#define GPIO_PMODE10_2 (0x2 << GPIO_PMODE10_Pos) /* 0x00200000 */ +#define GPIO_PMODE10_3 (0x3 << GPIO_PMODE10_Pos) /* 0x00300000 */ + +#define GPIO_PMODE11_Pos (22) +#define GPIO_PMODE11_Msk (0x3 << GPIO_PMODE11_Pos) /* 0x00C00000 */ +#define GPIO_PMODE11 GPIO_PMODE11_Msk /* 0x00C00000 */ +#define GPIO_PMODE11_0 (0x0 << GPIO_PMODE11_Pos) /* 0x00000000 */ +#define GPIO_PMODE11_1 (0x1 << GPIO_PMODE11_Pos) /* 0x00400000 */ +#define GPIO_PMODE11_2 (0x2 << GPIO_PMODE11_Pos) /* 0x00800000 */ +#define GPIO_PMODE11_3 (0x3 << GPIO_PMODE11_Pos) /* 0x00C00000 */ + +#define GPIO_PMODE12_Pos (24) +#define GPIO_PMODE12_Msk (0x3 << GPIO_PMODE12_Pos) /* 0x03000000 */ +#define GPIO_PMODE12 GPIO_PMODE12_Msk /* 0x03000000 */ +#define GPIO_PMODE12_0 (0x0 << GPIO_PMODE12_Pos) /* 0x00000000 */ +#define GPIO_PMODE12_1 (0x1 << GPIO_PMODE12_Pos) /* 0x01000000 */ +#define GPIO_PMODE12_2 (0x2 << GPIO_PMODE12_Pos) /* 0x02000000 */ +#define GPIO_PMODE12_3 (0x3 << GPIO_PMODE12_Pos) /* 0x03000000 */ + +#define GPIO_PMODE13_Pos (26) +#define GPIO_PMODE13_Msk (0x3 << GPIO_PMODE13_Pos) /* 0x0C000000 */ +#define GPIO_PMODE13 GPIO_PMODE13_Msk /* 0x0C000000 */ +#define GPIO_PMODE13_0 (0x0 << GPIO_PMODE13_Pos) /* 0x00000000 */ +#define GPIO_PMODE13_1 (0x1 << GPIO_PMODE13_Pos) /* 0x04000000 */ +#define GPIO_PMODE13_2 (0x2 << GPIO_PMODE13_Pos) /* 0x08000000 */ +#define GPIO_PMODE13_3 (0x3 << GPIO_PMODE13_Pos) /* 0x0C000000 */ + +#define GPIO_PMODE14_Pos (28) +#define GPIO_PMODE14_Msk (0x3 << GPIO_PMODE14_Pos) /* 0x30000000 */ +#define GPIO_PMODE14 GPIO_PMODE14_Msk /* 0x30000000 */ +#define GPIO_PMODE14_0 (0x0 << GPIO_PMODE14_Pos) /* 0x00000000 */ +#define GPIO_PMODE14_1 (0x1 << GPIO_PMODE14_Pos) /* 0x10000000 */ +#define GPIO_PMODE14_2 (0x2 << GPIO_PMODE14_Pos) /* 0x20000000 */ +#define GPIO_PMODE14_3 (0x3 << GPIO_PMODE14_Pos) /* 0x30000000 */ + +#define GPIO_PMODE15_Pos (30) +#define GPIO_PMODE15_Msk (0x3 << GPIO_PMODE15_Pos) /* 0xC0000000 */ +#define GPIO_PMODE15 GPIO_PMODE15_Msk /* 0xC0000000 */ +#define GPIO_PMODE15_0 (0x0 << GPIO_PMODE15_Pos) /* 0x00000000 */ +#define GPIO_PMODE15_1 (0x1 << GPIO_PMODE15_Pos) /* 0x40000000 */ +#define GPIO_PMODE15_2 (0x2 << GPIO_PMODE15_Pos) /* 0x80000000 */ +#define GPIO_PMODE15_3 (0x3 << GPIO_PMODE15_Pos) /* 0xC0000000 */ + +/** Bit definition for GPIO_POTYPE register **/ +#define GPIO_POTYPE_POT0 ((uint16_t)0x0001) +#define GPIO_POTYPE_POT1 ((uint16_t)0x0002) +#define GPIO_POTYPE_POT2 ((uint16_t)0x0004) +#define GPIO_POTYPE_POT3 ((uint16_t)0x0008) +#define GPIO_POTYPE_POT4 ((uint16_t)0x0010) +#define GPIO_POTYPE_POT5 ((uint16_t)0x0020) +#define GPIO_POTYPE_POT6 ((uint16_t)0x0040) +#define GPIO_POTYPE_POT7 ((uint16_t)0x0080) +#define GPIO_POTYPE_POT8 ((uint16_t)0x0100) +#define GPIO_POTYPE_POT9 ((uint16_t)0x0200) +#define GPIO_POTYPE_POT10 ((uint16_t)0x0400) +#define GPIO_POTYPE_POT11 ((uint16_t)0x0800) +#define GPIO_POTYPE_POT12 ((uint16_t)0x1000) +#define GPIO_POTYPE_POT13 ((uint16_t)0x2000) +#define GPIO_POTYPE_POT14 ((uint16_t)0x4000) +#define GPIO_POTYPE_POT15 ((uint16_t)0x8000) + +/** Bit definition for GPIO_SR register **/ +#define GPIO_SR_SR0 ((uint16_t)0x0001) /* Port x Slew Rate bit 0 */ +#define GPIO_SR_SR1 ((uint16_t)0x0002) /* Port x Slew Rate bit 1 */ +#define GPIO_SR_SR2 ((uint16_t)0x0004) /* Port x Slew Rate bit 2 */ +#define GPIO_SR_SR3 ((uint16_t)0x0008) /* Port x Slew Rate bit 3 */ +#define GPIO_SR_SR4 ((uint16_t)0x0010) /* Port x Slew Rate bit 4 */ +#define GPIO_SR_SR5 ((uint16_t)0x0020) /* Port x Slew Rate bit 5 */ +#define GPIO_SR_SR6 ((uint16_t)0x0040) /* Port x Slew Rate bit 6 */ +#define GPIO_SR_SR7 ((uint16_t)0x0080) /* Port x Slew Rate bit 7 */ +#define GPIO_SR_SR8 ((uint16_t)0x0100) /* Port x Slew Rate bit 8 */ +#define GPIO_SR_SR9 ((uint16_t)0x0200) /* Port x Slew Rate bit 9 */ +#define GPIO_SR_SR10 ((uint16_t)0x0400) /* Port x Slew Rate bit 10 */ +#define GPIO_SR_SR11 ((uint16_t)0x0800) /* Port x Slew Rate bit 11 */ +#define GPIO_SR_SR12 ((uint16_t)0x1000) /* Port x Slew Rate bit 12 */ +#define GPIO_SR_SR13 ((uint16_t)0x2000) /* Port x Slew Rate bit 13 */ +#define GPIO_SR_SR14 ((uint16_t)0x4000) /* Port x Slew Rate bit 14 */ +#define GPIO_SR_SR15 ((uint16_t)0x8000) /* Port x Slew Rate bit 15 */ + +/** Bit definition for GPIO_PUPD register **/ +#define GPIO_PUPD0_Pos (0) +#define GPIO_PUPD0_Msk (0x3 << GPIO_PUPD0_Pos) /* 0x00000003 */ +#define GPIO_PUPD0 GPIO_PUPD0_Msk /* 0x00000003 */ +#define GPIO_PUPD0_0 (0x0 << GPIO_PUPD0_Pos) /* 0x00000000 */ +#define GPIO_PUPD0_1 (0x1 << GPIO_PUPD0_Pos) /* 0x00000001 */ +#define GPIO_PUPD0_2 (0x2 << GPIO_PUPD0_Pos) /* 0x00000002 */ + +#define GPIO_PUPD1_Pos (2) +#define GPIO_PUPD1_Msk (0x3 << GPIO_PUPD1_Pos) /* 0x0000000C */ +#define GPIO_PUPD1 GPIO_PUPD1_Msk /* 0x0000000C */ +#define GPIO_PUPD1_0 (0x0 << GPIO_PUPD1_Pos) /* 0x00000000 */ +#define GPIO_PUPD1_1 (0x1 << GPIO_PUPD1_Pos) /* 0x00000004 */ +#define GPIO_PUPD1_2 (0x2 << GPIO_PUPD1_Pos) /* 0x00000008 */ + +#define GPIO_PUPD2_Pos (4) +#define GPIO_PUPD2_Msk (0x3 << GPIO_PUPD2_Pos) /* 0x00000030 */ +#define GPIO_PUPD2 GPIO_PUPD2_Msk /* 0x00000030 */ +#define GPIO_PUPD2_0 (0x0 << GPIO_PUPD2_Pos) /* 0x00000000 */ +#define GPIO_PUPD2_1 (0x1 << GPIO_PUPD2_Pos) /* 0x00000010 */ +#define GPIO_PUPD2_2 (0x2 << GPIO_PUPD2_Pos) /* 0x00000020 */ + +#define GPIO_PUPD3_Pos (6) +#define GPIO_PUPD3_Msk (0x3 << GPIO_PUPD3_Pos) /* 0x000000C0 */ +#define GPIO_PUPD3 GPIO_PUPD3_Msk /* 0x000000C0 */ +#define GPIO_PUPD3_0 (0x0 << GPIO_PUPD3_Pos) /* 0x00000000 */ +#define GPIO_PUPD3_1 (0x1 << GPIO_PUPD3_Pos) /* 0x00000040 */ +#define GPIO_PUPD3_2 (0x2 << GPIO_PUPD3_Pos) /* 0x00000080 */ + +#define GPIO_PUPD4_Pos (8) +#define GPIO_PUPD4_Msk (0x3 << GPIO_PUPD4_Pos) /* 0x00000300 */ +#define GPIO_PUPD4 GPIO_PUPD4_Msk /* 0x00000300 */ +#define GPIO_PUPD4_0 (0x0 << GPIO_PUPD4_Pos) /* 0x00000000 */ +#define GPIO_PUPD4_1 (0x1 << GPIO_PUPD4_Pos) /* 0x00000100 */ +#define GPIO_PUPD4_2 (0x2 << GPIO_PUPD4_Pos) /* 0x00000200 */ + +#define GPIO_PUPD5_Pos (10) +#define GPIO_PUPD5_Msk (0x3 << GPIO_PUPD5_Pos) /* 0x00000C00 */ +#define GPIO_PUPD5 GPIO_PUPD5_Msk /* 0x00000C00 */ +#define GPIO_PUPD5_0 (0x0 << GPIO_PUPD5_Pos) /* 0x00000000 */ +#define GPIO_PUPD5_1 (0x1 << GPIO_PUPD5_Pos) /* 0x00000400 */ +#define GPIO_PUPD5_2 (0x2 << GPIO_PUPD5_Pos) /* 0x00000800 */ + +#define GPIO_PUPD6_Pos (12) +#define GPIO_PUPD6_Msk (0x3 << GPIO_PUPD6_Pos) /* 0x00003000 */ +#define GPIO_PUPD6 GPIO_PUPD6_Msk /* 0x00003000 */ +#define GPIO_PUPD6_0 (0x0 << GPIO_PUPD6_Pos) /* 0x00000000 */ +#define GPIO_PUPD6_1 (0x1 << GPIO_PUPD6_Pos) /* 0x00001000 */ +#define GPIO_PUPD6_2 (0x2 << GPIO_PUPD6_Pos) /* 0x00002000 */ + +#define GPIO_PUPD7_Pos (14) +#define GPIO_PUPD7_Msk (0x3 << GPIO_PUPD7_Pos) /* 0x0000C000 */ +#define GPIO_PUPD7 GPIO_PUPD7_Msk /* 0x0000C000 */ +#define GPIO_PUPD7_0 (0x0 << GPIO_PUPD7_Pos) /* 0x00000000 */ +#define GPIO_PUPD7_1 (0x1 << GPIO_PUPD7_Pos) /* 0x00004000 */ +#define GPIO_PUPD7_2 (0x2 << GPIO_PUPD7_Pos) /* 0x00008000 */ + +#define GPIO_PUPD8_Pos (16) +#define GPIO_PUPD8_Msk (0x3 << GPIO_PUPD8_Pos) /* 0x00030000 */ +#define GPIO_PUPD8 GPIO_PUPD8_Msk /* 0x00030000 */ +#define GPIO_PUPD8_0 (0x0 << GPIO_PUPD8_Pos) /* 0x00000000 */ +#define GPIO_PUPD8_1 (0x1 << GPIO_PUPD8_Pos) /* 0x00010000 */ +#define GPIO_PUPD8_2 (0x2 << GPIO_PUPD8_Pos) /* 0x00020000 */ + +#define GPIO_PUPD9_Pos (18) +#define GPIO_PUPD9_Msk (0x3 << GPIO_PUPD9_Pos) /* 0x000C0000 */ +#define GPIO_PUPD9 GPIO_PUPD9_Msk /* 0x000C0000 */ +#define GPIO_PUPD9_0 (0x0 << GPIO_PUPD9_Pos) /* 0x00000000 */ +#define GPIO_PUPD9_1 (0x1 << GPIO_PUPD9_Pos) /* 0x00040000 */ +#define GPIO_PUPD9_2 (0x2 << GPIO_PUPD9_Pos) /* 0x00080000 */ + +#define GPIO_PUPD10_Pos (20) +#define GPIO_PUPD10_Msk (0x3 << GPIO_PUPD10_Pos) /* 0x00300000 */ +#define GPIO_PUPD10 GPIO_PUPD10_Msk /* 0x00300000 */ +#define GPIO_PUPD10_0 (0x0 << GPIO_PUPD10_Pos) /* 0x00000000 */ +#define GPIO_PUPD10_1 (0x1 << GPIO_PUPD10_Pos) /* 0x00100000 */ +#define GPIO_PUPD10_2 (0x2 << GPIO_PUPD10_Pos) /* 0x00200000 */ + +#define GPIO_PUPD11_Pos (22) +#define GPIO_PUPD11_Msk (0x3 << GPIO_PUPD11_Pos) /* 0x00C00000 */ +#define GPIO_PUPD11 GPIO_PUPD11_Msk /* 0x00C00000 */ +#define GPIO_PUPD11_0 (0x0 << GPIO_PUPD11_Pos) /* 0x00000000 */ +#define GPIO_PUPD11_1 (0x1 << GPIO_PUPD11_Pos) /* 0x00400000 */ +#define GPIO_PUPD11_2 (0x2 << GPIO_PUPD11_Pos) /* 0x00800000 */ + +#define GPIO_PUPD12_Pos (24) +#define GPIO_PUPD12_Msk (0x3 << GPIO_PUPD12_Pos) /* 0x03000000 */ +#define GPIO_PUPD12 GPIO_PUPD12_Msk /* 0x03000000 */ +#define GPIO_PUPD12_0 (0x0 << GPIO_PUPD12_Pos) /* 0x00000000 */ +#define GPIO_PUPD12_1 (0x1 << GPIO_PUPD12_Pos) /* 0x01000000 */ +#define GPIO_PUPD12_2 (0x2 << GPIO_PUPD12_Pos) /* 0x02000000 */ + +#define GPIO_PUPD13_Pos (26) +#define GPIO_PUPD13_Msk (0x3 << GPIO_PUPD13_Pos) /* 0x0C000000 */ +#define GPIO_PUPD13 GPIO_PUPD13_Msk /* 0x0C000000 */ +#define GPIO_PUPD13_0 (0x0 << GPIO_PUPD13_Pos) /* 0x00000000 */ +#define GPIO_PUPD13_1 (0x1 << GPIO_PUPD13_Pos) /* 0x04000000 */ +#define GPIO_PUPD13_2 (0x2 << GPIO_PUPD13_Pos) /* 0x08000000 */ + +#define GPIO_PUPD14_Pos (28) +#define GPIO_PUPD14_Msk (0x3 << GPIO_PUPD14_Pos) /* 0x30000000 */ +#define GPIO_PUPD14 GPIO_PUPD14_Msk /* 0x30000000 */ +#define GPIO_PUPD14_0 (0x0 << GPIO_PUPD14_Pos) /* 0x00000000 */ +#define GPIO_PUPD14_1 (0x1 << GPIO_PUPD14_Pos) /* 0x10000000 */ +#define GPIO_PUPD14_2 (0x2 << GPIO_PUPD14_Pos) /* 0x30000000 */ + +#define GPIO_PUPD15_Pos (30) +#define GPIO_PUPD15_Msk (0x3 << GPIO_PUPD15_Pos) /* 0xC0000000 */ +#define GPIO_PUPD15 GPIO_PUPD15_Msk /* 0xC0000000 */ +#define GPIO_PUPD15_0 (0x0 << GPIO_PUPD15_Pos) /* 0x00000000 */ +#define GPIO_PUPD15_1 (0x1 << GPIO_PUPD15_Pos) /* 0x40000000 */ +#define GPIO_PUPD15_2 (0x2 << GPIO_PUPD15_Pos) /* 0x80000000 */ + +/** Bit definition for GPIO_PID register **/ +#define GPIO_PID_PID0 ((uint16_t)0x0001) /* Port input data, bit 0 */ +#define GPIO_PID_PID1 ((uint16_t)0x0002) /* Port input data, bit 1 */ +#define GPIO_PID_PID2 ((uint16_t)0x0004) /* Port input data, bit 2 */ +#define GPIO_PID_PID3 ((uint16_t)0x0008) /* Port input data, bit 3 */ +#define GPIO_PID_PID4 ((uint16_t)0x0010) /* Port input data, bit 4 */ +#define GPIO_PID_PID5 ((uint16_t)0x0020) /* Port input data, bit 5 */ +#define GPIO_PID_PID6 ((uint16_t)0x0040) /* Port input data, bit 6 */ +#define GPIO_PID_PID7 ((uint16_t)0x0080) /* Port input data, bit 7 */ +#define GPIO_PID_PID8 ((uint16_t)0x0100) /* Port input data, bit 8 */ +#define GPIO_PID_PID9 ((uint16_t)0x0200) /* Port input data, bit 9 */ +#define GPIO_PID_PID10 ((uint16_t)0x0400) /* Port input data, bit 10 */ +#define GPIO_PID_PID11 ((uint16_t)0x0800) /* Port input data, bit 11 */ +#define GPIO_PID_PID12 ((uint16_t)0x1000) /* Port input data, bit 12 */ +#define GPIO_PID_PID13 ((uint16_t)0x2000) /* Port input data, bit 13 */ +#define GPIO_PID_PID14 ((uint16_t)0x4000) /* Port input data, bit 14 */ +#define GPIO_PID_PID15 ((uint16_t)0x8000) /* Port input data, bit 15 */ + +/** Bit definition for GPIO_POD register **/ +#define GPIO_POD_POD0 ((uint16_t)0x0001) /* Port output data, bit 0 */ +#define GPIO_POD_POD1 ((uint16_t)0x0002) /* Port output data, bit 1 */ +#define GPIO_POD_POD2 ((uint16_t)0x0004) /* Port output data, bit 2 */ +#define GPIO_POD_POD3 ((uint16_t)0x0008) /* Port output data, bit 3 */ +#define GPIO_POD_POD4 ((uint16_t)0x0010) /* Port output data, bit 4 */ +#define GPIO_POD_POD5 ((uint16_t)0x0020) /* Port output data, bit 5 */ +#define GPIO_POD_POD6 ((uint16_t)0x0040) /* Port output data, bit 6 */ +#define GPIO_POD_POD7 ((uint16_t)0x0080) /* Port output data, bit 7 */ +#define GPIO_POD_POD8 ((uint16_t)0x0100) /* Port output data, bit 8 */ +#define GPIO_POD_POD9 ((uint16_t)0x0200) /* Port output data, bit 9 */ +#define GPIO_POD_POD10 ((uint16_t)0x0400) /* Port output data, bit 10 */ +#define GPIO_POD_POD11 ((uint16_t)0x0800) /* Port output data, bit 11 */ +#define GPIO_POD_POD12 ((uint16_t)0x1000) /* Port output data, bit 12 */ +#define GPIO_POD_POD13 ((uint16_t)0x2000) /* Port output data, bit 13 */ +#define GPIO_POD_POD14 ((uint16_t)0x4000) /* Port output data, bit 14 */ +#define GPIO_POD_POD15 ((uint16_t)0x8000) /* Port output data, bit 15 */ + +/** Bit definition for GPIO_PBSC register **/ +#define GPIO_PBSC_PBS0 ((uint32_t)0x00000001) /* Port x Set bit 0 */ +#define GPIO_PBSC_PBS1 ((uint32_t)0x00000002) /* Port x Set bit 1 */ +#define GPIO_PBSC_PBS2 ((uint32_t)0x00000004) /* Port x Set bit 2 */ +#define GPIO_PBSC_PBS3 ((uint32_t)0x00000008) /* Port x Set bit 3 */ +#define GPIO_PBSC_PBS4 ((uint32_t)0x00000010) /* Port x Set bit 4 */ +#define GPIO_PBSC_PBS5 ((uint32_t)0x00000020) /* Port x Set bit 5 */ +#define GPIO_PBSC_PBS6 ((uint32_t)0x00000040) /* Port x Set bit 6 */ +#define GPIO_PBSC_PBS7 ((uint32_t)0x00000080) /* Port x Set bit 7 */ +#define GPIO_PBSC_PBS8 ((uint32_t)0x00000100) /* Port x Set bit 8 */ +#define GPIO_PBSC_PBS9 ((uint32_t)0x00000200) /* Port x Set bit 9 */ +#define GPIO_PBSC_PBS10 ((uint32_t)0x00000400) /* Port x Set bit 10 */ +#define GPIO_PBSC_PBS11 ((uint32_t)0x00000800) /* Port x Set bit 11 */ +#define GPIO_PBSC_PBS12 ((uint32_t)0x00001000) /* Port x Set bit 12 */ +#define GPIO_PBSC_PBS13 ((uint32_t)0x00002000) /* Port x Set bit 13 */ +#define GPIO_PBSC_PBS14 ((uint32_t)0x00004000) /* Port x Set bit 14 */ +#define GPIO_PBSC_PBS15 ((uint32_t)0x00008000) /* Port x Set bit 15 */ + +#define GPIO_PBSC_PBC0 ((uint32_t)0x00010000) /* Port x Reset bit 0 */ +#define GPIO_PBSC_PBC1 ((uint32_t)0x00020000) /* Port x Reset bit 1 */ +#define GPIO_PBSC_PBC2 ((uint32_t)0x00040000) /* Port x Reset bit 2 */ +#define GPIO_PBSC_PBC3 ((uint32_t)0x00080000) /* Port x Reset bit 3 */ +#define GPIO_PBSC_PBC4 ((uint32_t)0x00100000) /* Port x Reset bit 4 */ +#define GPIO_PBSC_PBC5 ((uint32_t)0x00200000) /* Port x Reset bit 5 */ +#define GPIO_PBSC_PBC6 ((uint32_t)0x00400000) /* Port x Reset bit 6 */ +#define GPIO_PBSC_PBC7 ((uint32_t)0x00800000) /* Port x Reset bit 7 */ +#define GPIO_PBSC_PBC8 ((uint32_t)0x01000000) /* Port x Reset bit 8 */ +#define GPIO_PBSC_PBC9 ((uint32_t)0x02000000) /* Port x Reset bit 9 */ +#define GPIO_PBSC_PBC10 ((uint32_t)0x04000000) /* Port x Reset bit 10 */ +#define GPIO_PBSC_PBC11 ((uint32_t)0x08000000) /* Port x Reset bit 11 */ +#define GPIO_PBSC_PBC12 ((uint32_t)0x10000000) /* Port x Reset bit 12 */ +#define GPIO_PBSC_PBC13 ((uint32_t)0x20000000) /* Port x Reset bit 13 */ +#define GPIO_PBSC_PBC14 ((uint32_t)0x40000000) /* Port x Reset bit 14 */ +#define GPIO_PBSC_PBC15 ((uint32_t)0x80000000) /* Port x Reset bit 15 */ + +/** Bit definition for GPIO_PBC register **/ +#define GPIO_PBC_PBC0 ((uint16_t)0x0001) /* Port x Reset bit 0 */ +#define GPIO_PBC_PBC1 ((uint16_t)0x0002) /* Port x Reset bit 1 */ +#define GPIO_PBC_PBC2 ((uint16_t)0x0004) /* Port x Reset bit 2 */ +#define GPIO_PBC_PBC3 ((uint16_t)0x0008) /* Port x Reset bit 3 */ +#define GPIO_PBC_PBC4 ((uint16_t)0x0010) /* Port x Reset bit 4 */ +#define GPIO_PBC_PBC5 ((uint16_t)0x0020) /* Port x Reset bit 5 */ +#define GPIO_PBC_PBC6 ((uint16_t)0x0040) /* Port x Reset bit 6 */ +#define GPIO_PBC_PBC7 ((uint16_t)0x0080) /* Port x Reset bit 7 */ +#define GPIO_PBC_PBC8 ((uint16_t)0x0100) /* Port x Reset bit 8 */ +#define GPIO_PBC_PBC9 ((uint16_t)0x0200) /* Port x Reset bit 9 */ +#define GPIO_PBC_PBC10 ((uint16_t)0x0400) /* Port x Reset bit 10 */ +#define GPIO_PBC_PBC11 ((uint16_t)0x0800) /* Port x Reset bit 11 */ +#define GPIO_PBC_PBC12 ((uint16_t)0x1000) /* Port x Reset bit 12 */ +#define GPIO_PBC_PBC13 ((uint16_t)0x2000) /* Port x Reset bit 13 */ +#define GPIO_PBC_PBC14 ((uint16_t)0x4000) /* Port x Reset bit 14 */ +#define GPIO_PBC_PBC15 ((uint16_t)0x8000) /* Port x Reset bit 15 */ + +/** Bit definition for GPIO_PLOCK register **/ +#define GPIO_PLOCK_PLOCK0 ((uint32_t)0x00000001) /* Port x Lock bit 0 */ +#define GPIO_PLOCK_PLOCK1 ((uint32_t)0x00000002) /* Port x Lock bit 1 */ +#define GPIO_PLOCK_PLOCK2 ((uint32_t)0x00000004) /* Port x Lock bit 2 */ +#define GPIO_PLOCK_PLOCK3 ((uint32_t)0x00000008) /* Port x Lock bit 3 */ +#define GPIO_PLOCK_PLOCK4 ((uint32_t)0x00000010) /* Port x Lock bit 4 */ +#define GPIO_PLOCK_PLOCK5 ((uint32_t)0x00000020) /* Port x Lock bit 5 */ +#define GPIO_PLOCK_PLOCK6 ((uint32_t)0x00000040) /* Port x Lock bit 6 */ +#define GPIO_PLOCK_PLOCK7 ((uint32_t)0x00000080) /* Port x Lock bit 7 */ +#define GPIO_PLOCK_PLOCK8 ((uint32_t)0x00000100) /* Port x Lock bit 8 */ +#define GPIO_PLOCK_PLOCK9 ((uint32_t)0x00000200) /* Port x Lock bit 9 */ +#define GPIO_PLOCK_PLOCK10 ((uint32_t)0x00000400) /* Port x Lock bit 10 */ +#define GPIO_PLOCK_PLOCK11 ((uint32_t)0x00000800) /* Port x Lock bit 11 */ +#define GPIO_PLOCK_PLOCK12 ((uint32_t)0x00001000) /* Port x Lock bit 12 */ +#define GPIO_PLOCK_PLOCK13 ((uint32_t)0x00002000) /* Port x Lock bit 13 */ +#define GPIO_PLOCK_PLOCK14 ((uint32_t)0x00004000) /* Port x Lock bit 14 */ +#define GPIO_PLOCK_PLOCK15 ((uint32_t)0x00008000) /* Port x Lock bit 15 */ +#define GPIO_PLOCK_PLOCKK ((uint32_t)0x00010000) /* Lock key */ + +/** Bit definition for GPIO_AFL register **/ +#define GPIO_AFL_AFSEL0 ((uint32_t)0x0000000F) /* Port x AFL bit (0..3) */ +#define GPIO_AFL_AFSEL1 ((uint32_t)0x000000F0) /* Port x AFL bit (4..7) */ +#define GPIO_AFL_AFSEL2 ((uint32_t)0x00000F00) /* Port x AFL bit (8..11) */ +#define GPIO_AFL_AFSEL3 ((uint32_t)0x0000F000) /* Port x AFL bit (12..15) */ +#define GPIO_AFL_AFSEL4 ((uint32_t)0x000F0000) /* Port x AFL bit (16..19) */ +#define GPIO_AFL_AFSEL5 ((uint32_t)0x00F00000) /* Port x AFL bit (20..23) */ +#define GPIO_AFL_AFSEL6 ((uint32_t)0x0F000000) /* Port x AFL bit (24..27) */ +#define GPIO_AFL_AFSEL7 ((uint32_t)0xF0000000) /* Port x AFL bit (27..31) */ + +/** Bit definition for GPIO_AFH register **/ +#define GPIO_AFH_AFSEL8 ((uint32_t)0x0000000F) /* Port x AFH bit (0..3) */ +#define GPIO_AFH_AFSEL9 ((uint32_t)0x000000F0) /* Port x AFH bit (4..7) */ +#define GPIO_AFH_AFSEL10 ((uint32_t)0x00000F00) /* Port x AFH bit (8..11) */ +#define GPIO_AFH_AFSEL11 ((uint32_t)0x0000F000) /* Port x AFH bit (12..15) */ +#define GPIO_AFH_AFSEL12 ((uint32_t)0x000F0000) /* Port x AFH bit (16..19) */ +#define GPIO_AFH_AFSEL13 ((uint32_t)0x00F00000) /* Port x AFH bit (20..23) */ +#define GPIO_AFH_AFSEL14 ((uint32_t)0x0F000000) /* Port x AFH bit (24..27) */ +#define GPIO_AFH_AFSEL15 ((uint32_t)0xF0000000) /* Port x AFH bit (27..31) */ + +/** Bit definition for GPIO_DS register **/ +#define GPIO_DS_DS0 ((uint16_t)0x0001) /* Port x Reset bit 0 */ +#define GPIO_DS_DS1 ((uint16_t)0x0002) /* Port x Reset bit 1 */ +#define GPIO_DS_DS2 ((uint16_t)0x0004) /* Port x Reset bit 2 */ +#define GPIO_DS_DS3 ((uint16_t)0x0008) /* Port x Reset bit 3 */ +#define GPIO_DS_DS4 ((uint16_t)0x0010) /* Port x Reset bit 4 */ +#define GPIO_DS_DS5 ((uint16_t)0x0020) /* Port x Reset bit 5 */ +#define GPIO_DS_DS6 ((uint16_t)0x0040) /* Port x Reset bit 6 */ +#define GPIO_DS_DS7 ((uint16_t)0x0080) /* Port x Reset bit 7 */ +#define GPIO_DS_DS8 ((uint16_t)0x0100) /* Port x Reset bit 8 */ +#define GPIO_DS_DS9 ((uint16_t)0x0200) /* Port x Reset bit 9 */ +#define GPIO_DS_DS10 ((uint16_t)0x0400) /* Port x Reset bit 10 */ +#define GPIO_DS_DS11 ((uint16_t)0x0800) /* Port x Reset bit 11 */ +#define GPIO_DS_DS12 ((uint16_t)0x1000) /* Port x Reset bit 12 */ +#define GPIO_DS_DS13 ((uint16_t)0x2000) /* Port x Reset bit 13 */ +#define GPIO_DS_DS14 ((uint16_t)0x4000) /* Port x Reset bit 14 */ +#define GPIO_DS_DS15 ((uint16_t)0x8000) /* Port x Reset bit 15 */ + +/** Bit definition for AFIO_CFG register **/ +#define AFIO_CFG_MASK ((uint16_t)0x001F) /* EXTI_ETRR bit mask */ +#define AFIO_CFG0 ((uint16_t)0x0001) /* AFIO bit 0 */ +#define AFIO_CFG1 ((uint16_t)0x0002) /* AFIO bit 1 */ +#define AFIO_CFG2 ((uint16_t)0x0004) /* AFIO bit 2 */ +#define AFIO_CFG3 ((uint16_t)0x0008) /* AFIO bit 3 */ +#define AFIO_CFG4 ((uint16_t)0x0010) /* AFIO bit 4 */ +#define AFIO_CFG_TIM3CH2_MAP ((uint16_t)0x0020) /* AFIO bit 5 */ +#define AFIO_CFG_SPI_NSS ((uint16_t)0x0040) /* AFIO bit 6 */ + +/*** SystemTick ***/ + +/** Bit definition for SysTick_CTRL register **/ +#define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /* Counter enable */ +#define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /* Counting down to 0 pends the SysTick handler */ +#define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /* Clock source */ +#define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /* Count Flag */ + +/** Bit definition for SysTick_LOAD register **/ +#define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /* Value to load into the SysTick Current Value Register when the counter reaches 0 */ +/** Bit definition for SysTick_VAL register **/ +#define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /* Current value at the time the register is accessed */ + +/** Bit definition for SysTick_CALIB register **/ +#define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /* Reload value to use for 10ms timing */ +#define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /* Calibration value is not exactly 10 ms */ +#define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /* The reference clock is not provided */ + + +/*** Nested Vectored Interrupt Controller ***/ + +/** Bit definition for NVIC_ISER register **/ +#define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /* Interrupt set enable bits */ +#define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /* bit 0 */ +#define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /* bit 1 */ +#define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /* bit 2 */ +#define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /* bit 3 */ +#define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /* bit 4 */ +#define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /* bit 5 */ +#define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /* bit 6 */ +#define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /* bit 7 */ +#define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /* bit 8 */ +#define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /* bit 9 */ +#define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /* bit 10 */ +#define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /* bit 11 */ +#define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /* bit 12 */ +#define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /* bit 13 */ +#define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /* bit 14 */ +#define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /* bit 15 */ +#define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /* bit 16 */ +#define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /* bit 17 */ +#define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /* bit 18 */ +#define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /* bit 19 */ +#define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /* bit 20 */ +#define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /* bit 21 */ +#define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /* bit 22 */ +#define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /* bit 23 */ +#define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /* bit 24 */ +#define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /* bit 25 */ +#define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /* bit 26 */ +#define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /* bit 27 */ +#define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /* bit 28 */ +#define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /* bit 29 */ +#define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /* bit 30 */ +#define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /* bit 31 */ + +/** Bit definition for NVIC_ICER register ***/ +#define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /* Interrupt clear-enable bits */ +#define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /* bit 0 */ +#define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /* bit 1 */ +#define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /* bit 2 */ +#define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /* bit 3 */ +#define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /* bit 4 */ +#define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /* bit 5 */ +#define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /* bit 6 */ +#define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /* bit 7 */ +#define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /* bit 8 */ +#define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /* bit 9 */ +#define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /* bit 10 */ +#define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /* bit 11 */ +#define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /* bit 12 */ +#define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /* bit 13 */ +#define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /* bit 14 */ +#define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /* bit 15 */ +#define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /* bit 16 */ +#define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /* bit 17 */ +#define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /* bit 18 */ +#define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /* bit 19 */ +#define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /* bit 20 */ +#define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /* bit 21 */ +#define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /* bit 22 */ +#define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /* bit 23 */ +#define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /* bit 24 */ +#define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /* bit 25 */ +#define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /* bit 26 */ +#define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /* bit 27 */ +#define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /* bit 28 */ +#define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /* bit 29 */ +#define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /* bit 30 */ +#define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /* bit 31 */ + +/** Bit definition for NVIC_ISPR register **/ +#define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /* Interrupt set-pending bits */ +#define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /* bit 0 */ +#define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /* bit 1 */ +#define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /* bit 2 */ +#define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /* bit 3 */ +#define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /* bit 4 */ +#define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /* bit 5 */ +#define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /* bit 6 */ +#define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /* bit 7 */ +#define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /* bit 8 */ +#define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /* bit 9 */ +#define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /* bit 10 */ +#define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /* bit 11 */ +#define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /* bit 12 */ +#define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /* bit 13 */ +#define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /* bit 14 */ +#define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /* bit 15 */ +#define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /* bit 16 */ +#define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /* bit 17 */ +#define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /* bit 18 */ +#define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /* bit 19 */ +#define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /* bit 20 */ +#define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /* bit 21 */ +#define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /* bit 22 */ +#define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /* bit 23 */ +#define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /* bit 24 */ +#define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /* bit 25 */ +#define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /* bit 26 */ +#define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /* bit 27 */ +#define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /* bit 28 */ +#define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /* bit 29 */ +#define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /* bit 30 */ +#define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /* bit 31 */ + +/** Bit definition for NVIC_ICPR register **/ +#define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /* Interrupt clear-pending bits */ +#define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /* bit 0 */ +#define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /* bit 1 */ +#define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /* bit 2 */ +#define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /* bit 3 */ +#define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /* bit 4 */ +#define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /* bit 5 */ +#define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /* bit 6 */ +#define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /* bit 7 */ +#define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /* bit 8 */ +#define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /* bit 9 */ +#define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /* bit 10 */ +#define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /* bit 11 */ +#define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /* bit 12 */ +#define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /* bit 13 */ +#define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /* bit 14 */ +#define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /* bit 15 */ +#define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /* bit 16 */ +#define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /* bit 17 */ +#define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /* bit 18 */ +#define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /* bit 19 */ +#define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /* bit 20 */ +#define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /* bit 21 */ +#define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /* bit 22 */ +#define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /* bit 23 */ +#define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /* bit 24 */ +#define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /* bit 25 */ +#define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /* bit 26 */ +#define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /* bit 27 */ +#define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /* bit 28 */ +#define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /* bit 29 */ +#define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /* bit 30 */ +#define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /* bit 31 */ + +/** Bit definition for NVIC_PRI0 register **/ +#define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /* Priority of interrupt 0 */ +#define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /* Priority of interrupt 1 */ +#define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /* Priority of interrupt 2 */ +#define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /* Priority of interrupt 3 */ + +/** Bit definition for NVIC_PRI1 register **/ +#define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /* Priority of interrupt 4 */ +#define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /* Priority of interrupt 5 */ +#define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /* Priority of interrupt 6 */ +#define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /* Priority of interrupt 7 */ + +/** Bit definition for NVIC_PRI2 register **/ +#define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /* Priority of interrupt 8 */ +#define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /* Priority of interrupt 9 */ +#define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /* Priority of interrupt 10 */ +#define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /* Priority of interrupt 11 */ + +/** Bit definition for NVIC_PRI3 register **/ +#define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /* Priority of interrupt 12 */ +#define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /* Priority of interrupt 13 */ +#define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /* Priority of interrupt 14 */ +#define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /* Priority of interrupt 15 */ + +/** Bit definition for NVIC_PRI4 register **/ +#define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /* Priority of interrupt 16 */ +#define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /* Priority of interrupt 17 */ +#define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /* Priority of interrupt 18 */ +#define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /* Priority of interrupt 19 */ + +/** Bit definition for NVIC_PRI5 register **/ +#define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /* Priority of interrupt 20 */ +#define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /* Priority of interrupt 21 */ +#define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /* Priority of interrupt 22 */ +#define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /* Priority of interrupt 23 */ + +/** Bit definition for NVIC_PRI6 register **/ +#define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /* Priority of interrupt 24 */ +#define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /* Priority of interrupt 25 */ +#define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /* Priority of interrupt 26 */ +#define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /* Priority of interrupt 27 */ + +/** Bit definition for NVIC_PRI7 register **/ +#define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /* Priority of interrupt 28 */ +#define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /* Priority of interrupt 29 */ +#define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /* Priority of interrupt 30 */ +#define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /* Priority of interrupt 31 */ + +/** Bit definition for SCB_CPUID register **/ +#define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /* Implementation defined revision number */ +#define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /* Number of processor within family */ +#define SCB_CPUID_Constant ((uint32_t)0x000F0000) /* Reads as 0x0F */ +#define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /* Implementation defined variant number */ +#define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /* Implementer code. ARM is 0x41 */ + +/** Bit definition for SCB_ICSR register **/ +#define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /* Active INTSTS number field */ +#define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /* All active exceptions minus the IPSR_current_exception yields the empty set */ +#define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /* Pending INTSTS number field */ +#define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /* Interrupt pending flag */ +#define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /* It indicates that a pending interrupt becomes active in the next running cycle */ +#define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /* Clear pending SysTick bit */ +#define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /* Set pending SysTick bit */ +#define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /* Clear pending pendSV bit */ +#define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /* Set pending pendSV bit */ +#define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /* Set pending NMI bit */ + +/** Bit definition for SCB_AIRCR register **/ +#define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /* Clear active vector bit */ +#define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /* Requests chip control logic to generate a reset */ +#define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /* Data endianness bit */ +#define SCB_AIRCR_VECTKEYSTAT ((uint32_t)0xFFFF0000) /* Reads as 0xFA05 (VECTKEYSTAT) */ +#define SCB_AIRCR_VECTKEY ((uint32_t)0x05FA0000) /* Register access key */ + +/** Bit definition for SCB_SCR register **/ +#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /* Sleep on exit bit */ +#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /* Sleep deep bit */ +#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /* Wake up from WFE */ + +/** Bit definition for SCB_CCR register **/ +#define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /* Trap for unaligned access */ +#define SCB_CCR_STKALIGN ((uint16_t)0x0200) /* On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */ + +/** Bit definition for SCB_SHPR register **/ +#define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /* Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */ +#define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /* Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */ +#define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /* Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */ +#define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /* Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */ + +/** Bit definition for SCB_SHCSR register **/ +#define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /* SVCall is pended */ + +/** Bit definition for SCB_DFSR register **/ +#define SCB_DFSR_HALTED ((uint8_t)0x01) /* Halt request flag */ +#define SCB_DFSR_BKPT ((uint8_t)0x02) /* BKPT flag */ +#define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /* Data Watchpoint and Trace (DWT) flag */ +#define SCB_DFSR_VCATCH ((uint8_t)0x08) /* Vector catch flag */ +#define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /* External debug request flag */ + +/** Bit definition for SCB_afsr register **/ +#define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /* Implementation defined */ + + + +/*** External Interrupt/Event Controller ***/ + +/** Bit definition for EXTI_IMASK register **/ +#define EXTI_IMASK_IMASK0 ((uint32_t)0x00000001) /* Interrupt Mask on line 0 */ +#define EXTI_IMASK_IMASK1 ((uint32_t)0x00000002) /* Interrupt Mask on line 1 */ +#define EXTI_IMASK_IMASK2 ((uint32_t)0x00000004) /* Interrupt Mask on line 2 */ +#define EXTI_IMASK_IMASK3 ((uint32_t)0x00000008) /* Interrupt Mask on line 3 */ +#define EXTI_IMASK_IMASK4 ((uint32_t)0x00000010) /* Interrupt Mask on line 4 */ +#define EXTI_IMASK_IMASK5 ((uint32_t)0x00000020) /* Interrupt Mask on line 5 */ +#define EXTI_IMASK_IMASK6 ((uint32_t)0x00000040) /* Interrupt Mask on line 6 */ +#define EXTI_IMASK_IMASK7 ((uint32_t)0x00000080) /* Interrupt Mask on line 7 */ +#define EXTI_IMASK_IMASK8 ((uint32_t)0x00000100) /* Interrupt Mask on line 8 */ +#define EXTI_IMASK_IMASK9 ((uint32_t)0x00000200) /* Interrupt Mask on line 9 */ +#define EXTI_IMASK_IMASK10 ((uint32_t)0x00000400) /* Interrupt Mask on line 10 */ +#define EXTI_IMASK_IMASK11 ((uint32_t)0x00000800) /* Interrupt Mask on line 11 */ +#define EXTI_IMASK_IMASK12 ((uint32_t)0x00001000) /* Interrupt Mask on line 12 */ +#define EXTI_IMASK_IMASK13 ((uint32_t)0x00002000) /* Interrupt Mask on line 13 */ +#define EXTI_IMASK_IMASK14 ((uint32_t)0x00004000) /* Interrupt Mask on line 14 */ +#define EXTI_IMASK_IMASK15 ((uint32_t)0x00008000) /* Interrupt Mask on line 15 */ +#define EXTI_IMASK_IMASK16 ((uint32_t)0x00010000) /* Interrupt Mask on line 16 */ +#define EXTI_IMASK_IMASK17 ((uint32_t)0x00020000) /* Interrupt Mask on line 17 */ +#define EXTI_IMASK_IMASK18 ((uint32_t)0x00040000) /* Interrupt Mask on line 18 */ +#define EXTI_IMASK_IMASK19 ((uint32_t)0x00080000) /* Interrupt Mask on line 19 */ + +/** Bit definition for EXTI_EMASK register **/ +#define EXTI_EMASK_EMASK0 ((uint32_t)0x00000001) /* Event Mask on line 0 */ +#define EXTI_EMASK_EMASK1 ((uint32_t)0x00000002) /* Event Mask on line 1 */ +#define EXTI_EMASK_EMASK2 ((uint32_t)0x00000004) /* Event Mask on line 2 */ +#define EXTI_EMASK_EMASK3 ((uint32_t)0x00000008) /* Event Mask on line 3 */ +#define EXTI_EMASK_EMASK4 ((uint32_t)0x00000010) /* Event Mask on line 4 */ +#define EXTI_EMASK_EMASK5 ((uint32_t)0x00000020) /* Event Mask on line 5 */ +#define EXTI_EMASK_EMASK6 ((uint32_t)0x00000040) /* Event Mask on line 6 */ +#define EXTI_EMASK_EMASK7 ((uint32_t)0x00000080) /* Event Mask on line 7 */ +#define EXTI_EMASK_EMASK8 ((uint32_t)0x00000100) /* Event Mask on line 8 */ +#define EXTI_EMASK_EMASK9 ((uint32_t)0x00000200) /* Event Mask on line 9 */ +#define EXTI_EMASK_EMASK10 ((uint32_t)0x00000400) /* Event Mask on line 10 */ +#define EXTI_EMASK_EMASK11 ((uint32_t)0x00000800) /* Event Mask on line 11 */ +#define EXTI_EMASK_EMASK12 ((uint32_t)0x00001000) /* Event Mask on line 12 */ +#define EXTI_EMASK_EMASK13 ((uint32_t)0x00002000) /* Event Mask on line 13 */ +#define EXTI_EMASK_EMASK14 ((uint32_t)0x00004000) /* Event Mask on line 14 */ +#define EXTI_EMASK_EMASK15 ((uint32_t)0x00008000) /* Event Mask on line 15 */ +#define EXTI_EMASK_EMASK16 ((uint32_t)0x00010000) /* Event Mask on line 16 */ +#define EXTI_EMASK_EMASK17 ((uint32_t)0x00020000) /* Event Mask on line 17 */ +#define EXTI_EMASK_EMASK18 ((uint32_t)0x00040000) /* Event Mask on line 18 */ +#define EXTI_EMASK_EMASK19 ((uint32_t)0x00080000) /* Event Mask on line 19 */ + +/** Bit definition for EXTI_RT_CFG register **/ +#define EXTI_RT_CFG_RT_CFG0 ((uint32_t)0x00000001) /* Rising trigger event configuration bit of line 0 */ +#define EXTI_RT_CFG_RT_CFG1 ((uint32_t)0x00000002) /* Rising trigger event configuration bit of line 1 */ +#define EXTI_RT_CFG_RT_CFG2 ((uint32_t)0x00000004) /* Rising trigger event configuration bit of line 2 */ +#define EXTI_RT_CFG_RT_CFG3 ((uint32_t)0x00000008) /* Rising trigger event configuration bit of line 3 */ +#define EXTI_RT_CFG_RT_CFG4 ((uint32_t)0x00000010) /* Rising trigger event configuration bit of line 4 */ +#define EXTI_RT_CFG_RT_CFG5 ((uint32_t)0x00000020) /* Rising trigger event configuration bit of line 5 */ +#define EXTI_RT_CFG_RT_CFG6 ((uint32_t)0x00000040) /* Rising trigger event configuration bit of line 6 */ +#define EXTI_RT_CFG_RT_CFG7 ((uint32_t)0x00000080) /* Rising trigger event configuration bit of line 7 */ +#define EXTI_RT_CFG_RT_CFG8 ((uint32_t)0x00000100) /* Rising trigger event configuration bit of line 8 */ +#define EXTI_RT_CFG_RT_CFG9 ((uint32_t)0x00000200) /* Rising trigger event configuration bit of line 9 */ +#define EXTI_RT_CFG_RT_CFG10 ((uint32_t)0x00000400) /* Rising trigger event configuration bit of line 10 */ +#define EXTI_RT_CFG_RT_CFG11 ((uint32_t)0x00000800) /* Rising trigger event configuration bit of line 11 */ +#define EXTI_RT_CFG_RT_CFG12 ((uint32_t)0x00001000) /* Rising trigger event configuration bit of line 12 */ +#define EXTI_RT_CFG_RT_CFG13 ((uint32_t)0x00002000) /* Rising trigger event configuration bit of line 13 */ +#define EXTI_RT_CFG_RT_CFG14 ((uint32_t)0x00004000) /* Rising trigger event configuration bit of line 14 */ +#define EXTI_RT_CFG_RT_CFG15 ((uint32_t)0x00008000) /* Rising trigger event configuration bit of line 15 */ +#define EXTI_RT_CFG_RT_CFG16 ((uint32_t)0x00010000) /* Rising trigger event configuration bit of line 16 */ +#define EXTI_RT_CFG_RT_CFG17 ((uint32_t)0x00020000) /* Rising trigger event configuration bit of line 17 */ +#define EXTI_RT_CFG_RT_CFG18 ((uint32_t)0x00040000) /* Rising trigger event configuration bit of line 18 */ +#define EXTI_RT_CFG_RT_CFG19 ((uint32_t)0x00080000) /* Rising trigger event configuration bit of line 19 */ + +/** Bit definition for EXTI_FT_CFG register **/ +#define EXTI_FT_CFG_FT_CFG0 ((uint32_t)0x00000001) /* Falling trigger event configuration bit of line 0 */ +#define EXTI_FT_CFG_FT_CFG1 ((uint32_t)0x00000002) /* Falling trigger event configuration bit of line 1 */ +#define EXTI_FT_CFG_FT_CFG2 ((uint32_t)0x00000004) /* Falling trigger event configuration bit of line 2 */ +#define EXTI_FT_CFG_FT_CFG3 ((uint32_t)0x00000008) /* Falling trigger event configuration bit of line 3 */ +#define EXTI_FT_CFG_FT_CFG4 ((uint32_t)0x00000010) /* Falling trigger event configuration bit of line 4 */ +#define EXTI_FT_CFG_FT_CFG5 ((uint32_t)0x00000020) /* Falling trigger event configuration bit of line 5 */ +#define EXTI_FT_CFG_FT_CFG6 ((uint32_t)0x00000040) /* Falling trigger event configuration bit of line 6 */ +#define EXTI_FT_CFG_FT_CFG7 ((uint32_t)0x00000080) /* Falling trigger event configuration bit of line 7 */ +#define EXTI_FT_CFG_FT_CFG8 ((uint32_t)0x00000100) /* Falling trigger event configuration bit of line 8 */ +#define EXTI_FT_CFG_FT_CFG9 ((uint32_t)0x00000200) /* Falling trigger event configuration bit of line 9 */ +#define EXTI_FT_CFG_FT_CFG10 ((uint32_t)0x00000400) /* Falling trigger event configuration bit of line 10 */ +#define EXTI_FT_CFG_FT_CFG11 ((uint32_t)0x00000800) /* Falling trigger event configuration bit of line 11 */ +#define EXTI_FT_CFG_FT_CFG12 ((uint32_t)0x00001000) /* Falling trigger event configuration bit of line 12 */ +#define EXTI_FT_CFG_FT_CFG13 ((uint32_t)0x00002000) /* Falling trigger event configuration bit of line 13 */ +#define EXTI_FT_CFG_FT_CFG14 ((uint32_t)0x00004000) /* Falling trigger event configuration bit of line 14 */ +#define EXTI_FT_CFG_FT_CFG15 ((uint32_t)0x00008000) /* Falling trigger event configuration bit of line 15 */ +#define EXTI_FT_CFG_FT_CFG16 ((uint32_t)0x00010000) /* Falling trigger event configuration bit of line 16 */ +#define EXTI_FT_CFG_FT_CFG17 ((uint32_t)0x00020000) /* Falling trigger event configuration bit of line 17 */ +#define EXTI_FT_CFG_FT_CFG18 ((uint32_t)0x00040000) /* Falling trigger event configuration bit of line 18 */ +#define EXTI_FT_CFG_FT_CFG19 ((uint32_t)0x00080000) /* Falling trigger event configuration bit of line 19 */ + +/** Bit definition for EXTI_SWIE register **/ +#define EXTI_SWIE_SWIE0 ((uint32_t)0x00000001) /* Software Interrupt on line 0 */ +#define EXTI_SWIE_SWIE1 ((uint32_t)0x00000002) /* Software Interrupt on line 1 */ +#define EXTI_SWIE_SWIE2 ((uint32_t)0x00000004) /* Software Interrupt on line 2 */ +#define EXTI_SWIE_SWIE3 ((uint32_t)0x00000008) /* Software Interrupt on line 3 */ +#define EXTI_SWIE_SWIE4 ((uint32_t)0x00000010) /* Software Interrupt on line 4 */ +#define EXTI_SWIE_SWIE5 ((uint32_t)0x00000020) /* Software Interrupt on line 5 */ +#define EXTI_SWIE_SWIE6 ((uint32_t)0x00000040) /* Software Interrupt on line 6 */ +#define EXTI_SWIE_SWIE7 ((uint32_t)0x00000080) /* Software Interrupt on line 7 */ +#define EXTI_SWIE_SWIE8 ((uint32_t)0x00000100) /* Software Interrupt on line 8 */ +#define EXTI_SWIE_SWIE9 ((uint32_t)0x00000200) /* Software Interrupt on line 9 */ +#define EXTI_SWIE_SWIE10 ((uint32_t)0x00000400) /* Software Interrupt on line 10 */ +#define EXTI_SWIE_SWIE11 ((uint32_t)0x00000800) /* Software Interrupt on line 11 */ +#define EXTI_SWIE_SWIE12 ((uint32_t)0x00001000) /* Software Interrupt on line 12 */ +#define EXTI_SWIE_SWIE13 ((uint32_t)0x00002000) /* Software Interrupt on line 13 */ +#define EXTI_SWIE_SWIE14 ((uint32_t)0x00004000) /* Software Interrupt on line 14 */ +#define EXTI_SWIE_SWIE15 ((uint32_t)0x00008000) /* Software Interrupt on line 15 */ +#define EXTI_SWIE_SWIE16 ((uint32_t)0x00010000) /* Software Interrupt on line 16 */ +#define EXTI_SWIE_SWIE17 ((uint32_t)0x00020000) /* Software Interrupt on line 17 */ +#define EXTI_SWIE_SWIE18 ((uint32_t)0x00040000) /* Software Interrupt on line 18 */ +#define EXTI_SWIE_SWIE19 ((uint32_t)0x00080000) /* Software Interrupt on line 19 */ + +/** Bit definition for EXTI_PEND register **/ +#define EXTI_PEND_PEND0 ((uint32_t)0x00000001) /* Pending bit for line 0 */ +#define EXTI_PEND_PEND1 ((uint32_t)0x00000002) /* Pending bit for line 1 */ +#define EXTI_PEND_PEND2 ((uint32_t)0x00000004) /* Pending bit for line 2 */ +#define EXTI_PEND_PEND3 ((uint32_t)0x00000008) /* Pending bit for line 3 */ +#define EXTI_PEND_PEND4 ((uint32_t)0x00000010) /* Pending bit for line 4 */ +#define EXTI_PEND_PEND5 ((uint32_t)0x00000020) /* Pending bit for line 5 */ +#define EXTI_PEND_PEND6 ((uint32_t)0x00000040) /* Pending bit for line 6 */ +#define EXTI_PEND_PEND7 ((uint32_t)0x00000080) /* Pending bit for line 7 */ +#define EXTI_PEND_PEND8 ((uint32_t)0x00000100) /* Pending bit for line 8 */ +#define EXTI_PEND_PEND9 ((uint32_t)0x00000200) /* Pending bit for line 9 */ +#define EXTI_PEND_PEND10 ((uint32_t)0x00000400) /* Pending bit for line 10 */ +#define EXTI_PEND_PEND11 ((uint32_t)0x00000800) /* Pending bit for line 11 */ +#define EXTI_PEND_PEND12 ((uint32_t)0x00001000) /* Pending bit for line 12 */ +#define EXTI_PEND_PEND13 ((uint32_t)0x00002000) /* Pending bit for line 13 */ +#define EXTI_PEND_PEND14 ((uint32_t)0x00004000) /* Pending bit for line 14 */ +#define EXTI_PEND_PEND15 ((uint32_t)0x00008000) /* Pending bit for line 15 */ +#define EXTI_PEND_PEND16 ((uint32_t)0x00010000) /* Pending bit for line 16 */ +#define EXTI_PEND_PEND17 ((uint32_t)0x00020000) /* Pending bit for line 17 */ +#define EXTI_PEND_PEND18 ((uint32_t)0x00040000) /* Pending bit for line 18 */ +#define EXTI_PEND_PEND19 ((uint32_t)0x00080000) /* Pending bit for line 19 */ + + + +//*** Analog to Digital Converter ***/ + +/** Bit definition for ADC_STS register **/ +#define ADC_STS_AWDG ((uint8_t)0x01) /* Analog watchdog flag */ +#define ADC_STS_ENDC ((uint8_t)0x02) /* End of conversion */ +#define ADC_STS_STR ((uint8_t)0x04) /* Regular channel Start flag */ +#define ADC_STS_ENDCA ((uint8_t)0x08) /* Regular channel any end flag */ + +/** Bit definition for ADC_CTRL1 register **/ +#define ADC_CTRL1_AWDGCH ((uint32_t)0x0000001F) /* AWDG_CH[3:0] bits (Analog watchdog channel select bits) */ +#define ADC_CTRL1_AWDGCH_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_CTRL1_AWDGCH_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_CTRL1_AWDGCH_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_CTRL1_AWDGCH_3 ((uint32_t)0x00000008) /* Bit 3 */ + +#define ADC_CTRL1_ENDCIEN ((uint32_t)0x00000010) /* Interrupt enable for EOC */ +#define ADC_CTRL1_AWDGIEN ((uint32_t)0x00000020) /* Analog Watchdog interrupt enable */ +#define ADC_CTRL1_AWDGSGLEN ((uint32_t)0x00000040) /* Enable the watchdog on a single channel in scan mode */ +#define ADC_CTRL1_AWDGERCH ((uint32_t)0x00000080) /* Analog watchdog enable on regular channels */ + +/** Bit definition for ADC_CTRL2 register **/ +#define ADC_CTRL2_ON ((uint32_t)0x00000001) /* A/D Converter ON / OFF */ +#define ADC_CTRL2_CTU ((uint32_t)0x00000002) /* Continuous Conversion */ +#define ADC_CTRL2_ALIG ((uint32_t)0x00000040) /* Data Alignment */ + +#define ADC_CTRL2_EXTRSEL ((uint32_t)0x00000078) /* EXTSEL[3:0] bits (External Event Select for regular group) */ +#define ADC_CTRL2_EXTRSEL_0 ((uint32_t)0x00000080) /* Bit 0 */ +#define ADC_CTRL2_EXTRSEL_1 ((uint32_t)0x00000010) /* Bit 1 */ +#define ADC_CTRL2_EXTRSEL_2 ((uint32_t)0x00080020) /* Bit 2 */ +#define ADC_CTRL2_EXTRSEL_3 ((uint32_t)0x00080040) /* Bit 3 */ + +#define ADC_CTRL2_EXTRTRIG ((uint32_t)0x00000080) /* External Trigger Conversion mode for regular channels */ +#define ADC_CTRL2_SWSTRRCH ((uint32_t)0x00000100) /* Start Conversion of regular channels */ + +#define ADC_CTRL2_LEN ((uint32_t)0x00000E00) /* LEN[2:0] bits (Regular Sequence length) */ +#define ADC_CTRL2_LEN_0 ((uint32_t)0x00000200) /* Bit 0 */ +#define ADC_CTRL2_LEN_1 ((uint32_t)0x00000400) /* Bit 1 */ +#define ADC_CTRL2_LEN_2 ((uint32_t)0x00000800) /* Bit 2 */ + +#define ADC_CTRL2_SCANMD ((uint32_t)0x00001000) /* Scan mode */ + +/** Bit definition for ADC_CTRL3 register **/ +#define ADC_CTRL3_VREFEN ((uint16_t)0x0002) /* ADC VREFINT_EN */ +#define ADC_CTRL3_VREFRDY ((uint16_t)0x0004) /* ADC VREFINT_READY */ +#define ADC_CTRL3_RDY ((uint16_t)0x0008) /* ADC Ready */ +#define ADC_CTRL3_PDRDY ((uint16_t)0x0010) /* ADC Power_down Ready */ +#define ADC_CTRL3_ENDCAIEN ((uint16_t)0x0020) /* Interrupt enable for any regular channels */ + +/** Bit definition for ADC_SAMPT register **/ +#define ADC_SAMPT_SAMP ((uint32_t)0x00000001F) /* SMP10[4:0] bits (Channel Sample time selection) */ +#define ADC_SAMPT_SAMP_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SAMPT_SAMP_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SAMPT_SAMP_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SAMPT_SAMP_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SAMPT_SAMP_4 ((uint32_t)0x00000010) /* Bit 4 */ + +/** Bit definition for ADC_WDGHIGH register **/ +#define ADC_WDGHIGH_HTH ((uint16_t)0x0FFF) /* Analog watchdog high threshold */ + +/** Bit definition for ADC_WDGLOW register **/ +#define ADC_WDGLOW_LTH ((uint16_t)0x0FFF) /* Analog watchdog low threshold */ + +/** Bit definition for ADC_DATA0 register **/ +#define ADC_DAT0_DAT ((uint32_t)0x0000FFFF) /* Regular data */ +#define ADC_DAT0_SEQ0 ((uint32_t)0x000F0000) /* channel seqence of conversion */ +#define ADC_DAT0_SEQ0_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define ADC_DAT0_SEQ0_1 ((uint32_t)0x00020000) /* Bit 1 */ +#define ADC_DAT0_SEQ0_2 ((uint32_t)0x00040000) /* Bit 2 */ +#define ADC_DAT0_SEQ0_3 ((uint32_t)0x00080000) /* Bit 3 */ + +/** Bit definition for ADC_DATA1 register **/ +#define ADC_DAT1_DAT ((uint32_t)0x0000FFFF) /* Regular data */ +#define ADC_DAT1_SEQ1 ((uint32_t)0x000F0000) /* channel seqence of conversion */ +#define ADC_DAT1_SEQ1_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define ADC_DAT1_SEQ1_1 ((uint32_t)0x00020000) /* Bit 1 */ +#define ADC_DAT1_SEQ1_2 ((uint32_t)0x00040000) /* Bit 2 */ +#define ADC_DAT1_SEQ1_3 ((uint32_t)0x00080000) /* Bit 3 */ + +/** Bit definition for ADC_DATA2 register **/ +#define ADC_DAT2_DAT ((uint32_t)0x0000FFFF) /* Regular data */ +#define ADC_DAT2_SEQ2 ((uint32_t)0x000F0000) /* channel seqence of conversion */ +#define ADC_DAT2_SEQ2_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define ADC_DAT2_SEQ2_1 ((uint32_t)0x00020000) /* Bit 1 */ +#define ADC_DAT2_SEQ2_2 ((uint32_t)0x00040000) /* Bit 2 */ +#define ADC_DAT2_SEQ2_3 ((uint32_t)0x00080000) /* Bit 3 */ + +/** Bit definition for ADC_DATA3 register **/ +#define ADC_DAT3_DAT ((uint32_t)0x0000FFFF) /* Regular data */ +#define ADC_DAT3_SEQ3 ((uint32_t)0x000F0000) /* channel seqence of conversion */ +#define ADC_DAT3_SEQ3_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define ADC_DAT3_SEQ3_1 ((uint32_t)0x00020000) /* Bit 1 */ +#define ADC_DAT3_SEQ3_2 ((uint32_t)0x00040000) /* Bit 2 */ +#define ADC_DAT3_SEQ3_3 ((uint32_t)0x00080000) /* Bit 3 */ + +/** Bit definition for ADC_DATA4 register **/ +#define ADC_DAT4_DAT ((uint32_t)0x0000FFFF) /* Regular data */ +#define ADC_DAT4_SEQ4 ((uint32_t)0x000F0000) /* channel seqence of conversion */ +#define ADC_DAT4_SEQ4_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define ADC_DAT4_SEQ4_1 ((uint32_t)0x00020000) /* Bit 1 */ +#define ADC_DAT4_SEQ4_2 ((uint32_t)0x00040000) /* Bit 2 */ +#define ADC_DAT4_SEQ4_3 ((uint32_t)0x00080000) /* Bit 3 */ + + + +/*** Comparators Peripheral Interface ***/ + +/** Bit definition for COMP_INTEN register **/ +#define COMP_INTEN_CMPIEN ((uint32_t)0x00000001) /* COMP Interrupt Enable */ + +/** Bit definition for COMP_INTSTS register **/ +#define COMP_INTSTS_CMPIS ((uint32_t)0x00000001) /* COMP Interrupt Status */ + +/** Bit definition for COMP_LOCK register **/ +#define COMP_LOCK_CMPLK ((uint32_t)0x00000001) /* COMP Control Register Lock Enable */ + +/** Bit definition for COMP_CTRL register **/ +#define COMP_CTRL_EN ((uint32_t)0x00000001) /* COMP Enable */ +#define COMP_CTRL_INMSEL ((uint32_t)0x00000002) /* COMP Inverting Input Selection */ +#define COMP_CTRL_INPSEL ((uint32_t)0x00000004) /* COMP Non Inverting Input Selection */ + +#define COMP_CTRL_CMPVOS ((uint32_t)0x00000018) /* COMP Non Inverting Subtraction Selection */ +#define COMP_CTRL_CMPVOS_0 ((uint32_t)0x00000008) /* Bit 0 */ +#define COMP_CTRL_CMPVOS_1 ((uint32_t)0x00000010) /* Bit 1 */ + +#define COMP_CTRL_OUTTRG ((uint32_t)0x00000380) /* COMP Output trigger */ +#define COMP_CTRL_OUTTRG_0 ((uint32_t)0x00000080) /* Bit 0 */ +#define COMP_CTRL_OUTTRG_1 ((uint32_t)0x00000100) /* Bit 1 */ +#define COMP_CTRL_OUTTRG_2 ((uint32_t)0x00000200) /* Bit 2 */ + +#define COMP_CTRL_POL ((uint32_t)0x00000800) /* COMP Output invert */ + +#define COMP_CTRL_HYST ((uint32_t)0x00003000) /* COMP Output Hysteresis Level */ +#define COMP_CTRL_HYST_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define COMP_CTRL_HYST_1 ((uint32_t)0x00002000) /* Bit 1 */ + +#define COMP_CTRL_BLKING ((uint32_t)0x00004000) /* COMP Output Blanking */ +#define COMP_CTRL_OUT ((uint32_t)0x00020000) /* COMP Output Status */ + +/** Bit definition for COMP_FILC register **/ +#define COMP_FILC_FILEN ((uint32_t)0x00000001) /* COMP Filter Enable */ +#define COMP_FILC_THRESH ((uint32_t)0x0000003E) /* COMP Low Filter Majority Voting Threshold */ +#define COMP_FILC_SAMPW ((uint32_t)0x000007C0) /* COMP Low Filter Sample Window Size */ + +/** Bit definition for COMP_FILP register **/ +#define COMP_FILP_CLKPSC ((uint32_t)0x0000FFFF) /* COMP Low Filter Sample Clock Prescale */ + + + +/*** TIM ***/ + +/** Bit definition for TIM_CTRL1 register **/ + +#define TIM_CTRL1_CNTEN ((uint32_t)0x00000001) /* Counter enable */ +#define TIM_CTRL1_UPDIS ((uint32_t)0x00000002) /* Update disable */ +#define TIM_CTRL1_UPRS ((uint32_t)0x00000004) /* Update request source */ +#define TIM_CTRL1_ONEPM ((uint32_t)0x00000008) /* One pulse mode */ +#define TIM_CTRL1_DIR ((uint32_t)0x00000010) /* Direction */ + +#define TIM_CTRL1_CAMSEL ((uint32_t)0x00000060) /* CMS[1:0] bits (Center-aligned mode selection) */ +#define TIM_CTRL1_CAMSEL_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define TIM_CTRL1_CAMSEL_1 ((uint32_t)0x00000040) /* Bit 1 */ + +#define TIM_CTRL1_ARPEN ((uint32_t)0x00000080) /* Auto-reload preload enable */ + +#define TIM_CTRL1_CLKD ((uint32_t)0x00000300) /* CKD[1:0] bits (clock division) */ +#define TIM_CTRL1_CLKD_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define TIM_CTRL1_CLKD_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define TIM_CTRL1_IOMBKPEN ((uint32_t)0x00000400) /* Break_in selection from IOM/COMP */ +#define TIM_CTRL1_C1SEL ((uint32_t)0x00000800) /* Channel 1 selection from IOM/COMP */ +#define TIM_CTRL1_CLRSEL ((uint32_t)0x00008000) /* OCxRef selection from ETR/COMP */ + +#define TIM_CTRL1_LBKPEN ((uint32_t)0x00010000) /* LOCKUP as bkp Enable*/ +#define TIM_CTRL1_PBKPEN ((uint32_t)0x00020000) /* PVD as bkp Enable */ + +/** Bit definition for TIM_CTRL2 register **/ + +#define TIM_CTRL2_CCPCTL ((uint32_t)0x00000001) /* Capture/Compare Preloaded Control */ +#define TIM_CTRL2_CCUSEL ((uint32_t)0x00000004) /* Capture/Compare Control Update Selection */ + +#define TIM_CTRL2_MMSEL ((uint32_t)0x00000070) /* MMS[3:0] bits (Master Mode Selection) */ +#define TIM_CTRL2_MMSEL_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define TIM_CTRL2_MMSEL_1 ((uint32_t)0x00000020) /* Bit 1 */ +#define TIM_CTRL2_MMSEL_2 ((uint32_t)0x00000040) /* Bit 2 */ + + +#define TIM_CTRL2_TI1SEL ((uint32_t)0x00000080) /* TI1 Selection */ + +#define TIM_CTRL2_OI1 ((uint32_t)0x00000100) /* Output Idle state 1 (OC1 output) */ +#define TIM_CTRL2_OI1N ((uint32_t)0x00000200) /* Output Idle state 1 (OC1N output) */ +#define TIM_CTRL2_OI2 ((uint32_t)0x00000400) /* Output Idle state 2 (OC2 output) */ +#define TIM_CTRL2_OI2N ((uint32_t)0x00000800) /* Output Idle state 2 (OC2N output) */ +#define TIM_CTRL2_OI3 ((uint32_t)0x00001000) /* Output Idle state 3 (OC3 output) */ +#define TIM_CTRL2_OI3N ((uint32_t)0x00002000) /* Output Idle state 3 (OC3N output) */ +#define TIM_CTRL2_OI4 ((uint32_t)0x00004000) /* Output Idle state 4 (OC4 output) */ +#define TIM_CTRL2_OI5 ((uint32_t)0x00010000) /* Output Idle state 5 (OC5 output) */ + + +/** Bit definition for TIM_SMCTRL register **/ + +#define TIM_SMCTRL_SMSEL ((uint16_t)0x0007) /* SMS[2:0] bits (Slave mode selection) */ +#define TIM_SMCTRL_SMSEL_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_SMCTRL_SMSEL_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_SMCTRL_SMSEL_2 ((uint16_t)0x0004) /* Bit 2 */ + +#define TIM_SMCTRL_TSEL ((uint16_t)0x0070) /* TS[2:0] bits (Trigger selection) */ +#define TIM_SMCTRL_TSEL_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_SMCTRL_TSEL_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_SMCTRL_TSEL_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_SMCTRL_MSMD ((uint16_t)0x0080) /* Master/slave mode */ + +#define TIM_SMCTRL_EXTF ((uint16_t)0x0F00) /* ETF[3:0] bits (External trigger filter) */ +#define TIM_SMCTRL_EXTF_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_SMCTRL_EXTF_1 ((uint16_t)0x0200) /* Bit 1 */ +#define TIM_SMCTRL_EXTF_2 ((uint16_t)0x0400) /* Bit 2 */ +#define TIM_SMCTRL_EXTF_3 ((uint16_t)0x0800) /* Bit 3 */ + +#define TIM_SMCTRL_EXTPS ((uint16_t)0x3000) /* ETPS[1:0] bits (External trigger prescaler) */ +#define TIM_SMCTRL_EXTPS_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_SMCTRL_EXTPS_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define TIM_SMCTRL_EXCEN ((uint16_t)0x4000) /* External clock enable */ +#define TIM_SMCTRL_EXTP ((uint16_t)0x8000) /* External trigger polarity */ + +/** Bit definition for TIM_DINTEN register **/ + +#define TIM_DINTEN_UIEN ((uint16_t)0x0001) /* Update interrupt enable */ +#define TIM_DINTEN_CC1IEN ((uint16_t)0x0002) /* Capture/Compare 1 interrupt enable */ +#define TIM_DINTEN_CC2IEN ((uint16_t)0x0004) /* Capture/Compare 2 interrupt enable */ +#define TIM_DINTEN_CC3IEN ((uint16_t)0x0008) /* Capture/Compare 3 interrupt enable */ +#define TIM_DINTEN_CC4IEN ((uint16_t)0x0010) /* Capture/Compare 4 interrupt enable */ +#define TIM_DINTEN_COMIEN ((uint16_t)0x0020) /* COM interrupt enable */ +#define TIM_DINTEN_TIEN ((uint16_t)0x0040) /* Trigger interrupt enable */ +#define TIM_DINTEN_BIEN ((uint16_t)0x0080) /* Break interrupt enable */ + +/** Bit definition for TIM_STS register **/ + +#define TIM_STS_UDITF ((uint32_t)0x00000001) /* Update interrupt Flag */ +#define TIM_STS_CC1ITF ((uint32_t)0x00000002) /* Capture/Compare 1 interrupt Flag */ +#define TIM_STS_CC2ITF ((uint32_t)0x00000004) /* Capture/Compare 2 interrupt Flag */ +#define TIM_STS_CC3ITF ((uint32_t)0x00000008) /* Capture/Compare 3 interrupt Flag */ +#define TIM_STS_CC4ITF ((uint32_t)0x00000010) /* Capture/Compare 4 interrupt Flag */ +#define TIM_STS_COMITF ((uint32_t)0x00000020) /* COM interrupt Flag */ +#define TIM_STS_TITF ((uint32_t)0x00000040) /* Trigger interrupt Flag */ +#define TIM_STS_BITF ((uint32_t)0x00000080) /* Break interrupt Flag */ +#define TIM_STS_CC1OCF ((uint32_t)0x00000200) /* Capture/Compare 1 Overcapture Flag */ +#define TIM_STS_CC2OCF ((uint32_t)0x00000400) /* Capture/Compare 2 Overcapture Flag */ +#define TIM_STS_CC3OCF ((uint32_t)0x00000800) /* Capture/Compare 3 Overcapture Flag */ +#define TIM_STS_CC4OCF ((uint32_t)0x00001000) /* Capture/Compare 4 Overcapture Flag */ +#define TIM_STS_CC5ITF ((uint32_t)0x00010000) /* Capture/Compare 5 interrupt Flag */ + + +/** Bit definition for TIM_EVTGEN register **/ + +#define TIM_EVTGEN_UDGN ((uint8_t)0x01) /* Update Generation */ +#define TIM_EVTGEN_CC1GN ((uint8_t)0x02) /* Capture/Compare 1 Generation */ +#define TIM_EVTGEN_CC2GN ((uint8_t)0x04) /* Capture/Compare 2 Generation */ +#define TIM_EVTGEN_CC3GN ((uint8_t)0x08) /* Capture/Compare 3 Generation */ +#define TIM_EVTGEN_CC4GN ((uint8_t)0x10) /* Capture/Compare 4 Generation */ +#define TIM_EVTGEN_CCUDGN ((uint8_t)0x20) /* Capture/Compare Control Update Generation */ +#define TIM_EVTGEN_TGN ((uint8_t)0x40) /* Trigger Generation */ +#define TIM_EVTGEN_BGN ((uint8_t)0x80) /* Break Generation */ + +/** Bit definition for TIM_CCMOD1 register **/ + +#define TIM_CCMOD1_CC1SEL ((uint16_t)0x0003) /* CC1S[1:0] bits (Capture/Compare 1 Selection) */ +#define TIM_CCMOD1_CC1SEL_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_CCMOD1_CC1SEL_1 ((uint16_t)0x0002) /* Bit 1 */ + +#define TIM_CCMOD1_OC1FEN ((uint16_t)0x0004) /* Output Compare 1 Fast enable */ +#define TIM_CCMOD1_OC1PEN ((uint16_t)0x0008) /* Output Compare 1 Preload enable */ + +#define TIM_CCMOD1_OC1MD ((uint16_t)0x0070) /* OC1M[2:0] bits (Output Compare 1 Mode) */ +#define TIM_CCMOD1_OC1MD_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_CCMOD1_OC1MD_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_CCMOD1_OC1MD_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_CCMOD1_OC1CEN ((uint16_t)0x0080) /* Output Compare 1Clear Enable */ + +#define TIM_CCMOD1_CC2SEL ((uint16_t)0x0300) /* CC2S[1:0] bits (Capture/Compare 2 Selection) */ +#define TIM_CCMOD1_CC2SEL_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CCMOD1_CC2SEL_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_CCMOD1_OC2FEN ((uint16_t)0x0400) /* Output Compare 2 Fast enable */ +#define TIM_CCMOD1_OC2PEN ((uint16_t)0x0800) /* Output Compare 2 Preload enable */ + +#define TIM_CCMOD1_OC2MD ((uint16_t)0x7000) /* OC2M[2:0] bits (Output Compare 2 Mode) */ +#define TIM_CCMOD1_OC2MD_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_CCMOD1_OC2MD_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_CCMOD1_OC2MD_2 ((uint16_t)0x4000) /* Bit 2 */ + +#define TIM_CCMOD1_OC2CEN ((uint16_t)0x8000) /* Output Compare 2 Clear Enable */ + +#define TIM_CCMOD1_IC1PSC ((uint16_t)0x000C) /* IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ +#define TIM_CCMOD1_IC1PSC_0 ((uint16_t)0x0004) /* Bit 0 */ +#define TIM_CCMOD1_IC1PSC_1 ((uint16_t)0x0008) /* Bit 1 */ + +#define TIM_CCMOD1_IC1F ((uint16_t)0x00F0) /* IC1F[3:0] bits (Input Capture 1 Filter) */ +#define TIM_CCMOD1_IC1F_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_CCMOD1_IC1F_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_CCMOD1_IC1F_2 ((uint16_t)0x0040) /* Bit 2 */ +#define TIM_CCMOD1_IC1F_3 ((uint16_t)0x0080) /* Bit 3 */ + +#define TIM_CCMOD1_IC2PSC ((uint16_t)0x0C00) /* IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ +#define TIM_CCMOD1_IC2PSC_0 ((uint16_t)0x0400) /* Bit 0 */ +#define TIM_CCMOD1_IC2PSC_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define TIM_CCMOD1_IC2F ((uint16_t)0xF000) /* IC2F[3:0] bits (Input Capture 2 Filter) */ +#define TIM_CCMOD1_IC2F_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_CCMOD1_IC2F_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_CCMOD1_IC2F_2 ((uint16_t)0x4000) /* Bit 2 */ +#define TIM_CCMOD1_IC2F_3 ((uint16_t)0x8000) /* Bit 3 */ + +/** Bit definition for TIM_CCMOD2 register **/ + +#define TIM_CCMOD2_CC3SEL ((uint32_t)0x00000003) /* CC3S[1:0] bits (Capture/Compare 3 Selection) */ +#define TIM_CCMOD2_CC3SEL_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define TIM_CCMOD2_CC3SEL_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define TIM_CCMOD2_OC3FEN ((uint32_t)0x00000004) /* Output Compare 3 Fast enable */ +#define TIM_CCMOD2_OC3PEN ((uint32_t)0x00000008) /* Output Compare 3 Preload enable */ + +#define TIM_CCMOD2_OC3MD ((uint32_t)0x00000070) /* OC3M[2:0] bits (Output Compare 3 Mode) */ +#define TIM_CCMOD2_OC3MD_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define TIM_CCMOD2_OC3MD_1 ((uint32_t)0x00000020) /* Bit 1 */ +#define TIM_CCMOD2_OC3MD_2 ((uint32_t)0x00000040) /* Bit 2 */ + +#define TIM_CCMOD2_OC3CEN ((uint32_t)0x00000080) /* Output Compare 3 Clear Enable */ + +#define TIM_CCMOD2_CC4SEL ((uint32_t)0x00000300) /* CC4S[1:0] bits (Capture/Compare 4 Selection) */ +#define TIM_CCMOD2_CC4SEL_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define TIM_CCMOD2_CC4SEL_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define TIM_CCMOD2_OC4FEN ((uint32_t)0x00000400) /* Output Compare 4 Fast enable */ +#define TIM_CCMOD2_OC4PEN ((uint32_t)0x00000800) /* Output Compare 4 Preload enable */ + +#define TIM_CCMOD2_OC4MD ((uint32_t)0x00007000) /* OC4M[2:0] bits (Output Compare 4 Mode) */ +#define TIM_CCMOD2_OC4MD_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define TIM_CCMOD2_OC4MD_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define TIM_CCMOD2_OC4MD_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define TIM_CCMOD2_OC4CEN ((uint32_t)0x00008000) /* Output Compare 4 Clear Enable */ + + +#define TIM_CCMOD2_IC3PSC ((uint32_t)0x0000000C) /* IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ +#define TIM_CCMOD2_IC3PSC_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define TIM_CCMOD2_IC3PSC_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define TIM_CCMOD2_IC3F ((uint32_t)0x000000F0) /* IC3F[3:0] bits (Input Capture 3 Filter) */ +#define TIM_CCMOD2_IC3F_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define TIM_CCMOD2_IC3F_1 ((uint32_t)0x00000020) /* Bit 1 */ +#define TIM_CCMOD2_IC3F_2 ((uint32_t)0x00000040) /* Bit 2 */ +#define TIM_CCMOD2_IC3F_3 ((uint32_t)0x00000080) /* Bit 3 */ + +#define TIM_CCMOD2_IC4PSC ((uint32_t)0x00000C00) /* IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ +#define TIM_CCMOD2_IC4PSC_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define TIM_CCMOD2_IC4PSC_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define TIM_CCMOD2_IC4F ((uint32_t)0x0000F000) /* IC4F[3:0] bits (Input Capture 4 Filter) */ +#define TIM_CCMOD2_IC4F_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define TIM_CCMOD2_IC4F_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define TIM_CCMOD2_IC4F_2 ((uint32_t)0x00004000) /* Bit 2 */ +#define TIM_CCMOD2_IC4F_3 ((uint32_t)0x00008000) /* Bit 3 */ + +/** Bit definition for TIM_CCMOD3 register **/ + +#define TIM_CCMOD3_OC5FEN ((uint16_t)0x0004) /* Output Compare 5 Fast enable */ +#define TIM_CCMOD3_OC5PEN ((uint16_t)0x0008) /* Output Compare 5 Preload enable */ + +#define TIM_CCMOD3_OC5MD ((uint16_t)0x0070) /* OC5M[2:0] bits (Output Compare 5 Mode) */ +#define TIM_CCMOD3_OC5MD_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_CCMOD3_OC5MD_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_CCMOD3_OC5MD_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_CCMOD3_OC5CEN ((uint16_t)0x0080) /* Output Compare 5Clear Enable */ + + + +/** Bit definition for TIM_CCEN register **/ + +#define TIM_CCEN_CC1EN ((uint32_t)0x00000001) /* Capture/Compare 1 output enable */ +#define TIM_CCEN_CC1P ((uint32_t)0x00000002) /* Capture/Compare 1 output Polarity */ +#define TIM_CCEN_CC1NEN ((uint32_t)0x00000004) /* Capture/Compare 1 Complementary output enable */ +#define TIM_CCEN_CC1NP ((uint32_t)0x00000008) /* Capture/Compare 1 Complementary output Polarity */ +#define TIM_CCEN_CC2EN ((uint32_t)0x00000010) /* Capture/Compare 2 output enable */ +#define TIM_CCEN_CC2P ((uint32_t)0x00000020) /* Capture/Compare 2 output Polarity */ +#define TIM_CCEN_CC2NEN ((uint32_t)0x00000040) /* Capture/Compare 2 Complementary output enable */ +#define TIM_CCEN_CC2NP ((uint32_t)0x00000080) /* Capture/Compare 2 Complementary output Polarity */ +#define TIM_CCEN_CC3EN ((uint32_t)0x00000100) /* Capture/Compare 3 output enable */ +#define TIM_CCEN_CC3P ((uint32_t)0x00000200) /* Capture/Compare 3 output Polarity */ +#define TIM_CCEN_CC3NEN ((uint32_t)0x00000400) /* Capture/Compare 3 Complementary output enable */ +#define TIM_CCEN_CC3NP ((uint32_t)0x00000800) /* Capture/Compare 3 Complementary output Polarity */ +#define TIM_CCEN_CC4EN ((uint32_t)0x00001000) /* Capture/Compare 4 output enable */ +#define TIM_CCEN_CC4P ((uint32_t)0x00002000) /* Capture/Compare 4 output Polarity */ +#define TIM_CCEN_CC5EN ((uint32_t)0x00010000) /* Capture/Compare 5 output enable */ +#define TIM_CCEN_CC5P ((uint32_t)0x00020000) /* Capture/Compare 5 output Polarity */ + + +/** Bit definition for TIM_CNT register **/ +#define TIM_CNT_CNT ((uint16_t)0xFFFF) /* Counter Value */ + +/** Bit definition for TIM_PSC register **/ +#define TIM_PSC_PSC ((uint16_t)0xFFFF) /* Prescaler Value */ + +/** Bit definition for TIM_AR register **/ +#define TIM_AR_AR ((uint16_t)0xFFFF) /* actual auto-reload Value */ + +/** Bit definition for TIM_REPCNT register **/ +#define TIM_REPCNT_REPCNT ((uint8_t)0xFF) /* Repetition Counter Value */ + +/** Bit definition for TIM_CCDAT1 register **/ +#define TIM_CCDAT1_CCDAT1 ((uint16_t)0xFFFF) /* Capture/Compare 1 Value */ + +/** Bit definition for TIM_CCDAT2 register **/ +#define TIM_CCDAT2_CCDAT2 ((uint16_t)0xFFFF) /* Capture/Compare 2 Value */ + +/** Bit definition for TIM_CCDAT3 register **/ +#define TIM_CCDAT3_CCDAT3 ((uint16_t)0xFFFF) /* Capture/Compare 3 Value */ + +/** Bit definition for TIM_CCDAT4 register **/ +#define TIM_CCDAT4_CCDAT4 ((uint16_t)0xFFFF) /* Capture/Compare 4 Value */ + +/** Bit definition for TIM_CCDAT5 register **/ +#define TIM_CCDAT5_CCDAT5 ((uint16_t)0xFFFF) /* Capture/Compare 5 Value */ + + +/** Bit definition for TIM_BKDT register **/ + +#define TIM_BKDT_DTGN ((uint16_t)0x00FF) /* DTG[0:7] bits (Dead-Time Generator set-up) */ +#define TIM_BKDT_DTGN_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_BKDT_DTGN_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_BKDT_DTGN_2 ((uint16_t)0x0004) /* Bit 2 */ +#define TIM_BKDT_DTGN_3 ((uint16_t)0x0008) /* Bit 3 */ +#define TIM_BKDT_DTGN_4 ((uint16_t)0x0010) /* Bit 4 */ +#define TIM_BKDT_DTGN_5 ((uint16_t)0x0020) /* Bit 5 */ +#define TIM_BKDT_DTGN_6 ((uint16_t)0x0040) /* Bit 6 */ +#define TIM_BKDT_DTGN_7 ((uint16_t)0x0080) /* Bit 7 */ + +#define TIM_BKDT_LCKCFG ((uint16_t)0x0300) /* LOCK[1:0] bits (Lock Configuration) */ +#define TIM_BKDT_LCKCFG_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_BKDT_LCKCFG_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_BKDT_OSSI ((uint16_t)0x0400) /* Off-State Selection for Idle mode */ +#define TIM_BKDT_OSSR ((uint16_t)0x0800) /* Off-State Selection for Run mode */ +#define TIM_BKDT_BKEN ((uint16_t)0x1000) /* Break enable */ +#define TIM_BKDT_BKP ((uint16_t)0x2000) /* Break Polarity */ +#define TIM_BKDT_AOEN ((uint16_t)0x4000) /* Automatic Output enable */ +#define TIM_BKDT_MOEN ((uint16_t)0x8000) /* Main Output enable */ + + + + + + +/*** Independent watchdog ***/ + +/** Bit definition for IWDG_KEY register **/ +#define IWDG_KEY_KEYV ((uint16_t)0xFFFF) /* Key value (write only, read 0000h) */ + +/** Bit definition for IWDG_PREDIV register **/ +#define IWDG_PREDIV_PD ((uint8_t)0x07) /* PD[2:0] (Prescaler divider) */ +#define IWDG_PREDIV_PD0 ((uint8_t)0x01) /* Bit 0 */ +#define IWDG_PREDIV_PD1 ((uint8_t)0x02) /* Bit 1 */ +#define IWDG_PREDIV_PD2 ((uint8_t)0x04) /* Bit 2 */ + +/** Bit definition for IWDG_RELV register **/ +#define IWDG_RELV_REL ((uint16_t)0x0FFF) /* Watchdog counter reload value */ + +/** Bit definition for IWDG_STS register **/ +#define IWDG_STS_PVU ((uint8_t)0x01) /* Watchdog prescaler value update */ +#define IWDG_STS_CRVU ((uint8_t)0x02) /* Watchdog counter reload value update */ + +/** Bit definition for IWDG_FREEZE register **/ +#define IWDG_FREEZE_FREEZE ((uint8_t)0x01) /* Watchdog freeze status value */ + +/*** Beeper ***/ + +/** Bit definition for BEEPER_CTRL register **/ +#define BEEPER_CTRL_EN ((uint32_t)0x00000001) /* Bit[0] */ +#define BEEPER_CTRL_INV_EN ((uint32_t)0x00000002) /* Bit[1] */ + +#define BEEPER_CTRL_FREQ_SEL ((uint32_t)0x000000FC) /* Beeper output frequency selection */ +#define BEEPER_CTRL_FREQ_SEL_0 ((uint32_t)0x00000004) /* Bit[0] */ +#define BEEPER_CTRL_FREQ_SEL_1 ((uint32_t)0x00000008) /* Bit[1] */ +#define BEEPER_CTRL_FREQ_SEL_2 ((uint32_t)0x00000010) /* Bit[2] */ +#define BEEPER_CTRL_FREQ_SEL_3 ((uint32_t)0x00000020) /* Bit[3] */ +#define BEEPER_CTRL_FREQ_SEL_4 ((uint32_t)0x00000040) /* Bit[4] */ +#define BEEPER_CTRL_FREQ_SEL_5 ((uint32_t)0x00000080) /* Bit[5] */ + +#define BEEPER_CTRL_FREQ_SEL_8K ((uint32_t)0x00000004) /* Beeper output frequency is 8kHz */ +#define BEEPER_CTRL_FREQ_SEL_4K ((uint32_t)0x0000000C) /* Beeper output frequency is 8kHz */ +#define BEEPER_CTRL_FREQ_SEL_2K ((uint32_t)0x0000001C) /* Beeper output frequency is 8kHz */ +#define BEEPER_CTRL_FREQ_SEL_1K ((uint32_t)0x0000003C) /* Beeper output frequency is 8kHz */ + + + + +/*** Serial Peripheral Interface ***/ + +/** Bit definition for SPI_CTRL1 register **/ + +#define SPI_CTRL1_CLKPHA ((uint16_t)0x0001) /* Clock Phase */ +#define SPI_CTRL1_CLKPOL ((uint16_t)0x0002) /* Clock Polarity */ +#define SPI_CTRL1_MSEL ((uint16_t)0x0004) /* Master Selection */ + +#define SPI_CTRL1_BR ((uint16_t)0x0038) /* BR[2:0] bits (Baud Rate Control) */ +#define SPI_CTRL1_BR0 ((uint16_t)0x0008) /* Bit 0 */ +#define SPI_CTRL1_BR1 ((uint16_t)0x0010) /* Bit 1 */ +#define SPI_CTRL1_BR2 ((uint16_t)0x0020) /* Bit 2 */ + +#define SPI_CTRL1_SPIEN ((uint16_t)0x0040) /* SPI Enable */ +#define SPI_CTRL1_LSBFF ((uint16_t)0x0080) /* Frame Format */ +#define SPI_CTRL1_SSEL ((uint16_t)0x0100) /* Internal slave select */ +#define SPI_CTRL1_SSMEN ((uint16_t)0x0200) /* Software slave management */ +#define SPI_CTRL1_RONLY ((uint16_t)0x0400) /* Receive only */ +#define SPI_CTRL1_DATFF ((uint16_t)0x0800) /* Data Frame Format */ +#define SPI_CTRL1_BIDIROEN ((uint16_t)0x4000) /* Output enable in bidirectional mode */ +#define SPI_CTRL1_BIDIRMODE ((uint16_t)0x8000) /* Bidirectional data mode enable */ + +/** Bit definition for SPI_CTRL2 register **/ +#define SPI_CTRL2_SSOEN ((uint8_t)0x04) /* SS Output Enable */ +#define SPI_CTRL2_ERRINTEN ((uint8_t)0x20) /* Error Interrupt Enable */ +#define SPI_CTRL2_RNEINTEN ((uint8_t)0x40) /* RX buffer Not Empty Interrupt Enable */ +#define SPI_CTRL2_TEINTEN ((uint8_t)0x80) /* Tx buffer Empty Interrupt Enable */ + +/** Bit definition for SPI_STS register **/ +#define SPI_STS_RNE ((uint8_t)0x01) /* Receive buffer Not Empty */ +#define SPI_STS_TE ((uint8_t)0x02) /* Transmit buffer Empty */ +#define SPI_STS_MODERR ((uint8_t)0x20) /* Mode fault */ +#define SPI_STS_OVER ((uint8_t)0x40) /* Overrun flag */ +#define SPI_STS_BUSY ((uint8_t)0x80) /* Busy flag */ + +/** Bit definition for SPI_DAT register **/ +#define SPI_DAT_DAT ((uint16_t)0xFFFF) /* Data Register */ + + +/*** Inter-integrated Circuit Interface ***/ + +/** Bit definition for I2C_CTRL1 register **/ +#define I2C_CTRL1_EN ((uint16_t)0x0001) /* Peripheral Enable */ +#define I2C_CTRL1_PECEN ((uint16_t)0x0020) /* PEC Enable */ +#define I2C_CTRL1_GCEN ((uint16_t)0x0040) /* General Call Enable */ +#define I2C_CTRL1_NOEXTEND ((uint16_t)0x0080) /* Clock Stretching Disable (Slave mode) */ +#define I2C_CTRL1_STARTGEN ((uint16_t)0x0100) /* Start Generation */ +#define I2C_CTRL1_STOPGEN ((uint16_t)0x0200) /* Stop Generation */ +#define I2C_CTRL1_ACKEN ((uint16_t)0x0400) /* Acknowledge Enable */ +#define I2C_CTRL1_ACKPOS ((uint16_t)0x0800) /* Acknowledge/PEC Position (for data reception) */ +#define I2C_CTRL1_PEC ((uint16_t)0x1000) /* Packet Error Checking */ +#define I2C_CTRL1_SWRESET ((uint16_t)0x8000) /* Software Reset */ + +/** Bit definition for I2C_CTRL2 register **/ +#define I2C_CTRL2_CLKFREQ ((uint16_t)0x003F) /* FREQ[5:0] bits (Peripheral Clock Frequency) */ +#define I2C_CTRL2_CLKFREQ_0 ((uint16_t)0x0001) /* Bit 0 */ +#define I2C_CTRL2_CLKFREQ_1 ((uint16_t)0x0002) /* Bit 1 */ +#define I2C_CTRL2_CLKFREQ_2 ((uint16_t)0x0004) /* Bit 2 */ +#define I2C_CTRL2_CLKFREQ_3 ((uint16_t)0x0008) /* Bit 3 */ +#define I2C_CTRL2_CLKFREQ_4 ((uint16_t)0x0010) /* Bit 4 */ +#define I2C_CTRL2_CLKFREQ_5 ((uint16_t)0x0020) /* Bit 5 */ + +#define I2C_CTRL2_ERRINTEN ((uint16_t)0x0100) /* Error Interrupt Enable */ +#define I2C_CTRL2_EVTINTEN ((uint16_t)0x0200) /* Event Interrupt Enable */ +#define I2C_CTRL2_BUFINTEN ((uint16_t)0x0400) /* Buffer Interrupt Enable */ + +/** Bit definition for I2C_OADDR1 register **/ +#define I2C_OADDR1_ADDR1_7 ((uint16_t)0x00FE) /* Interface Address */ +#define I2C_OADDR1_ADDR8_9 ((uint16_t)0x0300) /* Interface Address */ + +#define I2C_OADDR1_ADDR0 ((uint16_t)0x0001) /* Bit 0 */ +#define I2C_OADDR1_ADDR1 ((uint16_t)0x0002) /* Bit 1 */ +#define I2C_OADDR1_ADDR2 ((uint16_t)0x0004) /* Bit 2 */ +#define I2C_OADDR1_ADDR3 ((uint16_t)0x0008) /* Bit 3 */ +#define I2C_OADDR1_ADDR4 ((uint16_t)0x0010) /* Bit 4 */ +#define I2C_OADDR1_ADDR5 ((uint16_t)0x0020) /* Bit 5 */ +#define I2C_OADDR1_ADDR6 ((uint16_t)0x0040) /* Bit 6 */ +#define I2C_OADDR1_ADDR7 ((uint16_t)0x0080) /* Bit 7 */ +#define I2C_OADDR1_ADDR8 ((uint16_t)0x0100) /* Bit 8 */ +#define I2C_OADDR1_ADDR9 ((uint16_t)0x0200) /* Bit 9 */ + +#define I2C_OADDR1_ADDRMODE ((uint16_t)0x8000) /* Addressing Mode (Slave mode) */ + +/** Bit definition for I2C_OADDR2 register **/ +#define I2C_OADDR2_DUALEN ((uint8_t)0x01) /* Dual addressing mode enable */ +#define I2C_OADDR2_ADDR2 ((uint8_t)0xFE) /* Interface address */ + +/** Bit definition for I2C_DAT register **/ +#define I2C_DAT_DATA ((uint8_t)0xFF) /* 8-bit Data Register */ + +/** Bit definition for I2C_STS1 register **/ +#define I2C_STS1_STARTBF ((uint16_t)0x0001) /* Start Bit (Master mode) */ +#define I2C_STS1_ADDRF ((uint16_t)0x0002) /* Address sent (master mode)/matched (slave mode) */ +#define I2C_STS1_BSF ((uint16_t)0x0004) /* Byte Transfer Finished */ +#define I2C_STS1_ADDR10F ((uint16_t)0x0008) /* 10-bit header sent (Master mode) */ +#define I2C_STS1_STOPF ((uint16_t)0x0010) /* Stop detection (Slave mode) */ +#define I2C_STS1_RXDATNE ((uint16_t)0x0040) /* Data Register not Empty (receivers) */ +#define I2C_STS1_TXDATE ((uint16_t)0x0080) /* Data Register Empty (transmitters) */ +#define I2C_STS1_BUSERR ((uint16_t)0x0100) /* Bus Error */ +#define I2C_STS1_ARLOST ((uint16_t)0x0200) /* Arbitration Lost (master mode) */ +#define I2C_STS1_ACKFAIL ((uint16_t)0x0400) /* Acknowledge Failure */ +#define I2C_STS1_OVERRUN ((uint16_t)0x0800) /* Overrun/Underrun */ +#define I2C_STS1_PECERR ((uint16_t)0x1000) /* PEC Error in reception */ + +/** Bit definition for I2C_STS2 register **/ +#define I2C_STS2_MSMODE ((uint16_t)0x0001) /* Master/Slave */ +#define I2C_STS2_BUSY ((uint16_t)0x0002) /* Bus Busy */ +#define I2C_STS2_TRF ((uint16_t)0x0004) /* Transmitter/Receiver */ +#define I2C_STS2_GCALLADDR ((uint16_t)0x0010) /* General Call Address (Slave mode) */ +#define I2C_STS2_DUALFLAG ((uint16_t)0x0080) /* Dual Flag (Slave mode) */ +#define I2C_STS2_PECVAL ((uint16_t)0xFF00) /* Packet Error Checking Register */ + +/** Bit definition for I2C_CLKCTRL register **/ +#define I2C_CLKCTRL_CLKCTRL ((uint16_t)0x0FFF) /* Clock Control Register in Fast/Standard mode (Master mode) */ +#define I2C_CLKCTRL_DUTY ((uint16_t)0x4000) /* Fast Mode Duty Cycle */ +#define I2C_CLKCTRL_FSMODE ((uint16_t)0x8000) /* I2C Master Mode Selection */ + +/****************** Bit definition for I2C_TMRISE register *******************/ +#define I2C_TMRISE_TRISE ((uint8_t)0x3F) /* Maximum Rise Time in Fast/Standard mode (Master mode) */ + +/****************** Bit definition for I2C_GFLTRCTRL register *******************/ +#define I2C_GFLTRCTRL_SDADFW ((uint16_t)0x000F) /* SDA digital gfilter width selection */ +#define I2C_GFLTRCTRL_SCLDFW ((uint16_t)0x00F0) /* SCL digital gfilter width selection */ + +#define I2C_GFLTRCTRL_SDAAFW ((uint16_t)0x0300) /* SDA analog gfilter width selection */ +#define I2C_GFLTRCTRL_SDAAFW_0 ((uint16_t)0x0100) /* Bit 0 */ +#define I2C_GFLTRCTRL_SDAAFW_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define I2C_GFLTRCTRL_SDAAFENN ((uint16_t)0x0400) /* SDA analog gfilter enable */ + +#define I2C_GFLTRCTRL_SCLAFW ((uint16_t)0x1800) /* SCL analog gfilter width selection */ +#define I2C_GFLTRCTRL_SCLAFW_0 ((uint16_t)0x0800) /* Bit 0 */ +#define I2C_GFLTRCTRL_SCLAFW_1 ((uint16_t)0x1000) /* Bit 1 */ + +#define I2C_GFLTRCTRL_SCLAFENN ((uint16_t)0x2000) /* SCL analog gfilter enable */ + +/****************** Bit definition for I2C_BYTENUM register *******************/ +#define I2C_BYTENUM_BYTENUM ((uint16_t)0x3FFF) /* Master receives bytes configuration */ +#define I2C_BYTENUM_RXFSEL ((uint16_t)0x4000) /* Receive end send condition selection */ +#define I2C_BYTENUM_BYTENUMEN ((uint16_t)0x8000) /* Master receive byte control enable */ + + +/*** Universal Asynchronous Receiver Transmitter ***/ +/** Bit definition for UART_STS register **/ +#define UART_STS_PEF ((uint16_t)0x0001) /* Parity Error */ +#define UART_STS_FEF ((uint16_t)0x0002) /* Framing Error */ +#define UART_STS_NEF ((uint16_t)0x0004) /* Noise Error Flag */ +#define UART_STS_OREF ((uint16_t)0x0008) /* OverRun Error */ +#define UART_STS_IDLEF ((uint16_t)0x0010) /* IDLE line detected */ +#define UART_STS_RXDNE ((uint16_t)0x0020) /* Read Data Register Not Empty */ +#define UART_STS_TXC ((uint16_t)0x0040) /* Transmission Complete */ +#define UART_STS_TXDE ((uint16_t)0x0080) /* Transmit Data Register Empty */ + +/** Bit definition for UART_DAT register **/ +#define UART_DAT_DATV ((uint16_t)0x01FF) /* Data value */ + +/** Bit definition for UART_BRCF register **/ +#define UART_BRCF_DIV_Decimal ((uint16_t)0x000F) /* Fraction of UARTDIV */ +#define UART_BRCF_DIV_Integer ((uint16_t)0xFFF0) /* Mantissa of UARTDIV */ + +/** Bit definition for UART_CTRL1 register **/ +#define UART_CTRL1_SDBRK ((uint16_t)0x0001) /* Send Break */ +#define UART_CTRL1_RCVWU ((uint16_t)0x0002) /* Receiver wakeup */ +#define UART_CTRL1_RXEN ((uint16_t)0x0004) /* Receiver Enable */ +#define UART_CTRL1_TXEN ((uint16_t)0x0008) /* Transmitter Enable */ +#define UART_CTRL1_IDLEIEN ((uint16_t)0x0010) /* IDLE Interrupt Enable */ +#define UART_CTRL1_RXDNEIEN ((uint16_t)0x0020) /* RXNE Interrupt Enable */ +#define UART_CTRL1_TXCIEN ((uint16_t)0x0040) /* Transmission Complete Interrupt Enable */ +#define UART_CTRL1_TXDEIEN ((uint16_t)0x0080) /* PE Interrupt Enable */ +#define UART_CTRL1_PEIEN ((uint16_t)0x0100) /* PE Interrupt Enable */ +#define UART_CTRL1_PSEL ((uint16_t)0x0200) /* Parity Selection */ +#define UART_CTRL1_PCEN ((uint16_t)0x0400) /* Parity Control Enable */ +#define UART_CTRL1_WUM ((uint16_t)0x0800) /* Wakeup method */ +#define UART_CTRL1_WL ((uint16_t)0x1000) /* Word length */ +#define UART_CTRL1_UEN ((uint16_t)0x2000) /* UART Enable */ + +/** Bit definition for UART_CTRL2 register **/ +#define UART_CTRL2_ADDR ((uint16_t)0x000F) /* Address of the UART node */ +#define UART_CTRL2_STPB ((uint16_t)0x3000) /* STOP[1:0] bits (STOP bits) */ +#define UART_CTRL2_STPB_0 ((uint16_t)0x1000) /* Bit 0 */ +#define UART_CTRL2_STPB_1 ((uint16_t)0x2000) /* Bit 1 */ + +/** Bit definition for UART_CTRL3 register **/ +#define UART_CTRL3_HDMEN ((uint16_t)0x0008) /* Half-Duplex Selection */ + + +/*** FLASH Registers ***/ + +/** Bit definition for FLASH_AC register **/ +#define FLASH_AC_LATENCY ((uint8_t)0x07) /* LATENCY[2:0] bits (Latency) */ +#define FLASH_AC_LATENCY_0 ((uint8_t)0x00) /* Bit 0 = 0 */ +#define FLASH_AC_LATENCY_1 ((uint8_t)0x01) /* Bit 0 = 1 */ +#define FLASH_AC_LATENCY_2 ((uint8_t)0x02) /* Bit 0 = 0; Bit 1 = 1 */ +#define FLASH_AC_LATENCY_3 ((uint8_t)0x03) /* Bit 0 = 1; Bit 1 = 1 */ + +#define FLASH_AC_PRFTBFEN ((uint8_t)0x10) /* Prefetch Buffer Enable */ +#define FLASH_AC_PRFTBFSTS ((uint8_t)0x20) /* Prefetch Buffer Status */ + +/** Bit definition for FLASH_KEY register **/ +#define FLASH_KEY_FKEY ((uint32_t)0xFFFFFFFF) /* FPEC Key */ + +/** Bit definition for FLASH_OPTKEY register **/ +#define FLASH_OPTKEY_OPTKEY ((uint32_t)0xFFFFFFFF) /* Option Byte Key */ + +/** Bit definition for FLASH_STS register **/ +#define FLASH_STS_BUSY ((uint16_t)0x0001) /* Busy */ +#define FLASH_STS_PGERR ((uint16_t)0x0004) /* Programming Error */ +#define FLASH_STS_WRPERR ((uint16_t)0x0010) /* Write Protection Error */ +#define FLASH_STS_EOP ((uint16_t)0x0020) /* End of operation */ +#define FLASH_STS_SPRERR ((uint16_t)0x0100) /* Spccial Pattern read ERROR */ +#define FLASH_STS_CFGERR ((uint16_t)0x0200) /* Flash initial configuration error */ + +/** Bit definition for FLASH_CTRL register **/ +#define FLASH_CTRL_PG ((uint16_t)0x0001) /* Programming */ +#define FLASH_CTRL_PER ((uint16_t)0x0002) /* Page Erase */ +#define FLASH_CTRL_MER ((uint16_t)0x0004) /* Mass Erase */ +#define FLASH_CTRL_OPTPG ((uint16_t)0x0010) /* Option Byte Programming */ +#define FLASH_CTRL_OPTER ((uint16_t)0x0020) /* Option Byte Erase */ +#define FLASH_CTRL_START ((uint16_t)0x0040) /* Start */ +#define FLASH_CTRL_LOCK ((uint16_t)0x0080) /* Lock */ +#define FLASH_CTRL_MMER ((uint16_t)0x0100) /* Mass Erase flash and optionbytes*/ +#define FLASH_CTRL_OPTWRE ((uint16_t)0x0200) /* Option Bytes Write Enable */ +#define FLASH_CTRL_ERRITE ((uint16_t)0x0400) /* Error Interrupt Enable */ +#define FLASH_CTRL_EOPITE ((uint16_t)0x1000) /* End of operation interrupt enable */ + +/** Bit definition for FLASH_ADD register **/ +#define FLASH_ADD_FADD ((uint32_t)0xFFFFFFFF) /* Flash Address */ + +/** Bit definition for FLASH_OB register **/ +#define FLASH_OB_OBERR ((uint16_t)0x0001) /* Option Byte Error */ +#define FLASH_OB_RDPRT1 ((uint16_t)0x0002) /* Read protection */ + +#define FLASH_OB_USER ((uint16_t)0x007C) /* User Option Bytes */ +#define FLASH_OB_WDG_SW ((uint16_t)0x0004) /* WDG_SW */ +#define FLASH_OB_nRST_STOP ((uint16_t)0x0008) /* nRST_STOP */ +#define FLASH_OB_nRST_PD ((uint16_t)0x0010) /* nRST_STDBY */ +#define FLASH_OB_BOOT_LOCK ((uint16_t)0x0020) /* BOOT_LOCK */ +#define FLASH_OB_NRST_PA0 ((uint16_t)0x0040) /* NRST_PA0 */ + +#define FLASH_OB_DATA0_MSK ((uint32_t)0x0003FC00) /* Data0 mask */ +#define FLASH_OB_DATA1_MSK ((uint32_t)0x03FC0000) /* Data1 mask */ +#define FLASH_OB_RDPRT2 ((uint32_t)0x80000000) /* Read protection level 2 */ + +/** Bit definition for FLASH_USER register **/ +#define FLASH_USER_LVRCNT ((uint32_t)0x000000FF) /* LVR filter control count value */ +#define FLASH_USER_LVRLS ((uint32_t)0x00000F00) /* LVR gear selection */ +#define FLASH_USER_LVREN ((uint32_t)0x00001000) /* LVR enable */ +#define FLASH_USER_LVRFILEN ((uint32_t)0x00002000) /* LVR filter enable */ +#define FLASH_USER_LVRRSTEN ((uint32_t)0x00001000) /* LVR reset enable */ +#define FLASH_USER_POR_DELAY ((uint32_t)0x00FF0000) /* Delay time of CPU reset after POR is triggered */ + +/** Bit definition for FLASH_VTOR register **/ +#define FLASH_VTOR_EN ((uint32_t)0x80000000) /* VTOR enalbe */ +#define FLASH_VTOR_VALUE ((uint32_t)0x7FFFFFFF) /* VTOR address value */ + + + +/*** Option Bytes register ***/ + +/** Bit definition for FLASH_RDP register **/ +#define FLASH_RDP_RDP1 ((uint32_t)0x000000FF) /* Read protection option byte */ +#define FLASH_RDP_nRDP1 ((uint32_t)0x0000FF00) /* Read protection complemented option byte */ + +/** Bit definition for FLASH_USER register **/ +#define FLASH_USER_USER ((uint32_t)0x00FF0000) /* User option byte */ +#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /* User complemented option byte */ + +/** Bit definition for FLASH_Data0 register **/ +#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /* User data storage option byte */ +#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /* User data storage complemented option byte */ + +/** Bit definition for FLASH_Data1 register **/ +#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /* User data storage option byte */ +#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /* User data storage complemented option byte */ + +/** Bit definition for FLASH_WRP0 register **/ +#define FLASH_WRP0_USER2 ((uint32_t)0x000000FF) /* User2 option byte */ +#define FLASH_WRP0_nUSER2 ((uint32_t)0x0000FF00) /* User2 complemented option byte */ + +/** Bit definition for FLASH_WRP1 register **/ +#define FLASH_WRP1_USER3 ((uint32_t)0x00FF0000) /* User3 option byte */ +#define FLASH_WRP1_nUSER3 ((uint32_t)0xFF000000) /* User3 complemented option byte */ + +/** Bit definition for FLASH_WRP3 register **/ +#define FLASH_WRP3_USER4 ((uint32_t)0x00FF0000) /* User4 option byte */ +#define FLASH_WRP3_nUSER4 ((uint32_t)0xFF000000) /* User4 complemented option byte */ + +/** Bit definition for FLASH_RDP2 register **/ +#define FLASH_RDP_RDP2 ((uint32_t)0x000000FF) /* Read protection level 2 option byte */ +#define FLASH_RDP_nRDP2 ((uint32_t)0x0000FF00) /* Read protection level 2 complemented option byte */ + + + +/** Bit Offset register **/ +#define REG_BIT1_OFFSET ((uint32_t)0x00000001) +#define REG_BIT2_OFFSET ((uint32_t)0x00000002) +#define REG_BIT3_OFFSET ((uint32_t)0x00000003) +#define REG_BIT4_OFFSET ((uint32_t)0x00000004) +#define REG_BIT5_OFFSET ((uint32_t)0x00000005) +#define REG_BIT6_OFFSET ((uint32_t)0x00000006) +#define REG_BIT7_OFFSET ((uint32_t)0x00000007) +#define REG_BIT8_OFFSET ((uint32_t)0x00000008) +#define REG_BIT9_OFFSET ((uint32_t)0x00000009) +#define REG_BIT10_OFFSET ((uint32_t)0x0000000A) +#define REG_BIT11_OFFSET ((uint32_t)0x0000000B) +#define REG_BIT12_OFFSET ((uint32_t)0x0000000C) +#define REG_BIT13_OFFSET ((uint32_t)0x0000000D) +#define REG_BIT14_OFFSET ((uint32_t)0x0000000E) +#define REG_BIT15_OFFSET ((uint32_t)0x0000000F) +#define REG_BIT16_OFFSET ((uint32_t)0x00000010) +#define REG_BIT17_OFFSET ((uint32_t)0x00000011) +#define REG_BIT18_OFFSET ((uint32_t)0x00000012) +#define REG_BIT19_OFFSET ((uint32_t)0x00000013) +#define REG_BIT20_OFFSET ((uint32_t)0x00000014) +#define REG_BIT21_OFFSET ((uint32_t)0x00000015) +#define REG_BIT22_OFFSET ((uint32_t)0x00000016) +#define REG_BIT23_OFFSET ((uint32_t)0x00000017) +#define REG_BIT24_OFFSET ((uint32_t)0x00000018) +#define REG_BIT25_OFFSET ((uint32_t)0x00000019) +#define REG_BIT26_OFFSET ((uint32_t)0x0000001A) +#define REG_BIT27_OFFSET ((uint32_t)0x0000001B) +#define REG_BIT28_OFFSET ((uint32_t)0x0000001C) +#define REG_BIT29_OFFSET ((uint32_t)0x0000001D) +#define REG_BIT30_OFFSET ((uint32_t)0x0000001E) +#define REG_BIT31_OFFSET ((uint32_t)0x0000001F) +#define REG_BIT32_OFFSET ((uint32_t)0x00000020) + + + +#ifdef USE_STDPERIPH_DRIVER + #include "n32g003_conf.h" +#endif + +/*** Exported_macro ***/ + +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + + + +#ifdef __cplusplus +} +#endif + +#endif /* __n32g003_H */ + + + + diff --git a/firmware/CMSIS/device/n32g003_conf.h b/firmware/CMSIS/device/n32g003_conf.h new file mode 100644 index 0000000..c6bc693 --- /dev/null +++ b/firmware/CMSIS/device/n32g003_conf.h @@ -0,0 +1,84 @@ +/** +* Copyright (c) 2022, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** +*\*\file n32g003_conf.h +*\*\author Nations +*\*\version v1.0.0 +*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. +**/ + +#ifndef __N32G003_CONF_H__ +#define __N32G003_CONF_H__ + +/* Uncomment/Comment the line below to enable/disable peripheral header file inclusion */ + +#include "n32g003_adc.h" +#include "n32g003_crc.h" +#include "n32g003_comp.h" +#include "n32g003_dbg.h" +#include "n32g003_flash.h" +#include "n32g003_gpio.h" +#include "n32g003_i2c.h" +#include "n32g003_pwr.h" +#include "n32g003_rcc.h" +#include "n32g003_spi.h" +#include "n32g003_tim.h" +#include "n32g003_uart.h" +#include "n32g003_iwdg.h" +#include "n32g003_exti.h" +#include "n32g003_beeper.h" + +#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */ + +/* Uncomment the line below to expanse the "assert_param" macro in the + Standard Peripheral Library drivers code */ + + +#endif /* __N32G003_CONF_H___CONF_H */ + +/******************* (C) COPYRIGHT 2022 NATIONZ *****END OF FILE****/ diff --git a/firmware/CMSIS/device/startup/startup_n32g003.s b/firmware/CMSIS/device/startup/startup_n32g003.s new file mode 100644 index 0000000..eb91d5a --- /dev/null +++ b/firmware/CMSIS/device/startup/startup_n32g003.s @@ -0,0 +1,221 @@ +; Copyright (c) 2022, Nations Technologies Inc. +; +; All rights reserved. +; +; This software is the exclusive property of Nations Technologies Inc. (Hereinafter +; referred to as NATIONS). This software, and the product of NATIONS described herein +; (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +; of the People's Republic of China and other applicable jurisdictions worldwide. +; +; NATIONS does not grant any license under its patents, copyrights, trademarks, or other +; intellectual property rights. Names and brands of third party may be mentioned or referred +; thereto (if any) for identification purposes only. +; +; NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +; improvements to this software at any time without notice. Please contact NATIONS and obtain +; the latest version of this software before placing orders. + +; Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +; no responsibility for the accuracy and reliability of this software. +; +; It is the responsibility of the user of this software to properly design, program, and test +; the functionality and safety of any application made of this information and any resulting product. +; In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +; consequential damages arising in any way out of the use of this software or the Product. +; +; NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +; malfunction or failure of which may cause loss of human life, bodily injury or severe property +; damage. Such applications are deemed, "Insecure Usage". +; +; All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +; harmless from and against all claims, costs, damages, and other liabilities, arising from or related +; to any customer's Insecure Usage. + +; Any express or implied warranty with regard to this software or the Product, including,but not +; limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +; are disclaimed to the fullest extent permitted by law. + +; Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +; or otherwise distribute this software for any purposes, in whole or in part. +; +; NATIONS products and technologies shall not be used for or incorporated into any products or systems +; whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +; User shall comply with any applicable export control laws and regulations promulgated and administered by +; the governments of any countries asserting jurisdiction over the parties or transactions. + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PVD_IRQHandler ; PVD through EXTI Line 18 detect + DCD FLASH_IRQHandler ; Flash + DCD EXTI0_1_IRQHandler ; EXTI Line 0.1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2.3 + DCD EXTI4_17_IRQHandler ; EXTI Line 4..17 + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break/Update/Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM3_IRQHandler ; TIM3 + DCD TIM6_IRQHandler ; TIM6 + DCD ADC_IRQHandler ; ADC + DCD I2C_EV_IRQHandler ; I2C event + DCD I2C_ER_IRQHandler ; I2C error + DCD SPI_IRQHandler ; SPI + DCD UART1_IRQHandler ; UART1 + DCD UART2_IRQHandler ; UART2 + DCD COMP_IRQHandler ; COMP +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT System_Initializes + LDR R0, =System_Initializes + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT PVD_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_17_IRQHandler [WEAK] + EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT I2C_EV_IRQHandler [WEAK] + EXPORT I2C_ER_IRQHandler [WEAK] + EXPORT SPI_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT COMP_IRQHandler [WEAK] + +PVD_IRQHandler +FLASH_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_17_IRQHandler +TIM1_BRK_UP_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM3_IRQHandler +TIM6_IRQHandler +ADC_IRQHandler +I2C_EV_IRQHandler +I2C_ER_IRQHandler +SPI_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +COMP_IRQHandler + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/firmware/CMSIS/device/system_n32g003.c b/firmware/CMSIS/device/system_n32g003.c new file mode 100644 index 0000000..c78feaf --- /dev/null +++ b/firmware/CMSIS/device/system_n32g003.c @@ -0,0 +1,356 @@ +/** +* Copyright (c) 2022, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** +*\*\file system_n32g003.c +*\*\author Nations +*\*\version v1.0.0 +*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32g003.h" + +/* Uncomment the line corresponding to the desired System clock (SYSCLK) + frequency (after reset the HSI is used as SYSCLK source) + + IMPORTANT NOTE: + ============== + 1. After each device reset the HSI is used as System clock source. + + 2. Please make sure that the selected System clock doesn't exceed your + device's maximum frequency. + + 3. If none of the define below is enabled, the HSI is used as System clock + source. + + 4. The System clock configuration functions provided within this file assume + that: + - For Low, Medium and High density Value line devices an external 8MHz + crystal is used to drive the System clock. + - For Low, Medium and High density devices an external 8MHz crystal is + used to drive the System clock. + - For Connectivity line devices an external 25MHz crystal is used to + drive the System clock. If you are using different crystal you have to adapt + those functions accordingly. + */ + +#define SYSCLK_USE_HSI48M 0 +#define SYSCLK_USE_HSI40M 1 + +/*** Configure system clock frequency ***/ +#ifndef SYSCLK_FREQ +#define SYSCLK_FREQ 48000000 +#endif + + +/******* Select one ****** +** SYSCLK_USE_HSI48M ** +** SYSCLK_USE_HSI40M ***/ +#ifndef SYSCLK_SRC +#define SYSCLK_SRC SYSCLK_USE_HSI48M +#endif + +#if SYSCLK_SRC == SYSCLK_USE_HSI48M + + #if (SYSCLK_FREQ == SYSCLK_FREQ_48M) + + #define SYS_DIV RCC_CFG_SYSPRES_DIV1 + + #elif (SYSCLK_FREQ == SYSCLK_FREQ_24M) + + #define SYS_DIV RCC_CFG_SYSPRES_DIV2 + + #elif (SYSCLK_FREQ == SYSCLK_FREQ_8M) + + #define SYS_DIV RCC_CFG_SYSPRES_DIV6 + + #else + #error Cannot make a prescaler to SYSCLK_FREQ. + #endif + +#elif SYSCLK_SRC == SYSCLK_USE_HSI40M + + #if (SYSCLK_FREQ == SYSCLK_FREQ_40M) + + #define SYS_DIV RCC_CFG_SYSPRES_DIV1 + + #elif (SYSCLK_FREQ == SYSCLK_FREQ_8M) + + #define SYS_DIV RCC_CFG_SYSPRES_DIV5 + + #else + #error Cannot make a prescaler to SYSCLK_FREQ. + #endif + +#else +#error wrong value for SYSCLK_SRC +#endif + +/* If you want to use VECT_TAB_SRAM, release the comment*/ +/* #define VECT_TAB_SRAM */ + +/* Vector Table base offset field. This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x0 + +/** Clock Definitions **/ + +/* System Clock Frequency (Core Clock) */ +uint32_t SystemCoreClockFrequency = SYSCLK_FREQ; + +const uint8_t AHBPrescTable[16] = {1, 1, 1, 1, 1, 1, 1, 1, 2, 4, 8, 12, 16, 24, 24,24}; + +static void System_Clock_Set(void); + + + +/** +*\*\name System_Initializes. +*\*\fun Setup the microcontroller system +*\*\ Initialize the Embedded Flash Interface, update the +*\*\ SystemCoreClockFrequency variable. +*\*\param none. +*\*\return none +*\*\note This function should be used only after reset. +**/ +void System_Initializes(void) +{ + + /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ + /* Set HSI 48M bit */ + PWR->CTRL3 &= ~((uint16_t)0x0040); //48M + + /* Set SYSPRES[1:0] bit */ + RCC->CFG |= (uint32_t)0x00003000; + + /* Reset MCO[1:0] APBPRES[2:0] AHBPRES[3:0] bit */ + RCC->CFG &= (uint32_t)0xF9FFF80F; + + /* Reset LSIDETEN bit */ + RCC->LSICTRL &= (uint32_t)0xFFFFFF7F; + + /* Reset TIM1CLKSEL TIM6CLKSEL ADCPRES[3:0]bit */ + RCC->CFG2 &= (uint32_t)0x3FFFFFF0; + + /* Set ADC1MPRES[1:0] ADCPRES[3:0]bit */ + RCC->CFG2 |= (uint32_t)0x00000C01; + + /* Enable Prefetch Buffer */ + FLASH->AC |= (uint32_t)(FLASH_AC_PRFTBFEN); + + /* Configure the System clock frequency, HCLK PCLK prescalers */ + /* Configure the Flash Latency cycles and enable prefetch buffer */ + System_Clock_Set(); + +#ifdef VECT_TAB_SRAM + FLASH->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#else + FLASH->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ +#endif +} + +/** +*\*\name System_Clock_Frequency_Update. +*\*\fun Update SystemCoreClockFrequency variable according to Clock Register Values. +*\*\ The SystemCoreClockFrequency variable contains the core clock (HCLK), it can +*\*\ be used by the user application to setup the SysTick timer or +*\*\ configure other parameters. +*\*\param none. +*\*\return none +*\*\note Each time the core clock (HCLK) changes, this function must be called +*\*\ to update SystemCoreClockFrequency variable value. Otherwise, any +*\*\ configuration based on this variable will be incorrect. +*\*\ +*\*\note The system frequency computed by this function is not the real +*\*\ frequency in the chip. It is calculated based on the predefined +*\*\ constant and the selected clock source. +*\*\ +**/ +void System_Core_Clock_Frequency_Update(void) +{ + uint32_t temp_value = 0; + uint32_t hclkdiv_value = 0; + + /* Get SYSCLK source + * -------------------------------------------------------*/ + temp_value = PWR->CTRL3 & PWR_CTRL3_HSISEL; + + switch (temp_value) + { + case PWR_CTRL3_HSISEL: /* HSI 40M used as system clock */ + if((RCC->CFG & RCC_CFG_SYSPRES) == RCC_CFG_SYSPRES_DIV1) + { + SystemCoreClockFrequency = SYSCLK_FREQ_40M; + } + else + { + SystemCoreClockFrequency = SYSCLK_FREQ_8M; + } + break; + + default:/* HSI 48M used as system clock */ + if((RCC->CFG & RCC_CFG_SYSPRES) == RCC_CFG_SYSPRES_DIV1) + { + SystemCoreClockFrequency = SYSCLK_FREQ_48M; + } + else if((RCC->CFG & RCC_CFG_SYSPRES) == RCC_CFG_SYSPRES_DIV2) + { + SystemCoreClockFrequency = SYSCLK_FREQ_24M; + } + else + { + SystemCoreClockFrequency = SYSCLK_FREQ_8M; + } + break; + } + + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + hclkdiv_value = AHBPrescTable[((RCC->CFG & RCC_CFG_AHBPRES) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClockFrequency /= hclkdiv_value; + +} + +/** +*\*\name Systeminit_Flash_Latency_Set +*\*\fun Sets the code latency value. +*\*\note This function can be used for N32G003 devices. +*\*\param flash_latency : +*\*\ - FLASH_AC_LATENCY_0 FLASH Zero Latency cycle, 0 < HCLK <= 24MHz +*\*\ - FLASH_AC_LATENCY_1 FLASH One Latency cycle, 24MHz < HCLK<= 48MHz +*\*\return none +**/ + +static void Systeminit_Flash_Latency_Set(uint32_t flash_latency) +{ + uint32_t temp_value = 0; + + /* Read the AC register */ + temp_value = FLASH->AC; + + /* Sets the Latency value */ + temp_value &= (~FLASH_LATENCY_MASK); + temp_value |= flash_latency; + + /* Write the AC register */ + FLASH->AC = temp_value; +} + +/** +*\*\name System_Clock_Set. +*\*\fun Configures the System clock frequency, HCLK and PCLK prescalers. +*\*\param none. +*\*\return none +**/ +static void System_Clock_Set(void) +{ + volatile uint32_t temp_value = 0,status_value = 0; + volatile uint32_t counter_value = 0; + + /* Flash wait state 0: SYSCLK <= 24M 1: SYSCLK <= 48M */ + if(SYSCLK_FREQ <= SYSCLK_FREQ_24M) + { + /*8M\24M */ + Systeminit_Flash_Latency_Set(FLASH_AC_LATENCY_0); + } + else + { + /*40M\48M */ + Systeminit_Flash_Latency_Set(FLASH_AC_LATENCY_1); + } + + /* HCLK = SYSCLK */ + RCC->CFG |= (uint32_t)RCC_CFG_AHBPRES_DIV1; + + /* PCLK = HCLK */ + RCC->CFG |= (uint32_t)RCC_CFG_APBPRES_DIV1; + +#if (SYSCLK_SRC == SYSCLK_USE_HSI48M) + + /* Select HSI 48M*/ + PWR->CTRL3 &= ~PWR_CTRL3_HSISEL; //48M + + /* Wait till HSI is ready and if Time out is reached exit */ + do + { + status_value = RCC->HSICTRL & RCC_HSICTRL_HSI48MRDF; + counter_value++; + } while ((status_value == 0) && (counter_value != HSI_STARTUP_TIMEOUT)); + + if(status_value == RCC_HSICTRL_HSI48MRDF) + { + RCC_Sysclk_Config(SYS_DIV); + } + else + { + while(1); + } + + +#elif (SYSCLK_SRC == SYSCLK_USE_HSI40M) + + /* Select HSI 40M */ + PWR->CTRL3 |= PWR_CTRL3_HSISEL; //40M + + /* Wait till HSI is ready and if Time out is reached exit */ + do + { + status_value = RCC->HSICTRL & RCC_HSICTRL_HSI40MRDF; + counter_value++; + } while ((status_value == 0) && (counter_value != HSI_STARTUP_TIMEOUT)); + + if(status_value == RCC_HSICTRL_HSI40MRDF) + { + RCC_Sysclk_Config(SYS_DIV); + } + else + { + while(1); + } +#endif + +} + diff --git a/firmware/CMSIS/device/system_n32g003.h b/firmware/CMSIS/device/system_n32g003.h new file mode 100644 index 0000000..644aeb5 --- /dev/null +++ b/firmware/CMSIS/device/system_n32g003.h @@ -0,0 +1,80 @@ +/** +* Copyright (c) 2022, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** +*\*\file system_n32g003.h +*\*\author Nations +*\*\version v1.0.0 +*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. +**/ + +#ifndef __SYSTEM_N32G003_H +#define __SYSTEM_N32G003_H + +#ifdef __cplusplus + extern "C" { +#endif + +#define SYSCLK_FREQ_48M (48000000) +#define SYSCLK_FREQ_40M (40000000) +#define SYSCLK_FREQ_24M (24000000) +#define SYSCLK_FREQ_8M (8000000) + +extern uint32_t SystemCoreClockFrequency; /* System Clock Frequency (Core Clock) */ + + +extern void System_Initializes(void); +extern void System_Core_Clock_Frequency_Update(void); + + +#ifdef __cplusplus +} +#endif + +#endif /*__SYSTEM_N32G003_H */ + + diff --git a/firmware/n32g003_std_periph_driver/inc/misc.h b/firmware/n32g003_std_periph_driver/inc/misc.h new file mode 100644 index 0000000..92aaf71 --- /dev/null +++ b/firmware/n32g003_std_periph_driver/inc/misc.h @@ -0,0 +1,115 @@ +/** +* Copyright (c) 2022, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** +*\*\file misc.h +*\*\author Nations +*\*\version v1.0.0 +*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. +**/ + +#ifndef __MISC_H__ +#define __MISC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32g003.h" + +/** MISC Driving Functions Declaration **/ + +/** NVIC Init Structure definition **/ + +typedef struct +{ + IRQn_Type NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled. + This parameter can be a value of @ref IRQn_Type + (For the complete N32G003 Devices IRQ Channels list, please + refer to n32g003.h file) */ + + uint8_t NVIC_IRQChannelPriority; /*!< Specifies the priority for the IRQ channel + specified in NVIC_IRQChannel. This parameter can be a value + between 0 and 3 */ + + FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel + will be enabled or disabled. + This parameter can be set either to ENABLE or DISABLE */ +} NVIC_InitType; + + +/** MISC driver modules **/ +#define AIRCR_VECTKEY_MASK SCB_AIRCR_VECTKEY /* access key */ + +/** NVIC Priority **/ +#define NVIC_PRIORITY_0 ((uint8_t)0x00) +#define NVIC_PRIORITY_1 ((uint8_t)0x01) +#define NVIC_PRIORITY_2 ((uint8_t)0x02) +#define NVIC_PRIORITY_3 ((uint8_t)0x03) + +/** System_Low_Power **/ +#define NVIC_LP_SEVONPEND (SCB_SCR_SEVONPEND) +#define NVIC_LP_SLEEPDEEP (SCB_SCR_SLEEPDEEP) +#define NVIC_LP_SLEEPONEXIT (SCB_SCR_SLEEPONEXIT) + +/** SysTick_clock_source **/ +#define SYSTICK_CLKSOURCE_HCLK_DIV8 (~SysTick_CTRL_CLKSOURCE) +#define SYSTICK_CLKSOURCE_HCLK (SysTick_CTRL_CLKSOURCE) + + +void NVIC_Initializes(NVIC_InitType* NVIC_structure_initializes); +void NVIC_System_LowPower_Enable(uint8_t low_power_mode); +void NVIC_System_Low_Power_Disable(uint8_t low_power_mode); +void SysTick_Clock_Source_Set(uint32_t systick_clock_source); + +#ifdef __cplusplus +} +#endif + +#endif /* __MISC_H */ + + diff --git a/firmware/n32g003_std_periph_driver/inc/n32g003_adc.h b/firmware/n32g003_std_periph_driver/inc/n32g003_adc.h new file mode 100644 index 0000000..256430f --- /dev/null +++ b/firmware/n32g003_std_periph_driver/inc/n32g003_adc.h @@ -0,0 +1,295 @@ +/** +* Copyright (c) 2022, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** +*\*\file n32g003_adc.h +*\*\author Nations +*\*\version v1.0.0 +*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. +**/ + +#ifndef __N32G003_ADC_H__ +#define __N32G003_ADC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32g003.h" + +/** ADC init structure definition **/ +typedef struct +{ + FunctionalState MultiChEn; /* Specifies whether the conversion is performed in + Scan (multichannels) or Single (one channel) mode */ + + FunctionalState ContinueConvEn; /* Specifies whether the conversion is performed in + Continuous or Single mode */ + + uint32_t ExtTrigSelect; /* Defines the external trigger used to start the analog + to digital conversion of regular channels */ + + uint32_t DatAlign; /* Specifies whether the ADC data alignment is left or right */ + + uint32_t ChsNumber; /* Specifies the number of ADC channels that will be converted + using the sequencer for regular channel group */ +} ADC_InitType; +/** ADC scan conversion define **/ +#define ADC_MULTCH_ENABLE ((uint32_t)(0x00001000)) /* ADC_CTRL2 SCANMD bits */ +#define ADC_MULTCH_DISABLE ((uint32_t)(~0x00001000)) + +/** ADC continue conversion define **/ +#define ADC_CTU_ENABLE ((uint32_t)(0x00000002)) /* ADC_CTRL2 CTU bits */ +#define ADC_CTU_DISABLE ((uint32_t)(~0x00000002)) + +/** ADC external trigger sources for regular channels conversion define **/ +#define ADC_EXT_TRIGCONV_REGULAR_MASK ((uint32_t)(~(0x00000078|0x00000080))) /* ADC_CTRL2 EXTRSEL[3:0] bits Mask */ +#define ADC_EXT_TRIGCONV_REGULAR_T1_CC1 ((uint32_t)(0x00000000|0x00000080)) +#define ADC_EXT_TRIGCONV_REGULAR_T1_CC2 ((uint32_t)(0x00000008|0x00000080)) +#define ADC_EXT_TRIGCONV_REGULAR_T1_CC3 ((uint32_t)(0x00000010|0x00000080)) +#define ADC_EXT_TRIGCONV_REGULAR_T1_CC4 ((uint32_t)(0x00000018|0x00000080)) +#define ADC_EXT_TRIGCONV_REGULAR_T1_TRGO ((uint32_t)(0x00000020|0x00000080)) +#define ADC_EXT_TRIGCONV_REGULAR_T3_TRGO ((uint32_t)(0x00000028|0x00000080)) +#define ADC_EXT_TRIGCONV_REGULAR_T3_CC1 ((uint32_t)(0x00000030|0x00000080)) +#define ADC_EXT_TRIGCONV_REGULAR_T3_CC2 ((uint32_t)(0x00000038|0x00000080)) +#define ADC_EXT_TRIGCONV_REGULAR_EXT_INT11 ((uint32_t)(0x00000040|0x00000080)) +#define ADC_EXT_TRIGCONV_REGULAR_SWSTRRCH ((uint32_t)0x00000048) + +/** ADC data alignment define **/ +#define ADC_ALIG_MASK ((uint32_t)(~0x00000004)) /* ADC_CTRL2 ALIG bits Mask */ +#define ADC_DAT_ALIGN_R ((uint32_t)0x00000000) +#define ADC_DAT_ALIGN_L ((uint32_t)0x00000004) + +/** ADC regular channel sequence length define **/ +#define ADC_REGULAR_LEN_MSAK ((uint32_t)(~0x00000E00)) /* ADC_CTRL2 LEN[2:0] bits Mask */ +#define ADC_REGULAR_LEN_1 ((uint32_t)0x00000000) +#define ADC_REGULAR_LEN_2 ((uint32_t)0x00000200) +#define ADC_REGULAR_LEN_3 ((uint32_t)0x00000400) +#define ADC_REGULAR_LEN_4 ((uint32_t)0x00000600) +#define ADC_REGULAR_LEN_5 ((uint32_t)0x00000800) + +/** ADC channels define **/ +#define ADC_SQR_MASK ((uint32_t)~0x000f0000) +#define ADC_SQR_OFFSET ((uint32_t)0X10) +#define ADC_CH_0 ((uint8_t)0x00) +#define ADC_CH_1 ((uint8_t)0x01) +#define ADC_CH_2 ((uint8_t)0x02) +#define ADC_CH_3 ((uint8_t)0x03) +#define ADC_CH_4 ((uint8_t)0x04) +#define ADC_CH_5 ((uint8_t)0x05) +#define ADC_CH_6 ((uint8_t)0x06) +#define ADC_CH_7 ((uint8_t)0x07) +#define ADC_CH_8 ((uint8_t)0x08) +#define ADC_CH_9 ((uint8_t)0x09) +#define ADC_CH_10 ((uint8_t)0x0A) +#define ADC_CH_INT_VBG ((uint8_t)ADC_CH_9) +#define ADC_CH_INT_VDDA ((uint8_t)ADC_CH_10) + +#define ADC_Channel_00_PA1 ((uint8_t)0x00) +#define ADC_Channel_01_PA2 ((uint8_t)0x01) +#define ADC_Channel_02_PA5 ((uint8_t)0x02) +#define ADC_Channel_03_PA10 ((uint8_t)0x03) +#define ADC_Channel_04_PA12 ((uint8_t)0x04) +#define ADC_Channel_05_PA13 ((uint8_t)0x05) +#define ADC_Channel_06_PA14 ((uint8_t)0x06) +#define ADC_Channel_07_PB0 ((uint8_t)0x07) +#define ADC_Channel_08_PB1 ((uint8_t)0x08) +#define ADC_Channel_09_VBG ((uint8_t)0x09) +#define ADC_Channel_10_VDDA ((uint8_t)0x0A) +/** ADC converter operation define **/ +#define ADC_TURN_ON ((uint32_t)0x00000001) /* A/D Converter ON / OFF */ +#define ADC_TURN_OFF ((uint32_t)(~0x00000001)) + +/** ADC interrupts define **/ +#define ADC_INT_ENDC ((uint32_t)0x00000010) /* Interrupt enable for EOC */ +#define ADC_INT_AWD ((uint32_t)0x00000020) /* Analog Watchdog interrupt enable */ +#define ADC_INT_ENDCA ((uint32_t)0x00000020) /* Interrupt enable for any EOC */ +#define ADC_SET_INT_TYPE_ENDCA ((uint8_t) 0x01) /* Interrupt enable for any EOC */ +#define ADC_SET_INT_TYPE_OTHER ((uint8_t) 0x00) /* Interrupt enable for other */ + + +#define ADC_EXTTRIGCONV_REGULAR_ENABLE ((uint32_t)ADC_CTRL2_EXTRTRIG) +#define ADC_EXTTRIGCONV_REGULAR_DISABLE ((uint32_t)(~ADC_CTRL2_EXTRTRIG)) + +#define ADC_EXTRTRIG_SWSTRRCH_ENABLE ((uint32_t)(ADC_CTRL2_EXTRTRIG | ADC_CTRL2_SWSTRRCH)) +#define ADC_EXTRTRIG_SWSTRRCH_DISABLE ((uint32_t)(~(ADC_CTRL2_EXTRTRIG | ADC_CTRL2_SWSTRRCH))) +#define ADC_EXTRTRIG_SWSTRRCH_GET_STS ((uint32_t)ADC_CTRL2_SWSTRRCH) + + +/** ADC sampling time define **/ +#define ADC_SAMP_TIME_MASK ((uint32_t)~0x0000001F) +#define ADC_SAMP_TIME_RESERVED ((uint32_t)0x0) +#define ADC_SAMP_TIME_8CYCLES ((uint32_t)0x1) +#define ADC_SAMP_TIME_12CYCLES ((uint32_t)0x2) +#define ADC_SAMP_TIME_14CYCLES ((uint32_t)0x3) +#define ADC_SAMP_TIME_20CYCLES ((uint32_t)0x4) +#define ADC_SAMP_TIME_26CYCLES ((uint32_t)0x5) +#define ADC_SAMP_TIME_30CYCLES ((uint32_t)0x6) +#define ADC_SAMP_TIME_42CYCLES ((uint32_t)0x7) +#define ADC_SAMP_TIME_56CYCLES ((uint32_t)0x8) +#define ADC_SAMP_TIME_72CYCLES ((uint32_t)0x9) +#define ADC_SAMP_TIME_88CYCLES ((uint32_t)0xA) +#define ADC_SAMP_TIME_120CYCLES ((uint32_t)0xB) +#define ADC_SAMP_TIME_182CYCLES ((uint32_t)0xC) +#define ADC_SAMP_TIME_240CYCLES ((uint32_t)0xD) +#define ADC_SAMP_TIME_380CYCLES ((uint32_t)0xE) +#define ADC_SAMP_TIME_760CYCLES ((uint32_t)0xF) +#define ADC_SAMP_TIME_1520CYCLES ((uint32_t)0x10) +#define ADC_SAMP_TIME_3040CYCLES ((uint32_t)0x11) + +/** ADC analog watchdog mode define **/ +#define ADC_ANALOG_WTDG_MODE_MASK ((uint32_t)(~0x00000040)) +#define ADC_ANALOG_WTDG_SINGLE_MODE ((uint32_t)0x00000040)/* Enable the watchdog on a single channel in scan mode */ +#define ADC_ANALOG_WTDG_SCAN_MODE ((uint32_t)0x00000000) + + +/** ADC analog watchdog single mode channel define**/ +#define ADC_ANALOG_WTDG_SINGLE_CH_MASK ((uint32_t)(~0x0000000F))/* AWDG_CH[4:0] bits (Analog watchdog channel select bits) */ +#define ADC_ANALOG_WTDG_SINGLE_CH0 ((uint8_t)0X00) +#define ADC_ANALOG_WTDG_SINGLE_CH1 ((uint8_t)0X01) +#define ADC_ANALOG_WTDG_SINGLE_CH2 ((uint8_t)0X02) +#define ADC_ANALOG_WTDG_SINGLE_CH3 ((uint8_t)0X03) +#define ADC_ANALOG_WTDG_SINGLE_CH4 ((uint8_t)0X04) +#define ADC_ANALOG_WTDG_SINGLE_CH5 ((uint8_t)0X05) +#define ADC_ANALOG_WTDG_SINGLE_CH6 ((uint8_t)0X06) +#define ADC_ANALOG_WTDG_SINGLE_CH7 ((uint8_t)0X07) +#define ADC_ANALOG_WTDG_SINGLE_CH8 ((uint8_t)0X08) +#define ADC_ANALOG_WTDG_SINGLE_CH9 ((uint8_t)0X09) +#define ADC_ANALOG_WTDG_SINGLE_CH10 ((uint8_t)0X0A) + +/** ADC ADC Analog watchdog on regular channels define **/ +#define ADC_ANALOG_WTDG_REGULAR ((uint32_t)0x00000080) /* ADC_CTRL1 AWDGERCH bit */ + +/** ADC flags definition **/ +#define ADC_RUN_FLAG ((uint8_t)0x01) +#define ADC_RD_FLAG ((uint8_t)0x02) + +#define ADC_INT_FLAG_AWDG ((uint8_t)0x01) +#define ADC_INT_FLAG_ENDC ((uint8_t)0x02) +#define ADC_INT_FLAG_ENDCA ((uint8_t)0x08) + + +#define ADC_FLAG_AWDG ((uint8_t)0x01) +#define ADC_FLAG_ENDC ((uint8_t)0x02) +#define ADC_FLAG_STR ((uint8_t)0x04) +#define ADC_FLAG_ENDCA ((uint8_t)0x08) +/** ADC flags ex definition **/ +#define ADC_FLAG_BUF_RDY ((uint8_t)0x04) +#define ADC_FLAG_RDY ((uint8_t)0x08) +#define ADC_FLAG_PD_RDY ((uint8_t)0x10) + + +/** ADC regular data register define **/ +#define ADC_DATA_OFFSET0 ((uint8_t)0x00) +#define ADC_DATA_OFFSET1 ((uint8_t)0X01) +#define ADC_DATA_OFFSET2 ((uint8_t)0X02) +#define ADC_DATA_OFFSET3 ((uint8_t)0X03) +#define ADC_DATA_OFFSET4 ((uint8_t)0X04) + +/** ADC internal input buffer definition **/ +#define ADC_IN_BUFFER_ENABLE ((uint32_t)0x00000002) /*ADC internal input buffer enable.*/ +#define ADC_IN_BUFFER_DISABLE ((uint32_t)(~0x00000002)) + +/* ADC data registers read define */ +#define ADC_DATA_REG_READ(data, num) (*(uint32_t*)(&data+num)) + + + +/** ADC Driving Functions Declaration **/ + +void ADC_Reset(void); + +void ADC_Multichannels_Enable(void); +void ADC_Multichannels_Disable(void); + +void ADC_Continue_Conversion_Enable(void); +void ADC_Continue_Conversion_Disable(void); + +void ADC_Regular_Group_External_Trigger_Source_Config(uint32_t external_trigger_sources); +void ADC_Data_Alignment_Config(uint32_t data_alignment); +void ADC_Regular_Channels_Number_Config(uint32_t channels_number); + +void ADC_Initializes(ADC_InitType* ADC_initstruct); +void ADC_Initializes_Structure(ADC_InitType* ADC_initstruct); + +void ADC_ON(void); +void ADC_OFF(void); + +void ADC_Interrupts_Enable(u8 eoc_any, uint32_t adc_interrupt); +void ADC_Interrupts_Disable(u8 eoc_any, uint32_t adc_interrupt); + +FlagStatus ADC_Regular_Channels_Software_Conversion_Operation(uint32_t conversion_operation); + +void ADC_Channel_Sample_Time_Config(uint8_t sample_time); +void ADC_External_Trigger_Conversion_Config(uint32_t group_operation); + +uint16_t ADC_Regular_Conversion_Data_Get(void); +uint16_t ADC_Regular_Group_Conversion_Data_Get(uint8_t number); + +void ADC_Analog_Watchdog_Mode_Channel_Config(uint32_t mode, uint8_t channel); +void ADC_Analog_Watchdog_Enable(uint32_t wcdg_mode); +void ADC_Analog_Watchdog_Disable(uint32_t wcdg_mode); +void ADC_Analog_Watchdog_HighThresholds_Config(uint16_t high_thresholds); +void ADC_Analog_Watchdog_LowThresholds_Config(uint16_t low_thresholds); + +FlagStatus ADC_INTFlag_Status_Get(uint8_t adc_flag); +FlagStatus ADC_Flag_Status_Get(uint8_t selflag, uint8_t adc_runflag, uint8_t adc_rdflag); +void ADC_INTFlag_Status_Clear(uint8_t adc_flag); +void ADC_Flag_Status_Clear(uint8_t adc_flag); + +void ADC_Regular_Sequence_Single_Config(uint8_t channel); +void ADC_Regular_Sequence_Multi_Config(uint8_t channel,uint8_t number); + +void ADC_Internal_Input_Buffer_Enable(void); +void ADC_Internal_Input_Buffer_Disable(void); + +#ifdef __cplusplus +} +#endif + +#endif /*__N32G003_ADC_H__ */ + diff --git a/firmware/n32g003_std_periph_driver/inc/n32g003_beeper.h b/firmware/n32g003_std_periph_driver/inc/n32g003_beeper.h new file mode 100644 index 0000000..1928cae --- /dev/null +++ b/firmware/n32g003_std_periph_driver/inc/n32g003_beeper.h @@ -0,0 +1,93 @@ +/** +* Copyright (c) 2022, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** +*\*\file n32g003_beeper.h +*\*\author Nations +*\*\version v1.0.0 +*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. +**/ +#ifndef __N32G003_BEEPER_H__ +#define __N32G003_BEEPER_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32g003.h" + + +#define BEEPER_ENABLE (BEEPER_CTRL_EN) /* Enable Beeper */ +#define BEEPER_DISABLE (~BEEPER_CTRL_EN) /* Disable Beeper */ + +#define BEEPER_INV_ENABLE (BEEPER_CTRL_INV_EN) /* Only one output, the other output is off */ +#define BEEPER_INV_DISABLE (~BEEPER_CTRL_INV_EN) /* Both outputs are on, and the outputs are complementary */ + +#define BEEPER_FREQ_SEL_MASK (~BEEPER_CTRL_FREQ_SEL) + +#define BEEPER_FREQ_8KHZ (BEEPER_CTRL_FREQ_SEL_8K) +#define BEEPER_FREQ_4KHZ (BEEPER_CTRL_FREQ_SEL_4K) +#define BEEPER_FREQ_2KHZ (BEEPER_CTRL_FREQ_SEL_2K) +#define BEEPER_FREQ_1KHZ (BEEPER_CTRL_FREQ_SEL_1K) + + + +void BEEPER_Reset(void); +void BEEPER_Frequency_Select(uint32_t freq_selection); +void BEEPER_Inverted_Enable(void); +void BEEPER_Inverted_Disable(void); +void BEEPER_Enable(void); +void BEEPER_Disable(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32G003_BEEPER_H__ */ + + + diff --git a/firmware/n32g003_std_periph_driver/inc/n32g003_comp.h b/firmware/n32g003_std_periph_driver/inc/n32g003_comp.h new file mode 100644 index 0000000..339a7db --- /dev/null +++ b/firmware/n32g003_std_periph_driver/inc/n32g003_comp.h @@ -0,0 +1,208 @@ +/** +* Copyright (c) 2022, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** +*\*\file n32g003_comp.h +*\*\author Nations +*\*\version v1.0.0 +*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. +**/ + +#ifndef __N32G003_COMP_H +#define __N32G003_COMP_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "n32g003.h" +#include + +/** Bit operation definition **/ +#define SetBitMsk(reg, bit, msk) ((reg) = ((reg) & ~(msk) | (bit))) +#define ClrBit(reg, bit) ((reg) &= ~(bit)) +#define SetBit(reg, bit) ((reg) |= (bit)) +#define GetBit(reg, bit) ((reg) & (bit)) + +/** COMP init structure definition **/ +typedef struct +{ + /* ctrl define */ + uint32_t Blking; /* Specifies which timer can control the comp output blanking with its capture event */ + uint32_t Hyst; /* Specifies the comp hysteresis level with low/medium/high level */ + uint32_t PolRev; /* Specifies the comp output polarity */ + uint32_t OutSel; /* Specifies which timer input that can be connecte to the comp output */ + uint32_t SubSel; /* Specifies the comp subtract level with 0/100mv/200mv/300mv level */ + uint32_t InpSel; /* Specifies the comp inpsel */ + uint32_t InmSel; /* Specifies the comp inmsel */ + uint32_t En; /* enable or disable the comp */ + + /* filter define */ + uint8_t SampWindow; /* Initializes comp sampwindow value ~5bit */ + uint8_t Threshold; /* ~5bit ,need > SampWindow/2 */ + uint8_t FilterEn; /* enable or disable the comp filter */ + + /* filter prescale */ + uint16_t ClkPsc; /* Initializes comp clkpsc value ~5bit */ +} COMP_InitType; + +/** COMP blanking definition **/ +#define COMP_BLANKING_MASK ((uint32_t)(~COMP_CTRL_BLKING)) +#define COMP_BLANKING_NO ((uint32_t)0x00000000) +#define COMP_BLANKING_TIM1_OC5 ((uint32_t)COMP_CTRL_BLKING) + +/** COMP hysteresis definition **/ +#define COMP_HYST_MASK ((uint32_t)(~COMP_CTRL_HYST)) +#define COMP_HYST_NO ((uint32_t)0x00000000) +#define COMP_HYST_LOW ((uint32_t)COMP_CTRL_HYST_0) +#define COMP_HYST_MID ((uint32_t)COMP_CTRL_HYST_1) +#define COMP_HYST_HIGH ((uint32_t)(COMP_CTRL_HYST_0 | COMP_CTRL_HYST_1)) + +/** COMP output polarity definition **/ +#define COMP_OUTPOL_MASK ((uint32_t)(~COMP_CTRL_POL)) +#define COMP_OUTPOL_FLIP ((uint32_t)COMP_CTRL_POL) +#define COMP_OUTPOL_NFLIP ((uint32_t)0x00000000) + +/** COMP subtract definition **/ +#define COMP_SUB_MASK ((uint32_t)(~COMP_CTRL_CMPVOS)) +#define COMP_SUB_NO ((uint32_t)0x00000000) +#define COMP_SUB_100mV ((uint32_t)COMP_CTRL_CMPVOS_0) +#define COMP_SUB_200mV ((uint32_t)COMP_CTRL_CMPVOS_1) +#define COMP_SUB_300mV ((uint32_t)(COMP_CTRL_CMPVOS_0 | COMP_CTRL_CMPVOS_1)) + +/** COMP non inverting input definition **/ +#define COMP_INPSEL_MASK ((uint32_t)(~COMP_CTRL_INPSEL)) +#define COMP_INPSEL_RES ((uint32_t)0x00000000) + /** comp inp sel **/ +#define COMP_INPSEL_PB0 ((uint32_t)0x00000000) +#define COMP_INPSEL_PA5 ((uint32_t)0x00000004) + +/** COMP inverting input definition **/ +#define COMP_INMSEL_MASK ((uint32_t)(~COMP_CTRL_INMSEL)) +#define COMP_INMSEL_RES ((uint32_t)0x00000000) +/** comp inm sel **/ +#define COMP_INMSEL_PB1 ((uint32_t)0x00000000) +#define COMP_INMSEL_PA4 ((uint32_t)0x00000002) + +/** COMP output connection definition **/ +#define COMP_OUTSEL_MASK ((uint32_t)(~COMP_CTRL_OUTTRG)) +#define COMP_OUTSEL_RES ((uint32_t)0x00000000) +/** comp out trig **/ +#define COMP_OUTSEL_NO ((uint32_t)0x00000000) +#define COMP_OUTSEL_TIM1_BKIN ((uint32_t)0x00000080) +#define COMP_OUTSEL_TIM1_IC1 ((uint32_t)0x00000100) +#define COMP_OUTSEL_TIM1_OCREFCLEAR ((uint32_t)0x00000180) +#define COMP_OUTSEL_TIM3_IC1 ((uint32_t)0x00000200) +#define COMP_OUTSEL_TIM3_OCREFCLEAR ((uint32_t)0x00000280) + +/** COMP switch definition **/ +#define COMP_ENABLE ((uint32_t)COMP_CTRL_EN) +#define COMP_DISABLE ((uint32_t)(~COMP_CTRL_EN)) + +/** COMP filter definition **/ +#define COMP_FILTER_SAMPW_MASK ((uint16_t)(~COMP_FILC_SAMPW)) /* Low filter sample window size. Number of samples to monitor is SAMPWIN+1. */ +#define COMP_FILTER_THRESHOLD_MASK ((uint16_t)(~COMP_FILC_THRESH)) /* For proper operation, the value of THRESHOLD must be greater than SAMPWIN / 2. */ + +#define COMP_FILTER_ENABLE ((uint16_t)COMP_FILC_FILEN) /* Filter enable. */ +#define COMP_FILTER_DISABLE ((uint16_t)(~COMP_FILC_FILEN)) /* Filter disable. */ + +/** COMP filter prescale definition **/ +#define COMP_FILTER_CLKPSC_MASK ((uint16_t)(~COMP_FILP_CLKPSC)) /* Low filter sample clock prescale.Number of system clocks between samples = CLK_PRE_CYCLE + 1, e.g. */ + +/** COMP lock definition**/ +#define COMP_LOCK_MSK ((uint16_t)(~COMP_LOCK_CMPLK)) /* COMP Lock bit */ +#define COMP_LOCK ((uint16_t)COMP_LOCK_CMPLK) /* COMP Lock bit */ + +/** COMP interrupt enable definition **/ +#define COMP_INTEN_MSK ((uint16_t)(~COMP_INTEN_CMPIEN)) +#define COMP_INTEN ((uint16_t)COMP_INTEN_CMPIEN) /* This bit control Interrput enable of COMP. */ + +/** COMP interrupt status clear definition **/ +#define COMP_INTS_CLEAR ((uint32_t)(~COMP_INTSTS_CMPIS)) + +/** COMP output status definition**/ +#define COMP_OUT_MASK ((uint32_t)(~COMP_CTRL_OUT)) +#define COMP_OUT ((uint32_t)COMP_CTRL_OUT) + +/** COMP Driving Functions Declaration **/ +void COMP_Reset(void); + +void COMP_Initializes_Structure(COMP_InitType* COMP_initstruct); +void COMP_Filter_SampWindow_Config(uint8_t sampwin_value); +void COMP_Filter_Threshold_Config(uint8_t Threshold_value); +void COMP_Filter_Enable(void); +void COMP_Filter_Disable(void); +void COMP_Filter_Clock_Prescale_Config(uint16_t clkpsc_value); +void COMP_Blking_Soucre_Config(uint32_t blking_mode); +void COMP_Hysteresis_Level_Config(uint32_t hyst_mode); +void COMP_Output_Polarity_Config(uint32_t output_pol); +void COMP_InpSel_Config(uint32_t vpsel); +void COMP_InmSel_Config(uint32_t vpsel); +void COMP_Subtract_Level_Config(uint32_t sub_mode); +void COMP_Output_Trigger_Config(uint32_t outtrgsel); + +void COMP_ON(void); +void COMP_OFF(void); + +void COMP_Lock_Config(void); +void COMP_Interrupt_Enable(uint32_t inten); +void COMP_Interrupt_Disable(uint32_t inten); +uint8_t COMP_Interrupt_Status_Get(void); +void COMP_Interrupt_Status_Clear(void); + +FlagStatus COMP_Output_Status_Get(void); + +void COMP_Filter_Control_Config(uint32_t sw, uint8_t threshold , uint8_t sampwindow); + +void COMP_Initializes(COMP_InitType* COMP_initstruct); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32G003_COMP_H */ + diff --git a/firmware/n32g003_std_periph_driver/inc/n32g003_crc.h b/firmware/n32g003_std_periph_driver/inc/n32g003_crc.h new file mode 100644 index 0000000..be15773 --- /dev/null +++ b/firmware/n32g003_std_periph_driver/inc/n32g003_crc.h @@ -0,0 +1,99 @@ +/** +* Copyright (c) 2022, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** +*\*\file n32g003_crc.h +*\*\author Nations +*\*\version v1.0.0 +*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ + + +#ifndef __N32G003_CRC_H_ +#define __N32G003_CRC_H_ + +#ifdef __cplusplus + extern "C" { +#endif + +#include "n32g003.h" + +/*** CRC Structure Definition Start ***/ + +/*** CRC Structure Definition End ***/ + +/*** CRC Macro Definition Start ***/ + + +/** CRC clear the CRC16 check value definition **/ +#define CRC_CRC16_VALUE_CLEAR ((uint32_t)CRC16_CTRL_RESET) +#define CRC_CRC16_VALUE_NO_CLEAR ((uint32_t)CRC16_CTRL_NO_RESET) + +/** CRC little-endian and big-endian definition **/ +#define CRC_LITTLE_ENDIAN_ENABLE ((uint32_t)CRC16_CTRL_LITTLE) /* Set little-endian */ +#define CRC_BIG_ENDIAN_ENABLE ((uint32_t)CRC16_CTRL_BIG) /* Set big-endian */ + +/*** CRC Macro Definition End ***/ + +/*** CRC Driving Functions Declaration ***/ +uint16_t CRC16_Calculate(uint8_t data); +uint16_t CRC16_Buffer_Calculate(uint8_t p_buf[], uint32_t buf_len); +void CRC16_Set(uint8_t data); +uint16_t CRC16_Get(void); +void CRC16_Little_Endian_Format_Set(void); +void CRC16_Big_Endian_Format_Set(void); +void CRC16_Value_Clean_Enable(void); +void CRC16_Value_Clean_Disable(void); +void CRC_LRC_Set(uint8_t data); +uint8_t CRC_LRC_Get(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32G003_CRC_H_ */ + diff --git a/firmware/n32g003_std_periph_driver/inc/n32g003_dbg.h b/firmware/n32g003_std_periph_driver/inc/n32g003_dbg.h new file mode 100644 index 0000000..2f0d219 --- /dev/null +++ b/firmware/n32g003_std_periph_driver/inc/n32g003_dbg.h @@ -0,0 +1,73 @@ +/** +* Copyright (c) 2022, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** +*\*\file n32g003_dbg.h +*\*\author Nations +*\*\version v1.0.0 +*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. +**/ + +#ifndef __N32G003_DBG_H__ +#define __N32G003_DBG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32g003.h" + + +void UCID_Get(uint8_t *UCIDbuf); +void UID_Get(uint8_t *UIDbuf); +void DBGMCU_ID_Get(uint8_t *DBGIDbuf); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32G003_DBG_H__ */ diff --git a/firmware/n32g003_std_periph_driver/inc/n32g003_exti.h b/firmware/n32g003_std_periph_driver/inc/n32g003_exti.h new file mode 100644 index 0000000..1478bd2 --- /dev/null +++ b/firmware/n32g003_std_periph_driver/inc/n32g003_exti.h @@ -0,0 +1,149 @@ +/** +* Copyright (c) 2022, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/*** +*\*\file n32g003_exti.h +*\*\author Nations +*\*\version v1.0.0 +*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. +***/ + +#ifndef __N32G003_EXTI_H +#define __N32G003_EXTI_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "n32g003.h" + +/*** EXTI Structure Definition Start ***/ + +/** EXTI mode enumeration **/ + +typedef enum +{ + EXTI_Mode_Interrupt = 0x00, + EXTI_Mode_Event = 0x04 +} EXTI_ModeType; + + +/** EXTI Trigger enumeration **/ + +typedef enum +{ + EXTI_Trigger_Rising = 0x08, + EXTI_Trigger_Falling = 0x0C, + EXTI_Trigger_Rising_Falling = 0x10 +} EXTI_TriggerType; + + +/** EXTI Init Structure definition **/ + +typedef struct +{ + uint32_t EXTI_Line; /* Specifies the EXTI lines to be enabled or disabled. */ + + EXTI_ModeType EXTI_Mode; /* Specifies the mode for the EXTI lines. */ + + EXTI_TriggerType EXTI_Trigger; /* Specifies the trigger signal active edge for the EXTI lines. */ + + FunctionalState EXTI_LineCmd; /* Specifies the new state of the selected EXTI lines. */ +} EXTI_InitType; + +/*** EXTI Structure Definition End ***/ + + +/*** EXTI Macro Definition Start ***/ + +/** EXTI_Lines **/ +#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */ + +#define EXTI_LINE0 ((uint32_t)0x00001) /* External interrupt line 0 Connected to the PA0 */ +#define EXTI_LINE1 ((uint32_t)0x00002) /* External interrupt line 1 Connected to the PA1 */ +#define EXTI_LINE2 ((uint32_t)0x00004) /* External interrupt line 2 Connected to the PA2 */ +#define EXTI_LINE3 ((uint32_t)0x00008) /* External interrupt line 3 Connected to the PA3 */ +#define EXTI_LINE4 ((uint32_t)0x00010) /* External interrupt line 4 Connected to the PA4 */ +#define EXTI_LINE5 ((uint32_t)0x00020) /* External interrupt line 5 Connected to the PA5 */ +#define EXTI_LINE6 ((uint32_t)0x00040) /* External interrupt line 6 Connected to the PA6 */ +#define EXTI_LINE7 ((uint32_t)0x00080) /* External interrupt line 7 Connected to the PA7 */ +#define EXTI_LINE8 ((uint32_t)0x00100) /* External interrupt line 8 Connected to the PA8 */ +#define EXTI_LINE9 ((uint32_t)0x00200) /* External interrupt line 9 Connected to the PA9 */ +#define EXTI_LINE10 ((uint32_t)0x00400) /* External interrupt line 10 Connected to the PA10 */ +#define EXTI_LINE11 ((uint32_t)0x00800) /* External interrupt line 11 Connected to the PA11 */ +#define EXTI_LINE12 ((uint32_t)0x01000) /* External interrupt line 12 Connected to the PA12 */ +#define EXTI_LINE13 ((uint32_t)0x02000) /* External interrupt line 13 Connected to the PA13 */ +#define EXTI_LINE14 ((uint32_t)0x04000) /* External interrupt line 14 Connected to the PA14 */ +#define EXTI_LINE15 ((uint32_t)0x08000) /* External interrupt line 15 Connected to the PA15 */ +#define EXTI_LINE16 ((uint32_t)0x10000) /* External interrupt line 16 Connected to the PB0 */ +#define EXTI_LINE17 ((uint32_t)0x20000) /* External interrupt line 17 Connected to the PB1 */ +#define EXTI_LINE18 ((uint32_t)0x40000) /* External interrupt line 18 Connected to the PVD Output */ +#define EXTI_LINE19 ((uint32_t)0x80000) /* External interrupt line 19 Connected to the TIM6 interrupt */ + + +/*** EXTI Macro Definition End ***/ + +/** EXTI Driving Functions Declaration **/ + +void EXTI_Reset(void); +void EXTI_Peripheral_Initializes(EXTI_InitType* EXTI_InitStruct); +void EXTI_Work_Mode_Config(uint32_t exti_line,uint32_t exti_mode); +void EXTI_Trigger_Config(uint32_t exti_line,uint32_t exti_trigger); +void EXTI_LineCmd_Disable(uint32_t exti_line,uint32_t exti_linecmd,uint32_t exti_mode); +void EXTI_Structure_Initializes(EXTI_InitType* EXTI_InitStruct); +void EXTI_Software_Interrupt_Trigger(uint32_t exti_line); +FlagStatus EXTI_Flag_Status_Get(uint32_t exti_line); +void EXTI_Flag_Status_Clear(uint32_t exti_line); +ITStatus EXTI_Interrupt_Status_Get(uint32_t exti_line); +void EXTI_Interrupt_Status_Clear(uint32_t exti_line); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32G003_EXTI_H__ */ + diff --git a/firmware/n32g003_std_periph_driver/inc/n32g003_flash.h b/firmware/n32g003_std_periph_driver/inc/n32g003_flash.h new file mode 100644 index 0000000..b9f7eef --- /dev/null +++ b/firmware/n32g003_std_periph_driver/inc/n32g003_flash.h @@ -0,0 +1,265 @@ +/** +* Copyright (c) 2022, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** +*\*\file n32g003_flash.h +*\*\author Nations +*\*\version v1.0.0 +*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. +**/ +#ifndef __N32G003_FLASH_H +#define __N32G003_FLASH_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "n32g003.h" + +/** FLASH Status **/ +typedef enum +{ + FLASH_BUSY = 1, + FLASH_ERR_PG, + FLASH_ERR_WRP, + FLASH_EOP, + FLASH_ERR_RDP2, + FLASH_ERR_ADD, + FLASH_TIMEOUT +}FLASH_STS; + +/** Flash Access Control Register bits **/ +#define FLASH_PRFTBS_MSK ((uint32_t)FLASH_AC_PRFTBFSTS) +/** Prefetch_Buffer_Enable_Disable **/ +#define FLASH_PREFETCHBUF_EN ((uint32_t)FLASH_AC_PRFTBFEN) /* FLASH Prefetch Buffer Enable */ +#define FLASH_PREFETCHBUF_DIS (~((uint32_t)FLASH_AC_PRFTBFEN)) /* FLASH Prefetch Buffer Disable */ + +/** Flash_Latency **/ +#define FLASH_LATENCY_0 ((uint32_t)FLASH_AC_LATENCY_0) /* FLASH Zero Latency cycle */ +#define FLASH_LATENCY_1 ((uint32_t)FLASH_AC_LATENCY_1) /* FLASH One Latency cycle */ +#define FLASH_LATENCY_MASK ((uint32_t)FLASH_AC_LATENCY) + +/** FLASH Keys **/ +#define FLASH_KEY1 ((uint32_t)0x45670123) +#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) + +/** Flash Control Register bits **/ +#define FLASH_CTRL_SET_PG ((uint32_t)FLASH_CTRL_PG) +#define FLASH_CTRL_RESET_PG (~((uint32_t)FLASH_CTRL_PG)) +#define FLASH_CTRL_SET_PER ((uint32_t)FLASH_CTRL_PER) +#define FLASH_CTRL_RESET_PER (~((uint32_t)FLASH_CTRL_PER)) +#define FLASH_CTRL_SET_MER ((uint32_t)FLASH_CTRL_MER) +#define FLASH_CTRL_RESET_MER (~((uint32_t)FLASH_CTRL_MER)) +#define FLASH_CTRL_SET_OPTPG ((uint32_t)FLASH_CTRL_OPTPG) +#define FLASH_CTRL_RESET_OPTPG (~((uint32_t)FLASH_CTRL_OPTPG)) +#define FLASH_CTRL_SET_OPTER ((uint32_t)FLASH_CTRL_OPTER) +#define FLASH_CTRL_RESET_OPTER (~((uint32_t)FLASH_CTRL_OPTER)) +#define FLASH_CTRL_SET_MMER ((uint32_t)FLASH_CTRL_MMER) +#define FLASH_CTRL_RESET_MMER (~((uint32_t)FLASH_CTRL_MMER)) +#define FLASH_CTRL_SET_START ((uint32_t)FLASH_CTRL_START) +#define FLASH_CTRL_SET_LOCK ((uint32_t)FLASH_CTRL_LOCK) +#define FLASH_CTRL_SET_OPTWE ((uint32_t)FLASH_CTRL_OPTWRE) + +/** Option byte **/ +#define FLASH_L1_RDP_KEY ((uint32_t)0xFFFF00A5) +#define FLASH_L2_RDP_KEY ((uint32_t)0xFFFF33CC) +#define FLASH_OB_DATA0_MASK (FLASH_OB_DATA0_MSK) +#define FLASH_OB_DATA1_MASK (FLASH_OB_DATA1_MSK) + + +/** OB Register related definition**/ +#define FLASH_USER_MASK (FLASH_USER_USER) +#define FLASH_RDP1_MASK (FLASH_RDP_RDP1) +#define FLASH_RDP2_MASK ((uint32_t)0xFF00FFFF) +#define FLASH_FLAG_OBERR (FLASH_OB_OBERR) + + +/** FLASH Mask **/ +#define FLASH_RDPRTL1_MSK ((uint32_t)FLASH_OB_RDPRT1) +#define FLASH_RDPRTL2_MSK ((uint32_t)FLASH_OB_RDPRT2) +#define FLASH_OB_USER_MSK ((uint32_t)FLASH_OB_USER) + +/** Option_Bytes_RDPx **/ +#define FLASH_OB_RDP1_ENABLE ((uint8_t)0x00) /* Enable RDP1 */ +#define FLASH_OB_RDP1_DISABLE ((uint8_t)0xA5) /* DISABLE RDP1 */ + +#define FLASH_OB_RDP2_ENABLE ((uint8_t)0xCC) /* Enable RDP2 */ +#define FLASH_OB_RDP2_DISABLE ((uint8_t)0x00) /* Disable RDP2 */ + +/** Option_Bytes_IWatchdog **/ +#define FLASH_OB_IWDG_SW ((uint16_t)0x0001) /* Software IWDG selected */ +#define FLASH_OB_IWDG_HW ((uint16_t)0x0000) /* Hardware IWDG selected */ + +/** Option_Bytes_nRST_STOP **/ +#define FLASH_OB_STOP_NORST ((uint16_t)0x0002) /* No reset generated when entering in STOP */ +#define FLASH_OB_STOP_RST ((uint16_t)0x0000) /* Reset generated when entering in STOP */ + +/** Option_Bytes_nRST_PD **/ +#define FLASH_OB_PD_NORST ((uint16_t)0x0004) /* No reset generated when entering in PD */ +#define FLASH_OB_PD_RST ((uint16_t)0x0000) /* Reset generated when entering in PD */ + +/** Option_Bytes_LOCK_BOOT **/ +#define FLASH_OB_LOCK_BOOT ((uint16_t)0x0008) /* First 3KB FLASH LOCK*/ +#define FLASH_OB_NOLOCK_BOOT ((uint16_t)0x0000) /* First 3KB FLASH NOLOCK */ + +/** Option_Bytes_PA0_IO **/ +#define FLASH_OB_PA0_IO ((uint16_t)0x0000) /* PA0 is general pin */ +#define FLASH_OB_PA0_NRST ((uint16_t)0x0010) /* PA0 is RESET pin */ + +/** Option_Bytes_USER_LVREN **/ +#define FLASH_OB_USER_LVR_ENABLE ((uint16_t)0x0000) /* LVR enable */ +#define FLASH_OB_USER_LVR_DISABLE ((uint16_t)0x0010) /* LVR disable */ + +/** Option_Bytes_USER_LVRFIL **/ +#define FLASH_OB_USER_LVRFIL_ENABLE ((uint16_t)0x0000) /* LVR filter enable */ +#define FLASH_OB_USER_LVRFIL_DISABLE ((uint16_t)0x0020) /* LVR filter disable */ + +/** Option_Bytes_USER_LVRFIL **/ +#define FLASH_OB_USER_LVRRST_ENABLE ((uint16_t)0x0000) /* LVR reset enable */ +#define FLASH_OB_USER_LVRRST_DISABLE ((uint16_t)0x0040) /* LVR reset disable */ + + +/** FLASH USER Mask **/ +#define FLASH_USER_LVRCNT_MSK ((uint32_t)FLASH_USER_LVRCNT) +#define FLASH_USER_LVRLS_MSK ((uint32_t)FLASH_USER_LVRLS) +#define FLASH_USER_POR_DELAY_MSK ((uint32_t)FLASH_USER_POR_DELAY) + + +#define FLASH_USER_RDP_OFFSET (REG_BIT16_OFFSET) +#define FLASH_OB_TO_USER_OFFSET (REG_BIT14_OFFSET) +#define FLASH_OB_OFFSET (REG_BIT2_OFFSET) +#define FLASH_DATA0_DATA1_OFFSET (REG_BIT16_OFFSET) +#define FLASH_USER2_USER3_OFFSET (REG_BIT16_OFFSET) +#define FLASH_OB_DATA0_OFFSET (REG_BIT10_OFFSET) +#define FLASH_OB_DATA1_OFFSET (REG_BIT18_OFFSET) +#define FLASH_USER3_OFFSET (REG_BIT8_OFFSET) +#define FLASH_USER4_OFFSET (REG_BIT16_OFFSET) + + +/** Delay definition **/ +#define ERASE_TIMEOUT ((uint32_t)0x000B0000) +#define PROGRAM_TIMEOUT ((uint32_t)0x00002000) + +#define FLASH_WORD_LENGTH ((uint32_t)0x00000003) + + +/** FLASH_Interrupts **/ +#define FLASH_INT_ERROR ((uint32_t)FLASH_CTRL_ERRITE) /* PGERR WRPERR ERROR error interrupt source */ +#define FLASH_INT_EOP ((uint32_t)FLASH_CTRL_EOPITE) /* End of FLASH Operation Interrupt source */ + +/** FLASH_Flags **/ +#define FLASH_FLAG_BUSY ((uint32_t)FLASH_STS_BUSY) /* FLASH Busy flag */ +#define FLASH_FLAG_PGERR ((uint32_t)FLASH_STS_PGERR) /* FLASH Program error flag */ +#define FLASH_FLAG_WRPERR ((uint32_t)FLASH_STS_WRPERR) /* FLASH Write protected error flag */ +#define FLASH_FLAG_EOP ((uint32_t)FLASH_STS_EOP) /* FLASH End of Operation flag */ +#define FLASH_FLAG_SPERR ((uint32_t)FLASH_STS_SPRERR) /* FLASH Special Pattern Read error */ +#define FLASH_FLAG_CFGERR ((uint32_t)FLASH_STS_CFGERR) /* FLASH Configuration registers error when checking */ + +/** FLASH_STS_CLRFLAG **/ +#define FLASH_STS_CLRFLAG (FLASH_FLAG_PGERR | FLASH_FLAG_WRPERR | FLASH_FLAG_EOP) + + +/** FLASH_VTOR_CLRFLAG **/ +#define FLASH_VTOR_ENABLE ((uint32_t)FLASH_VTOR_EN) /* FLASH Busy flag */ +#define FLASH_VTOR_DISABLE ((uint32_t)0x00000000) /* FLASH Busy flag */ + +/** Delay definition **/ +#define ERASE_TIMEOUT ((uint32_t)0x000B0000) +#define PROGRAM_TIMEOUT ((uint32_t)0x00002000) + +#define FLASH_WORD_LENGTH ((uint32_t)0x00000003) + + + +/** Functions used for N32G003 devices **/ +void FLASH_Latency_Set(uint32_t flash_latency); +uint8_t FLASH_Latency_Get(void); +void FLASH_Prefetch_Buffer_Enable(void); +void FLASH_Prefetch_Buffer_Disable(void); +void FLASH_Unlock(void); +void FLASH_Lock(void); +void Option_Bytes_Unlock(void); +void Option_Bytes_Lock(void); +FlagStatus Option_Bytes_Lock_Status_Get(void); +FLASH_STS FLASH_One_Page_Erase(uint32_t page_address); +FLASH_STS FLASH_Mass_Erase(void); +FLASH_STS FLASH_48Page_Mass_Erase(void); +FLASH_STS FLASH_Word_Program(uint32_t address, uint32_t data); +FLASH_STS FLASH_Option_Bytes_Erase(void); +FLASH_STS FLASH_Option_Bytes_User_RDP1_Program(uint8_t option_byte_rdp1, uint16_t option_byte_iwdg, \ + uint16_t option_byte_stop, uint16_t option_byte_PD, \ + uint16_t option_byte_lock_boot, uint16_t option_byte_PA0_NRST); +FLASH_STS FLASH_Option_Bytes_DATA_Program(uint8_t option_byte_data0,uint8_t option_byte_data1); +FLASH_STS FLASH_Option_Bytes_User2_User3_Program(uint8_t option_byte_user2,uint8_t option_byte_LVR_cnt, \ + uint8_t option_byte_LVR,uint8_t option_byte_LVR_filter,uint8_t option_byte_LVR_reset); +FLASH_STS FLASH_Option_Bytes_User4_RDP2_Program(uint8_t option_byte_rdp2,uint8_t option_byte_user4); +FLASH_STS FLASH_Read_Out_Protection_L1_Enable(void); +FLASH_STS FLASH_Read_Out_Protection_L1_Disable(void); +FLASH_STS FLASH_Read_Out_Protection_L2_Enable(void); +FlagStatus FLASH_Option_Bytes_User_Get(uint32_t option_byte_bit); +uint32_t FLASH_Option_Bytes_User2_Get(void); +uint32_t FLASH_User_LVRLS_Get(void); +FlagStatus FLASH_Option_Bytes_User3_Get(uint32_t option_byte_bit); +uint32_t FLASH_Option_Bytes_User4_Get(void); +FlagStatus FLASH_Read_Out_Protection_Status_Get(void); +FlagStatus FLASH_Read_Out_Protection_L2_Status_Get(void); +FlagStatus FLASH_Prefetch_Buffer_Status_Get(void); +void FLASH_Interrupt_Enable(uint32_t flash_interrupts); +void FLASH_Interrupt_Disable(uint32_t flash_interrupts); +FlagStatus FLASH_Flag_Status_Get(uint32_t flash_flag); +FlagStatus FLASH_Option_Bytes_Flag_Get(uint32_t flash_flag); +void FLASH_Flag_Status_Clear(uint32_t flash_flag); +FLASH_STS FLASH_Status_Get(void); +FLASH_STS FLASH_Last_Operation_Wait(uint32_t timeout); +void FLASH_VTOR_Address_Set(uint32_t VTOR_address,uint32_t VTOR_cmd); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32G003_FLASH_H */ + diff --git a/firmware/n32g003_std_periph_driver/inc/n32g003_gpio.h b/firmware/n32g003_std_periph_driver/inc/n32g003_gpio.h new file mode 100644 index 0000000..9e590a9 --- /dev/null +++ b/firmware/n32g003_std_periph_driver/inc/n32g003_gpio.h @@ -0,0 +1,321 @@ +/** +* Copyright (c) 2022, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** +*\*\file n32g003_gpio.h +*\*\author Nations +*\*\version v1.0.0 +*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. +**/ + +#ifndef __N32G003_GPIO_H__ +#define __N32G003_GPIO_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32g003.h" + + +#define GPIOA_POSITION1 (8U) +#define GPIOA_POSITION2 (9U) + +#define GPIO_AF_MODE ((uint32_t)GPIO_PMODE0_2) +#define GPIO_ANALOG_MODE ((uint32_t)GPIO_PMODE0_Msk) +#define GPIO_PU_MODE ((uint32_t)GPIO_PUPD0_1) +#define GPIO_PD_MODE ((uint32_t)GPIO_PUPD0_2) +#define GPIO_SR_SLOW (GPIO_SR_SR0) +#define GPIO_LOW_DRIVER (GPIO_DS_DS0) + +#define GPIO_OUTPUT_TYPE_MASK ((uint32_t)0x00000010) +#define GPIO_SET_PMODE_MASK ((uint32_t)0x00000003) +#define GPIO_AF_MASK ((uint32_t)0x0000000F) +#define GPIO_PMODE_MASK ((uint32_t)GPIO_PMODE0_Msk) +#define GPIO_PUPD_MASK ((uint32_t)GPIO_PUPD0_Msk) +#define GPIO_POTYPE_MASK (GPIO_POTYPE_POT0) +#define GPIO_SR_MASK (GPIO_SR_SR0) +#define GPIO_DS_MASK (GPIO_DS_DS0) +#define GPIO_PLOCKK_MASK (GPIO_PLOCK_PLOCKK) +#define AF_SELECTION_MASK (0x08) +#define AF_WRITE_POSITION_MASK (0x07U) +#define IO_POSITION_MASK (1U) + +#define MULTIPLIER_FACTOR_2 (2U) +#define MULTIPLIER_FACTOR_4 (4U) + +#define SHIFT_POTYPE (REG_BIT4_OFFSET) +#define SHIFT_PBSC_HIGH16 (REG_BIT16_OFFSET) + +#define GPIO_GET_PERIPH(INDEX) (((INDEX)==((uint8_t)0x00))? GPIOA : GPIOB ) + +/** + *\*\name GPIO_ModeType. + *\*\fun GPIO mode definition. + *\*\ Values convention: 0x00YZ + *\*\ - Y : Output type (Push Pull or Open Drain) + *\*\ - Z : IO Direction mode (Input, Output, Alternate or Analog) + */ +#define GPIO_MODE_INPUT ((uint32_t)0x00000000U) /* Input Floating Mode */ +#define GPIO_MODE_OUT_PP ((uint32_t)0x00000001U) /* Output Push Pull Mode */ +#define GPIO_MODE_OUT_OD ((uint32_t)0x00000011U) /* Output Open Drain Mode */ +#define GPIO_MODE_AF_PP ((uint32_t)0x00000002U) /* Alternate Function Push Pull Mode */ +#define GPIO_MODE_AF_OD ((uint32_t)0x00000012U) /* Alternate Function Open Drain Mode */ +#define GPIO_MODE_ANALOG ((uint32_t)0x00000003U) /* Analog Mode */ + +/** GPIO Pull-Up or Pull-Down Activation **/ +#define GPIO_NO_PULL ((uint32_t)GPIO_PUPD0_0) /* No Pull-up or Pull-down activation */ +#define GPIO_PULL_UP ((uint32_t)GPIO_PUPD0_1) /* Pull-up activation */ +#define GPIO_PULL_DOWN ((uint32_t)GPIO_PUPD0_2) /* Pull-down activation */ + +/** slew rate config **/ +#define GPIO_SLEW_RATE_FAST ((uint32_t)0x00000000U) +#define GPIO_SLEW_RATE_SLOW ((uint32_t)0x00000001U) + +/** driver strength config **/ +#define GPIO_HIGH_DREIVE ((uint32_t)0x00000000U) +#define GPIO_LOW_DREIVE ((uint32_t)0x00000001U) + + +/** GPIO Init Structure Definition **/ +typedef struct +{ + uint32_t Pin; /* Specifies the GPIO pins to be configured. */ + + uint32_t GPIO_Mode; /* Specifies the operating mode for the selected pins. */ + + uint32_t GPIO_Pull; /* Specifies the Pull-up or Pull-Down activation for the selected pins. */ + + uint32_t GPIO_Slew_Rate; /* Specify the reverse speed for the selected pins. */ + + uint32_t GPIO_Current; /* Driving drive capability of the select pins. */ + + uint32_t GPIO_Alternate; /* Peripheral to be connected to the selected pins. */ +}GPIO_InitType; + +/** Bit_SET and Bit_RESET enumeration **/ +typedef enum +{ + PIN_RESET = 0, + PIN_SET +}Bit_CommandType; + +/** GPIO_pins_define **/ +#define GPIO_PIN_0 ((uint16_t)0x0001U) /* Pin 0 selected */ +#define GPIO_PIN_1 ((uint16_t)0x0002U) /* Pin 1 selected */ +#define GPIO_PIN_2 ((uint16_t)0x0004U) /* Pin 2 selected */ +#define GPIO_PIN_3 ((uint16_t)0x0008U) /* Pin 3 selected */ +#define GPIO_PIN_4 ((uint16_t)0x0010U) /* Pin 4 selected */ +#define GPIO_PIN_5 ((uint16_t)0x0020U) /* Pin 5 selected */ +#define GPIO_PIN_6 ((uint16_t)0x0040U) /* Pin 6 selected */ +#define GPIO_PIN_7 ((uint16_t)0x0080U) /* Pin 7 selected */ +#define GPIO_PIN_8 ((uint16_t)0x0100U) /* Pin 8 selected */ +#define GPIO_PIN_9 ((uint16_t)0x0200U) /* Pin 9 selected */ +#define GPIO_PIN_10 ((uint16_t)0x0400U) /* Pin 10 selected */ +#define GPIO_PIN_11 ((uint16_t)0x0800U) /* Pin 11 selected */ +#define GPIO_PIN_12 ((uint16_t)0x1000U) /* Pin 12 selected */ +#define GPIO_PIN_13 ((uint16_t)0x2000U) /* Pin 13 selected */ +#define GPIO_PIN_14 ((uint16_t)0x4000U) /* Pin 14 selected */ +#define GPIO_PIN_15 ((uint16_t)0x8000U) /* Pin 15 selected */ +#define GPIO_PIN_ALL ((uint16_t)0xFFFFU) /* All pins selected */ + +/** GPIO Port Sources **/ +#define GPIOA_PORT_SOURCE ((uint8_t)0x00) +#define GPIOB_PORT_SOURCE ((uint8_t)0x01) + +/** GPIO Pin Sources **/ +#define GPIO_PIN_SOURCE0 ((uint8_t)0x00) +#define GPIO_PIN_SOURCE1 ((uint8_t)0x01) +#define GPIO_PIN_SOURCE2 ((uint8_t)0x02) +#define GPIO_PIN_SOURCE3 ((uint8_t)0x03) +#define GPIO_PIN_SOURCE4 ((uint8_t)0x04) +#define GPIO_PIN_SOURCE5 ((uint8_t)0x05) +#define GPIO_PIN_SOURCE6 ((uint8_t)0x06) +#define GPIO_PIN_SOURCE7 ((uint8_t)0x07) +#define GPIO_PIN_SOURCE8 ((uint8_t)0x08) +#define GPIO_PIN_SOURCE9 ((uint8_t)0x09) +#define GPIO_PIN_SOURCE10 ((uint8_t)0x0A) +#define GPIO_PIN_SOURCE11 ((uint8_t)0x0B) +#define GPIO_PIN_SOURCE12 ((uint8_t)0x0C) +#define GPIO_PIN_SOURCE13 ((uint8_t)0x0D) +#define GPIO_PIN_SOURCE14 ((uint8_t)0x0E) +#define GPIO_PIN_SOURCE15 ((uint8_t)0x0F) + + +/** EXTI line and GPIO sources **/ +#define AFIO_ADC_TRIG_PA0 ((uint8_t)0x00) /* PA0 */ +#define AFIO_ADC_TRIG_PA1 ((uint8_t)0x01) /* PA1 */ +#define AFIO_ADC_TRIG_PA2 ((uint8_t)0x02) /* PA2 */ +#define AFIO_ADC_TRIG_PA3 ((uint8_t)0x03) /* PA3 */ +#define AFIO_ADC_TRIG_PA4 ((uint8_t)0x04) /* PA4 */ +#define AFIO_ADC_TRIG_PA5 ((uint8_t)0x05) /* PA5 */ +#define AFIO_ADC_TRIG_PA6 ((uint8_t)0x06) /* PA6 */ +#define AFIO_ADC_TRIG_PA7 ((uint8_t)0x07) /* PA7 */ +#define AFIO_ADC_TRIG_PA8 ((uint8_t)0x08) /* PA8 */ +#define AFIO_ADC_TRIG_PA9 ((uint8_t)0x09) /* PA9 */ +#define AFIO_ADC_TRIG_PA10 ((uint8_t)0x0A) /* PA10 */ +#define AFIO_ADC_TRIG_PA11 ((uint8_t)0x0B) /* PA11 */ +#define AFIO_ADC_TRIG_PA12 ((uint8_t)0x0C) /* PA12 */ +#define AFIO_ADC_TRIG_PA13 ((uint8_t)0x0D) /* PA13 */ +#define AFIO_ADC_TRIG_PA14 ((uint8_t)0x0E) /* PA14 */ +#define AFIO_ADC_TRIG_PA15 ((uint8_t)0x0F) /* PA15 */ +#define AFIO_ADC_TRIG_PB0 ((uint8_t)0x10) /* PB0 */ +#define AFIO_ADC_TRIG_PB1 ((uint8_t)0x11) /* PB1 */ + + +/** GPIOx_Alternate_function_selection Alternate function selection **/ + +/** Alternate function AF0 **/ +#define ALTERNATE_FUN_0 ((uint8_t)0x00U) +#define GPIO_AF0_SWDIO (ALTERNATE_FUN_0) /* SWDIO Alternate Function mapping */ +#define GPIO_AF0_SWCLK (ALTERNATE_FUN_0) /* SWCLK Alternate Function mapping */ +#define GPIO_AF0_TIM1 (ALTERNATE_FUN_0) /* TIM1 Alternate Function mapping */ +#define GPIO_AF0_TIM3 (ALTERNATE_FUN_0) /* TIM3 Alternate Function mapping */ +#define GPIO_AF0_SPI (ALTERNATE_FUN_0) /* SPI Alternate Function mapping */ + +/** Alternate function AF1 **/ +#define ALTERNATE_FUN_1 ((uint8_t)0x01U) +#define GPIO_AF1_UART2 (ALTERNATE_FUN_1) /* UART2 Alternate Function mapping */ +#define GPIO_AF1_TIM3 (ALTERNATE_FUN_1) /* TIM3 Alternate Function mapping */ + +/** Alternate function AF2 **/ +#define ALTERNATE_FUN_2 ((uint8_t)0x02U) +#define GPIO_AF2_UART1 (ALTERNATE_FUN_2) /* UART1 Alternate Function mapping */ +#define GPIO_AF2_TIM1 (ALTERNATE_FUN_2) /* TIM1 Alternate Function mapping */ +#define GPIO_AF2_TIM3 (ALTERNATE_FUN_2) /* TIM3 Alternate Function mapping */ + + +/** Alternate function AF3 **/ +#define ALTERNATE_FUN_3 ((uint8_t)0x03U) +#define GPIO_AF3_EVENTOUT (ALTERNATE_FUN_3) /* EVENTOUT Alternate Function mapping */ +#define GPIO_AF3_TIM1 (ALTERNATE_FUN_3) /* TIM1 Alternate Function mapping */ +#define GPIO_AF3_COMP (ALTERNATE_FUN_3) /* COMP Alternate Function mapping */ + +/** Alternate function AF4 **/ +#define ALTERNATE_FUN_4 ((uint8_t)0x04U) +#define GPIO_AF4_TIM1 (ALTERNATE_FUN_4) /* TIM1 Alternate Function mapping */ + +/** Alternate function AF5 **/ +#define ALTERNATE_FUN_5 ((uint8_t)0x05U) +#define GPIO_AF5_UART1 (ALTERNATE_FUN_5) /* UART1 Alternate Function mapping */ +#define GPIO_AF5_TIM1 (ALTERNATE_FUN_5) /* TIM1 Alternate Function mapping */ +#define GPIO_AF5_SPI (ALTERNATE_FUN_5) /* SPI Alternate Function mapping */ + +/** Alternate function AF6 **/ +#define ALTERNATE_FUN_6 ((uint8_t)0x06U) +#define GPIO_AF6_SPI (ALTERNATE_FUN_6) /* SPI Alternate Function mapping */ +#define GPIO_AF6_I2C (ALTERNATE_FUN_6) /* I2C Alternate Function mapping */ +#define GPIO_AF6_TIM3 (ALTERNATE_FUN_6) /* TIM3 Alternate Function mapping */ +#define GPIO_AF6_UART2 (ALTERNATE_FUN_6) /* UART2 Alternate Function mapping */ +#define GPIO_AF6_MCO (ALTERNATE_FUN_6) /* MCO Alternate Function mapping */ + +/** Alternate function AF7 **/ +#define ALTERNATE_FUN_7 ((uint8_t)0x07U) +#define GPIO_AF7_BEEPER (ALTERNATE_FUN_7) /* BEEPER Alternate Function mapping */ + +/** Alternate function AF8 **/ +#define ALTERNATE_FUN_8 ((uint8_t)0x08U) +#define GPIO_AF8_UART2 (ALTERNATE_FUN_8) /* UART2 Alternate Function mapping */ + +/** Alternate function AF15 **/ +#define ALTERNATE_FUN_15 ((uint8_t)0x0FU) /* NON Alternate Function mapping */ + +#define GPIO_NO_AF (ALTERNATE_FUN_15) + +/** SPI mode definition in AFIO register **/ +#define AFIO_SPI_NSS ((uint32_t)AFIO_CFG_SPI_NSS) + +#define AFIO_SPI_NSS_HIGH_IMPEDANCE (0x0UL) +#define AFIO_SPI_NSS_High_LEVEL (0x1UL) + +/** TIM3_CH2 internal remap definition in AFIO register **/ +#define AFIO_TIM3CH2_MAP ((uint32_t)AFIO_CFG_TIM3CH2_MAP) + +#define TIM3CH2_TO_PORT (0x0UL) +#define TIM3CH2_TO_LSI (0x1UL) + + + +/** GPIO_Exported_Functions **/ + +void GPIO_Reset(GPIO_Module* GPIOx); +void GPIO_Alternate_Function_Reset(void); +void GPIOA_Pin_Reset(uint16_t pin); +void GPIOB_Pin_Reset(uint16_t pin); + +void GPIO_Alternate_Set(GPIO_Module* GPIOx, uint32_t alternate, uint32_t position); +void GPIO_Mode_Set(GPIO_Module* GPIOx, uint32_t mode, uint32_t position); +void GPIO_Pull_Set(GPIO_Module* GPIOx, uint32_t pull, uint32_t position); +void GPIO_SlewRate_Set(GPIO_Module* GPIOx, uint32_t slew_rate, uint32_t position); +void GPIO_Driver_Set(GPIO_Module* GPIOx, uint32_t current, uint32_t position); +void GPIO_Peripheral_Initialize(GPIO_Module* GPIOx, GPIO_InitType* GPIO_InitStructure); +void GPIO_Structure_Initialize(GPIO_InitType* GPIO_InitStruct); + +uint8_t GPIO_Input_Pin_Data_Get(GPIO_Module* GPIOx, uint16_t pin); +uint16_t GPIO_Input_Data_Get(GPIO_Module* GPIOx); +uint8_t GPIO_Output_Pin_Data_Get(GPIO_Module* GPIOx, uint16_t pin); +uint16_t GPIO_Output_Data_Get(GPIO_Module* GPIOx); +void GPIO_Pins_Set(GPIO_Module* GPIOx, uint16_t pin); +void GPIO_Pins_Reset(GPIO_Module* GPIOx, uint16_t pin); +void GPIO_PBSC_Pins_Reset(GPIO_Module* GPIOx, uint16_t pin); +void GPIO_PBC_Pins_Reset(GPIO_Module* GPIOx, uint16_t pin); +void GPIO_Write(GPIO_Module* GPIOx, uint16_t data_value); +void GPIO_Pin_Toggle(GPIO_Module* GPIOx, uint16_t pin); +void GPIO_Pin_Lock_Set(GPIO_Module* GPIOx, uint16_t pin); + +void GPIO_Pin_Remap_Set(uint8_t port_source, uint8_t pin_source, uint32_t alternate_function); +void AFIO_ADC_External_Trigger_Set(uint8_t ADC_trigger); +void AFIO_SPI_NSS_Mode_Set(uint32_t SPI_NSS_mode); +void AFIO_TIM3CH2_Remap(uint32_t TIM3CH2_remap); + + +#ifdef __cplusplus +} +#endif + +#endif /* __N32G003_GPIO_H__ */ + diff --git a/firmware/n32g003_std_periph_driver/inc/n32g003_i2c.h b/firmware/n32g003_std_periph_driver/inc/n32g003_i2c.h new file mode 100644 index 0000000..f2acc67 --- /dev/null +++ b/firmware/n32g003_std_periph_driver/inc/n32g003_i2c.h @@ -0,0 +1,544 @@ +/** +* Copyright (c) 2022, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** +*\*\file n32g003_i2c.h +*\*\author Nations +*\*\version v1.0.0 +*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. +**/ + +#ifndef __N32G003_I2C_H_ +#define __N32G003_I2C_H_ + +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "n32g003.h" + +/** N32G003_StdPeriph_Driver + * + */ + +/** I2C Init structure definition **/ + +typedef struct +{ + uint32_t ClkSpeed; /* Specifies the clock frequency. */ + + uint16_t DutyCycle; /* Specifies the I2C duty cycle. */ + + uint16_t OwnAddr1; /* Specifies the first device own address. */ + + uint16_t AckEnable; /* Enables or disables the acknowledgement. */ + + uint16_t AddrMode; /* Specifies if 7-bit or 10-bit address is acknowledged. */ +} I2C_InitType; + + + +#define APB_FREQ_MAX_VALUE (48) /*48M*/ +#define CLK_SPEED_100K (100000) +#define CLK_SPEED_400K (400000) +#define CLK_SPEED_1M (1000000) +#define SM_CLKCTRL_LOW_LIMIT (0x04) +#define FM_CLKCTRL_LOW_LIMIT (0x01) +#define SM_TRISE_100K (1000) /*1000ns*/ +#define FM_TRISE_400K (300) /*300ns*/ +#define FM_TRISE_1M (120) /*120ns*/ + +/** Register shift macro definition **/ +#define RCC_FLAG_STS2_OFFSET (REG_BIT16_OFFSET) +#define RCC_FLAG_GET_OFFSET (REG_BIT28_OFFSET) + +#define I2C_REG_BIT_MASK ((uint16_t)0x0000) + +/* I2C EN mask */ +#define I2C_EN_SET (I2C_CTRL1_EN) +#define I2C_EN_RESET (~I2C_CTRL1_EN) + +/* I2C START mask */ +#define I2C_START_SET (I2C_CTRL1_STARTGEN) +#define I2C_START_RESET (~I2C_CTRL1_STARTGEN) + +/* I2C STOP mask */ +#define I2C_STOP_SET (I2C_CTRL1_STOPGEN) +#define I2C_STOP_RESET (~I2C_CTRL1_STOPGEN) + +/* I2C ACK mask */ +#define I2C_ACK_SET (I2C_CTRL1_ACKEN) +#define I2C_ACK_RESET (~I2C_CTRL1_ACKEN) + +/* I2C ENGC mask */ +#define I2C_GCEN_SET (I2C_CTRL1_GCEN) +#define I2C_GCEN_RESET (~I2C_CTRL1_GCEN) + +/* I2C SWRST mask */ +#define I2C_SWRESET_SET (I2C_CTRL1_SWRESET) +#define I2C_SWRESET_RESET (~I2C_CTRL1_SWRESET) + +/* I2C PEC mask */ +#define I2C_PEC_SET (I2C_CTRL1_PEC) +#define I2C_PEC_RESET (~I2C_CTRL1_PEC) + +/* I2C ENPEC mask */ +#define I2C_PECEN_SET (I2C_CTRL1_PECEN) +#define I2C_PECEN_RESET (~I2C_CTRL1_PECEN) + +/* I2C NOSTRETCH mask */ +#define I2C_NOEXTEND_SET (I2C_CTRL1_NOEXTEND) +#define I2C_NOEXTEND_RESET (~I2C_CTRL1_NOEXTEND) + +/* I2C registers Masks */ +#define I2C_ACKEN_CLR_MASK (~(I2C_CTRL1_ACKEN)) +#define I2C_ADDRMODE_CLR_MASK (~(I2C_OADDR1_ADDRMODE)) +#define I2C_OADDR_CLR_MASK (~(I2C_OADDR1_ADDR0 | I2C_OADDR1_ADDR1_7 | I2C_OADDR1_ADDR8_9)) + +/* I2C FREQ mask */ +#define I2C_CLKFREQ_RESET (~I2C_CTRL2_CLKFREQ) + +/* I2C ADD0 mask */ +#define I2C_ADDR0_SET (I2C_OADDR1_ADDR0) +#define I2C_ADDR0_RESET (~I2C_OADDR1_ADDR0) + + +/* I2C ENDUAL mask */ +#define I2C_DUALEN_SET (((uint16_t)I2C_OADDR2_DUALEN)) +#define I2C_DUALEN_RESET (~((uint16_t)I2C_OADDR2_DUALEN)) + +/* I2C ADD2 mask */ +#define I2C_ADDR2_SET ((uint16_t)I2C_OADDR2_ADDR2) +#define I2C_ADDR2_RESET (~((uint16_t)I2C_OADDR2_ADDR2)) + +/* I2C F/S mask */ +#define I2C_FSMODE_SET (I2C_CLKCTRL_FSMODE) + +/* I2C CHCFG mask */ +#define I2C_CLKCTRL_SET (I2C_CLKCTRL_CLKCTRL) + +/* I2C TMRISE mask */ +#define I2C_SDADFW_MASK (~I2C_GFLTRCTRL_SDADFW) +#define I2C_SCLDFW_MASK (~I2C_GFLTRCTRL_SCLDFW) +#define I2C_SDAAFW_MASK (~I2C_GFLTRCTRL_SDAAFW) +#define I2C_SCLAFW_MASK (~I2C_GFLTRCTRL_SCLAFW) + +#define I2C_SDAAFENN_SET (I2C_GFLTRCTRL_SDAAFENN) +#define I2C_SDAAFENN_RESET (~I2C_GFLTRCTRL_SDAAFENN) + +#define I2C_SCLAFENN_SET (I2C_GFLTRCTRL_SCLAFENN) +#define I2C_SCLAFENN_RESET (~I2C_GFLTRCTRL_SCLAFENN) + +#define I2C_TMRISE_MASK (I2C_TMRISE_TRISE) + + +/* I2C FLAG mask */ +#define I2C_FLAG_Mask ((uint32_t)0x00FFFFFF) + +/* I2C Interrupt Enable mask */ +#define I2C_INTEN_MASK ((uint32_t)0x07000000) + + +/** I2C_duty_cycle **/ +#define I2C_SMDUTYCYCLE_1 (I2C_REG_BIT_MASK) /* I2C standard mode Tlow/Thigh = 1/1 */ +#define I2C_FMDUTYCYCLE_16_9 (I2C_CLKCTRL_DUTY) /* I2C fast mode Tlow/Thigh = 16/9 */ +#define I2C_FMDUTYCYCLE_2 (~I2C_CLKCTRL_DUTY) /* I2C fast mode Tlow/Thigh = 2 */ + +/** I2C_acknowledgement **/ +#define I2C_ACKEN (I2C_CTRL1_ACKEN) +#define I2C_ACKDIS (I2C_REG_BIT_MASK) + +/** I2C_transfer_direction **/ +#define I2C_DIRECTION_SEND ((uint8_t)0x00) +#define I2C_DIRECTION_RECV ((uint8_t)0x01) + +/** I2C_acknowledged_address **/ +/* Bit 14 Should be kept at 1 by software*/ +#define I2C_ADDR_MODE_7BIT (((uint16_t)0x4000) | I2C_REG_BIT_MASK) +#define I2C_ADDR_MODE_10BIT (((uint16_t)0x4000) | I2C_OADDR1_ADDRMODE) + + +/** I2C_registers **/ + +#define I2C_REG_CTRL1 ((uint8_t)0x00) +#define I2C_REG_CTRL2 ((uint8_t)0x04) +#define I2C_REG_OADDR1 ((uint8_t)0x08) +#define I2C_REG_OADDR2 ((uint8_t)0x0C) +#define I2C_REG_DAT ((uint8_t)0x10) +#define I2C_REG_STS1 ((uint8_t)0x14) +#define I2C_REG_STS2 ((uint8_t)0x18) +#define I2C_REG_CLKCTRL ((uint8_t)0x1C) +#define I2C_REG_TMRISE ((uint8_t)0x20) +#define I2C_REG_GFLTRCTRL ((uint8_t)0x24) +#define I2C_REG_BYTENUM ((uint8_t)0x28) + + +/** I2C_PEC_position **/ +#define I2C_PEC_POS_NEXT (I2C_CTRL1_ACKPOS) +#define I2C_PEC_POS_CURRENT (~I2C_CTRL1_ACKPOS) + +/** I2C_NCAK_position **/ +#define I2C_NACK_POS_NEXT (I2C_CTRL1_ACKPOS) +#define I2C_NACK_POS_CURRENT (~I2C_CTRL1_ACKPOS) + +/** I2C_Analog_Filter_Width **/ +#define I2C_ANALOG_FILTER_WIDTH_5NS ((uint16_t)0x0000) +#define I2C_ANALOG_FILTER_WIDTH_15NS (I2C_GFLTRCTRL_SDAAFW_0) +#define I2C_ANALOG_FILTER_WIDTH_25NS (I2C_GFLTRCTRL_SDAAFW_1) +#define I2C_ANALOG_FILTER_WIDTH_35NS (I2C_GFLTRCTRL_SDAAFW_0|I2C_GFLTRCTRL_SDAAFW_1) + +/** I2C_interrupts_definition **/ +#define I2C_INT_BUF (I2C_CTRL2_BUFINTEN) +#define I2C_INT_EVENT (I2C_CTRL2_EVTINTEN) +#define I2C_INT_ERR (I2C_CTRL2_ERRINTEN) + +/* I2C BYTE_NUM_EN mask */ +#define I2C_BYTENUMEN_SET (I2C_BYTENUM_BYTENUMEN) +#define I2C_BYTENUMEN_RESET (~I2C_BYTENUM_BYTENUMEN) + +/* I2C BYTE_NUM byte number mask */ +#define I2C_BYTENUM_MASK (~I2C_BYTENUM_BYTENUM) + +/* I2C master sended status after finishing receiving data bytes */ +#define I2C_BYTENUM_LAST_STOP (~I2C_BYTENUM_RXFSEL) +#define I2C_BYTENUM_LAST_START (I2C_BYTENUM_RXFSEL) + + +/** I2C_interrupts_definition **/ +#define I2C_INT_PECERR (((uint32_t)0x01000000) | ((uint32_t)I2C_STS1_PECERR)) +#define I2C_INT_OVERRUN (((uint32_t)0x01000000) | ((uint32_t)I2C_STS1_OVERRUN)) +#define I2C_INT_ACKFAIL (((uint32_t)0x01000000) | ((uint32_t)I2C_STS1_ACKFAIL)) +#define I2C_INT_ARLOST (((uint32_t)0x01000000) | ((uint32_t)I2C_STS1_ARLOST)) +#define I2C_INT_BUSERR (((uint32_t)0x01000000) | ((uint32_t)I2C_STS1_BUSERR)) +#define I2C_INT_TXDATE (((uint32_t)0x06000000) | ((uint32_t)I2C_STS1_TXDATE)) +#define I2C_INT_RXDATNE (((uint32_t)0x06000000) | ((uint32_t)I2C_STS1_RXDATNE)) +#define I2C_INT_STOPF (((uint32_t)0x02000000) | ((uint32_t)I2C_STS1_STOPF)) +#define I2C_INT_ADDR10F (((uint32_t)0x02000000) | ((uint32_t)I2C_STS1_ADDR10F)) +#define I2C_INT_BYTEF (((uint32_t)0x02000000) | ((uint32_t)I2C_STS1_BSF)) +#define I2C_INT_ADDRF (((uint32_t)0x02000000) | ((uint32_t)I2C_STS1_ADDRF)) +#define I2C_INT_STARTBF (((uint32_t)0x02000000) | ((uint32_t)I2C_STS1_STARTBF)) + +/** I2C_flags_definition **/ + +/** STS2 register flags **/ + +#define I2C_FLAG_DUALFLAG (((uint32_t)I2C_STS2_DUALFLAG)<<16) +#define I2C_FLAG_GCALLADDR (((uint32_t)I2C_STS2_GCALLADDR)<<16) +#define I2C_FLAG_TRF (((uint32_t)I2C_STS2_TRF)<<16) +#define I2C_FLAG_BUSY (((uint32_t)I2C_STS2_BUSY)<<16) +#define I2C_FLAG_MSMODE (((uint32_t)I2C_STS2_MSMODE)<<16) + +/** STS1 register flags **/ + +#define I2C_FLAG_PECERR (((uint32_t)0x10000000) | ((uint32_t)I2C_STS1_PECERR)) +#define I2C_FLAG_OVERRUN (((uint32_t)0x10000000) | ((uint32_t)I2C_STS1_OVERRUN)) +#define I2C_FLAG_ACKFAIL (((uint32_t)0x10000000) | ((uint32_t)I2C_STS1_ACKFAIL)) +#define I2C_FLAG_ARLOST (((uint32_t)0x10000000) | ((uint32_t)I2C_STS1_ARLOST)) +#define I2C_FLAG_BUSERR (((uint32_t)0x10000000) | ((uint32_t)I2C_STS1_BUSERR)) +#define I2C_FLAG_TXDATE (((uint32_t)0x10000000) | ((uint32_t)I2C_STS1_TXDATE)) +#define I2C_FLAG_RXDATNE (((uint32_t)0x10000000) | ((uint32_t)I2C_STS1_RXDATNE)) +#define I2C_FLAG_STOPF (((uint32_t)0x10000000) | ((uint32_t)I2C_STS1_STOPF)) +#define I2C_FLAG_ADDR10F (((uint32_t)0x10000000) | ((uint32_t)I2C_STS1_ADDR10F)) +#define I2C_FLAG_BYTEF (((uint32_t)0x10000000) | ((uint32_t)I2C_STS1_BSF)) +#define I2C_FLAG_ADDRF (((uint32_t)0x10000000) | ((uint32_t)I2C_STS1_ADDRF)) +#define I2C_FLAG_STARTBF (((uint32_t)0x10000000) | ((uint32_t)I2C_STS1_STARTBF)) + + +/** I2C_Events **/ + +/** I2C Master Events (Events grouped in order of communication) **/ +/** +*\*\brief Communication start +*\*\After sending the START condition (I2C_Generate_Start_Enable() function) the master +*\*\has to wait for this event. It means that the Start condition has been correctly +*\*\released on the I2C bus (the bus is free, no other devices is communicating). +**/ + +/* MSMODE */ +#define I2C_ROLE_MASTER (((uint32_t)I2C_STS2_MSMODE)<<16) +/* EV5 */ +/* BUSY, MSMODE and STARTBF flag*/ +#define I2C_EVT_MASTER_MODE_FLAG (((uint32_t)I2C_STS1_STARTBF)\ + |((((uint32_t)I2C_STS2_BUSY)|((uint32_t)I2C_STS2_MSMODE))<<16)) + + +/** +*\*\brief Address Acknowledge +*\*\After checking on EV5 (start condition correctly released on the bus), the +*\*\master sends the address of the slave(s) with which it will communicate +*\*\(I2C_7bit_Addr_Send() function, it also determines the direction of the communication: +*\*\Master transmitter or Receiver). Then the master has to wait that a slave acknowledges +*\*\his address. If an acknowledge is sent on the bus, one of the following events will +*\*\be set: +*\*\ 1) In case of Master Receiver (7-bit addressing): the I2C_EVT_MASTER_RXMODE_FLAG +*\*\ event is set. +*\*\ 2) In case of Master Transmitter (7-bit addressing): the I2C_EVT_MASTER_TXMODE_FLAG +*\*\ is set +*\*\ 3) In case of 10-Bit addressing mode, the master (just after generating the START +*\*\ and checking on EV5) has to send the header of 10-bit addressing mode (I2C_Data_Send() +*\*\ function). Then master should wait on EV9. It means that the 10-bit addressing +*\*\ header has been correctly sent on the bus. Then master should send the second part of +*\*\ the 10-bit address (LSB) using the function I2C_7bit_Addr_Send(). Then master +*\*\ should wait for event EV6. + **/ + +/* --EV6 */ +/* BUSY, MSMODE, ADDRF, TXDATE and TRF flags */ +#define I2C_EVT_MASTER_TXMODE_FLAG (((uint32_t)I2C_STS1_ADDRF)|((uint32_t)I2C_STS1_TXDATE)\ + |((((uint32_t)I2C_STS2_BUSY)|((uint32_t)I2C_STS2_MSMODE)|((uint32_t)I2C_STS2_TRF))<<16)) +/* BUSY, MSMODE and ADDRF flags */ +#define I2C_EVT_MASTER_RXMODE_FLAG (((uint32_t)I2C_STS1_ADDRF)\ + |((((uint32_t)I2C_STS2_BUSY)|((uint32_t)I2C_STS2_MSMODE))<<16)) +/* --EV9 */ +/* BUSY, MSMODE and ADD10RF flags */ +#define I2C_EVT_MASTER_MODE_ADDRESS10_FLAG (((uint32_t)I2C_STS1_ADDR10F)\ + |((((uint32_t)I2C_STS2_BUSY)|((uint32_t)I2C_STS2_MSMODE))<<16)) + +/** +*\*\brief Communication events +*\*\If a communication is established (START condition generated and slave address +*\*\acknowledged) then the master has to check on one of the following events for +*\*\communication procedures: +*\*\1) Master Receiver mode: The master has to wait on the event EV7 then to read +*\*\ the data received from the slave (I2C_Data_Recv() function). +*\*\2) Master Transmitter mode: The master has to send data (I2C_Data_Send() +*\*\ function) then to wait on event EV8 or EV8_2. +*\*\ These two events are similar: +*\*\ - EV8 means that the data has been written in the data register and is +*\*\ being shifted out. +*\*\ - EV8_2 means that the data has been physically shifted out and output +*\*\ on the bus. +*\*\ In most cases, using EV8 is sufficient for the application. +*\*\ Using EV8_2 leads to a slower communication but ensure more reliable test. +*\*\ EV8_2 is also more suitable than EV8 for testing on the last data transmission +*\*\ (before Stop condition generation). +*\*\note In case the user software does not guarantee that this event EV7 is +*\*\ managed before the current byte end of transfer, then user may check on EV7 +*\*\ and BSF flag at the same time (ie. (I2C_EVT_MASTER_DATA_RECVD_FLAG | I2C_FLAG_BYTEF)). +*\*\ In this case the communication may be slower. + **/ + +/* Master RECEIVER mode -----------------------------*/ +/* --EV7 */ +/* BUSY, MSMODE and RXDATNE flags */ +#define I2C_EVT_MASTER_DATA_RECVD_FLAG (((uint32_t)I2C_STS1_RXDATNE)\ + |((((uint32_t)I2C_STS2_BUSY)|((uint32_t)I2C_STS2_MSMODE))<<16)) + +/* EV7x shifter register full */ +/* BUSY, MSMODE, BSF and RXDATNE flags */ +#define I2C_EVT_MASTER_DATA_RECVD_BSF_FLAG (((uint32_t)I2C_STS1_RXDATNE)|((uint32_t)I2C_STS1_BSF)\ + |((((uint32_t)I2C_STS2_BUSY)|((uint32_t)I2C_STS2_MSMODE))<<16)) + +/* Master TRANSMITTER mode --------------------------*/ +/* --EV8 */ +/* TRF, BUSY, MSMODE, TXDATE flags */ +#define I2C_EVT_MASTER_DATA_SENDING (((uint32_t)I2C_STS1_TXDATE)\ + |((((uint32_t)I2C_STS2_BUSY)|((uint32_t)I2C_STS2_MSMODE)|((uint32_t)I2C_STS2_TRF))<<16)) +/* --EV8_2 */ +/* TRF, BUSY, MSMODE, TXDATE and BSF flags */ +#define I2C_EVT_MASTER_DATA_SENDED (((uint32_t)I2C_STS1_BSF)|((uint32_t)I2C_STS1_TXDATE)\ + |((((uint32_t)I2C_STS2_BUSY)|((uint32_t)I2C_STS2_MSMODE)|((uint32_t)I2C_STS2_TRF))<<16)) + +/*======================================== + + I2C Slave Events (Events grouped in order of communication) + ==========================================*/ + +/** +*\*\brief Communication start events +*\*\Wait on one of these events at the start of the communication. It means that +*\*\the I2C peripheral detected a Start condition on the bus (generated by master +*\*\device) followed by the peripheral address. The peripheral generates an ACK +*\*\condition on the bus (if the acknowledge feature is enabled through function +*\*\I2C_ConfigAck()) and the events listed above are set : +*\*\1) In normal case (only one address managed by the slave), when the address +*\*\ sent by the master matches the own address of the peripheral (configured by +*\*\ OwnAddr1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set +*\*\ (where XXX could be TRANSMITTER or RECEIVER). +*\*\2) In case the address sent by the master matches the second address of the +*\*\ peripheral (configured by the function I2C_ConfigOwnAddr2() and enabled +*\*\ by the function I2C_EnableDualAddr()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED +*\*\ (where XXX could be TRANSMITTER or RECEIVER) are set. +*\*\3) In case the address sent by the master is General Call (address 0x00) and +*\*\ if the General Call is enabled for the peripheral (using function I2C_EnableGeneralCall()) +*\*\ the following event is set I2C_EVT_SLAVE_GCALLADDR_MATCHED. + **/ + +/* --EV1 (all the events below are variants of EV1) */ +/* 1) Case of One Single Address managed by the slave */ + /* BUSY and ADDRF flags */ +#define I2C_EVT_SLAVE_RECV_ADDR_MATCHED (((uint32_t)I2C_STS1_ADDRF)\ + |((((uint32_t)I2C_STS2_BUSY))<<16)) + /* TRF, BUSY, TXDATE and ADDRF flags */ +#define I2C_EVT_SLAVE_SEND_ADDR_MATCHED (((uint32_t)I2C_STS1_TXDATE)|((uint32_t)I2C_STS1_ADDRF)\ + |((((uint32_t)I2C_STS2_BUSY)|((uint32_t)I2C_STS2_TRF))<<16)) + +/* 2) Case of Dual address managed by the slave */ + /* DUALF and BUSY flags */ +#define I2C_EVT_SLAVE_RECV_ADDR2_MATCHED ((((uint32_t)I2C_STS2_BUSY)|((uint32_t)I2C_STS2_DUALFLAG))<<16) + /* DUALF, TRF, BUSY and TXDATE flags */ +#define I2C_EVT_SLAVE_SEND_ADDR2_MATCHED (((uint32_t)I2C_STS1_TXDATE)\ + |((((uint32_t)I2C_STS2_BUSY)|((uint32_t)I2C_STS2_DUALFLAG)|((uint32_t)I2C_STS2_TRF))<<16)) + +/* 3) Case of General Call enabled for the slave */ + /* GENCALL and BUSY flags */ +#define I2C_EVT_SLAVE_GCALLADDR_MATCHED ((((uint32_t)I2C_STS2_BUSY)|((uint32_t)I2C_STS2_GCALLADDR))<<16) + +/** +*\*\brief Communication events +*\*\Wait on one of these events when EV1 has already been checked and: +*\*\- Slave RECEIVER mode: +*\*\ - EV2: When the application is expecting a data byte to be received. +*\*\ - EV4: When the application is expecting the end of the communication: master +*\*\ sends a stop condition and data transmission is stopped. +*\*\- Slave Transmitter mode: +*\*\ - EV3: When a byte has been transmitted by the slave and the application is expecting +*\*\ the end of the byte transmission. The two events I2C_EVT_SLAVE_DATA_SENDED and +*\*\ I2C_EVT_SLAVE_DATA_SENDING are similar. The second one can optionally be +*\*\ used when the user software doesn't guarantee the EV3 is managed before the +*\*\ current byte end of transfer. +*\*\ - EV3_2: When the master sends a NACK in order to tell slave that data transmission +*\*\ shall end (before sending the STOP condition). In this case slave has to stop sending +*\*\ data bytes and expect a Stop condition on the bus. +*\*\note In case the user software does not guarantee that the event EV2 is +*\*\ managed before the current byte end of transfer, then user may check on EV2 +*\*\ and BSF flag at the same time (ie. (I2C_EVT_SLAVE_DATA_RECVD | I2C_FLAG_BYTEF)). +*\*\In this case the communication may be slower. + **/ + +/* Slave RECEIVER mode --------------------------*/ +/* --EV2 */ + /* BUSY and RXDATNE flags */ +#define I2C_EVT_SLAVE_DATA_RECVD (((uint32_t)I2C_STS1_RXDATNE)\ + |((((uint32_t)I2C_STS2_BUSY))<<16)) +/* --EV2x */ + /* no BUSY and RXDATNE flags */ +#define I2C_EVT_SLAVE_DATA_RECVD_NOBUSY ((uint32_t)I2C_STS1_RXDATNE) +/* --EV4 */ + /* STOPF flag */ +#define I2C_EVT_SLAVE_STOP_RECVD ((uint32_t)I2C_STS1_STOPF) + +/* Slave TRANSMITTER mode -----------------------*/ +/* --EV3 */ + /* TRF, BUSY, TXDATE and BSF flags */ +#define I2C_EVT_SLAVE_DATA_SENDED (((uint32_t)I2C_STS1_BSF)|((uint32_t)I2C_STS1_TXDATE)\ + |((((uint32_t)I2C_STS2_BUSY)|((uint32_t)I2C_STS2_TRF))<<16)) + /* TRF, BUSY and TXDATE flags */ +#define I2C_EVT_SLAVE_DATA_SENDING (((uint32_t)I2C_STS1_TXDATE)\ + |((((uint32_t)I2C_STS2_BUSY)|((uint32_t)I2C_STS2_TRF))<<16)) +/* --EV3_2 */ + /* AF flag */ +#define I2C_EVT_SLAVE_ACK_MISS ((uint32_t)I2C_STS1_ACKFAIL) + +/*=========================== End of Events Description ==========================================*/ + +void I2C_Reset(I2C_Module* I2Cx); +void I2C_Initializes(I2C_Module* I2Cx, I2C_InitType* I2C_InitParam); +void I2C_Clock_Speed_Config(I2C_Module* I2Cx, uint32_t clk_speed, uint16_t duty_cycle); +void I2C_Acknowledgement_Config(I2C_Module* I2Cx, uint16_t ack); +void I2C_Addressing_Mode_Config(I2C_Module* I2Cx, uint16_t mode); +void I2C_Own_Addr1_Config(I2C_Module* I2Cx, uint16_t addr1); +void I2C_Initializes_Structure(I2C_InitType* I2C_InitStruct); +void I2C_ON(I2C_Module* I2Cx); +void I2C_OFF(I2C_Module* I2Cx); +void I2C_Generate_Start_Enable(I2C_Module* I2Cx); +void I2C_Generate_Start_Disable(I2C_Module* I2Cx); +void I2C_Generate_Stop_Enable(I2C_Module* I2Cx); +void I2C_Generate_Stop_Disable(I2C_Module* I2Cx); +void I2C_Acknowledg_Enable(I2C_Module* I2Cx); +void I2C_Acknowledg_Disable(I2C_Module* I2Cx); +void I2C_Own_Addr2_Set(I2C_Module* I2Cx, uint8_t address); +void I2C_Dual_Addr_Enable(I2C_Module* I2Cx); +void I2C_Dual_Addr_Disable(I2C_Module* I2Cx); +void I2C_General_Call_Enable(I2C_Module* I2Cx); +void I2C_General_Call_Disable(I2C_Module* I2Cx); +void I2C_Interrupts_Enable(I2C_Module* I2Cx, uint16_t I2C_IT); +void I2C_Interrupts_Disable(I2C_Module* I2Cx, uint16_t I2C_IT); +void I2C_Data_Send(I2C_Module* I2Cx, uint8_t data); +uint8_t I2C_Data_Recv(I2C_Module* I2Cx); +void I2C_7bit_Addr_Send(I2C_Module* I2Cx, uint8_t address, uint8_t mode); +uint16_t I2C_Register_Value_Get(I2C_Module* I2Cx, uint8_t I2C_Register); +void I2C_Software_Reset_Enable(I2C_Module* I2Cx); +void I2C_Software_Reset_Disable(I2C_Module* I2Cx); +void I2C_NACK_Position_Set(I2C_Module* I2Cx, uint16_t position); +void I2C_PEC_Send_Enable(I2C_Module* I2Cx); +void I2C_PEC_Send_Disable(I2C_Module* I2Cx); +void I2C_PEC_Position_Set(I2C_Module* I2Cx, uint16_t position); +void I2C_PEC_Compute_Enable(I2C_Module* I2Cx); +void I2C_PEC_Compute_Disable(I2C_Module* I2Cx); +uint8_t I2C_PEC_Get(I2C_Module* I2Cx); +void I2C_Extend_Clock_Enable(I2C_Module* I2Cx); +void I2C_Extend_Clock_Disable(I2C_Module* I2Cx); +void I2C_Fast_Mode_Duty_Cycle_Set(I2C_Module* I2Cx, uint16_t duty_cycle); +void I2C_SDA_Digital_Filter_Width_Set(I2C_Module* I2Cx, uint8_t width); +void I2C_SCL_Digital_Filter_Width_Set(I2C_Module* I2Cx, uint8_t width); +void I2C_SDA_Analog_Filter_Width_Set(I2C_Module* I2Cx, uint16_t width); +void I2C_SDA_Analog_Filter_Enable(I2C_Module* I2Cx); +void I2C_SDA_Analog_Filter_Disable(I2C_Module* I2Cx); +void I2C_SCL_Analog_Filter_Width_Set(I2C_Module* I2Cx, uint16_t width); +void I2C_SCL_Analog_Filter_Enable(I2C_Module* I2Cx); +void I2C_SCL_Analog_Filter_Disable(I2C_Module* I2Cx); +ErrorStatus I2C_Event_Check( I2C_Module* I2Cx, uint32_t I2C_event ); +uint32_t I2C_Last_Event_Get( I2C_Module* I2Cx ); +FlagStatus I2C_Flag_Status_Get( I2C_Module* I2Cx, uint32_t I2C_flag ); +void I2C_Flag_Status_Clear( I2C_Module* I2Cx, uint32_t I2C_flag ); +ITStatus I2C_Interrupt_Status_Get( I2C_Module* I2Cx, uint32_t Interrupt ); +void I2C_Interrupt_Statu_Clear(I2C_Module* I2Cx, uint32_t Interrupt); +void I2C_ByteNum_enable(I2C_Module* I2Cx); +void I2C_ByteNum_Disable(I2C_Module* I2Cx); +void I2C_Master_Received_DataBytesNum_Set(I2C_Module* I2Cx, uint16_t Number_Of_bytes); +void I2C_ByteNum_Last_StartStop_Set(I2C_Module* I2Cx, uint16_t LastStatus); + +#ifdef __cplusplus +} +#endif + +#endif /*__N32G003_I2C_H */ +/** + * + */ diff --git a/firmware/n32g003_std_periph_driver/inc/n32g003_iwdg.h b/firmware/n32g003_std_periph_driver/inc/n32g003_iwdg.h new file mode 100644 index 0000000..e5ec065 --- /dev/null +++ b/firmware/n32g003_std_periph_driver/inc/n32g003_iwdg.h @@ -0,0 +1,111 @@ +/** +* Copyright (c) 2022, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** +*\*\file n32g003_iwdg.h +*\*\author Nations +*\*\version v1.0.0 +*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. +**/ + +#ifndef __n32g003_IWDG_H +#define __n32g003_IWDG_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "n32g003.h" + +typedef enum +{ + IWDG_PVU_FLAG = IWDG_STS_PVU, + IWDG_CRVU_FLAG = IWDG_STS_CRVU +}IWDG_STATUS_FLAG; + +/** KEY register bit mask **/ +#define KEY_RELOAD_COUNTER ((uint16_t)0xAAAA) +#define KEY_ENABLE_COUNTER ((uint16_t)0xCCCC) +#define IWDG_FREEZE ((uint16_t)0xDDDD) +#define IWDG_UNFREEZE ((uint16_t)0xDDDD) + +/** PREDIV and RELV register write permission **/ +typedef enum +{ + IWDG_WRITE_CONFIG_ENABLE = 0x5555, + IWDG_WRITE_CONFIG_DISABLE = 0x0000 +}IWDOG_WRITE_CONFIG; + + +typedef enum +{ + IWDG_CONFIG_PRESCALER_DIV4 = (~IWDG_PREDIV_PD), + IWDG_CONFIG_PRESCALER_DIV8 = (IWDG_PREDIV_PD0), + IWDG_CONFIG_PRESCALER_DIV16 = (IWDG_PREDIV_PD1), + IWDG_CONFIG_PRESCALER_DIV32 = (IWDG_PREDIV_PD1 | IWDG_PREDIV_PD0), + IWDG_CONFIG_PRESCALER_DIV64 = (IWDG_PREDIV_PD2), + IWDG_CONFIG_PRESCALER_DIV128 = (IWDG_PREDIV_PD2 | IWDG_PREDIV_PD0), + IWDG_CONFIG_PRESCALER_DIV256 = (IWDG_PREDIV_PD2 | IWDG_PREDIV_PD1 | IWDG_PREDIV_PD0) +}IWDG_CONFIG_PRESCALER; + +#define IWDG_FREEZE_FLAG ((uint16_t)IWDG_FREEZE_FREEZE) + +void IWDG_Write_Protection_Disable(void); +void IWDG_Write_Protection_Enable(void); +void IWDG_Prescaler_Division_Set(IWDG_CONFIG_PRESCALER IWDG_prescaler); +void IWDG_Counter_Reload(uint16_t reload_value); +void IWDG_Key_Reload(void); +void IWDG_Enable(void); +ErrorStatus IWDG_Freeze_Enable(void); +ErrorStatus IWDG_Restore_From_Freeze(void); +FlagStatus IWDG_Status_Get(IWDG_STATUS_FLAG IWDG_flag); + +#ifdef __cplusplus +} +#endif + +#endif /* __n32g003_IWDG_H */ diff --git a/firmware/n32g003_std_periph_driver/inc/n32g003_pwr.h b/firmware/n32g003_std_periph_driver/inc/n32g003_pwr.h new file mode 100644 index 0000000..c5661e2 --- /dev/null +++ b/firmware/n32g003_std_periph_driver/inc/n32g003_pwr.h @@ -0,0 +1,328 @@ +/** +* Copyright (c) 2022, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** +*\*\file n32g003_pwr.h +*\*\author Nations +*\*\version v1.0.0 +*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ + +#ifndef __N32G003_PWR_H +#define __N32G003_PWR_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "n32g003.h" + +/*** PWR Structure Definition Start ***/ + +/** PWR wakeup PINx enmu definition **/ +typedef enum +{ + WAKEUP_PIN1 = 0x0100, + WAKEUP_PIN2 = 0x0200, +} WAKEUP_PINX; + +/*** PWR Structure Definition End ***/ + +/*** PWR Macro Definition Start ***/ + +/** PWR CTRL register bit mask definition **/ +#define PWR_CTRL_PLS_MASK (~((uint32_t)PWR_CTRL_PLS)) +#define PWR_CTRL_PDSTP_MASK (~((uint32_t)PWR_CTRL_PDSTP)) +#define PWR_CTRL_PDRS_MASK (~((uint32_t)PWR_CTRL_PDRS)) + +/** PWR CTRL2 register bit mask definition **/ +#define PWR_CTRL2_LVRLS_MASK (~((uint32_t)PWR_CTRL2_LVRLS)) + +/** PWR CTRLSTS register bit mask definition **/ +#define PWR_CTRLSTS_WKUPPOL_MASK (~((uint32_t)PWR_CTRLSTS_WKUPPOL)) + +/** PWR CTRL5 register bit mask definition **/ +#define PWR_CTRL5_STPMRSEL_MASK (~((uint32_t)PWR_CTRL5_STPMRSEL)) + +/** PWR PVD enable definition **/ +#define PWR_PVD_ENABLE ((uint32_t)PWR_CTRL_PVDEN) + +/** PWR PVD interrupt enable definition **/ +#define PWR_PVD_INT_ENABLE ((uint32_t)PWR_CTRL_PVDITEN) + +/** PWR PVD Filter enable definition **/ +#define PWR_PVD_FIL_ENABLE ((uint32_t)PWR_CTRL_PVDFILEN) + +/** PWR LVR enable definition **/ +#define PWR_LVR_ENABLE ((uint32_t)PWR_CTRL2_LVREN) + +/** PWR LVR reset enable definition **/ +#define PWR_LVR_RST_ENABLE ((uint32_t)PWR_CTRL2_LVRRSTEN) + +/** PWR LVR Filter enable definition **/ +#define PWR_LVR_FIL_ENABLE ((uint32_t)PWR_CTRL2_LVRFILEN) + +/** PWR wakup PIN polarity definition **/ +#define PWR_PIN_RISING ((uint32_t)0x00000001) +#define PWR_PIN_FALLING ((uint32_t)0x00000000) + +/** PWR clear WKUPF definition **/ +#define PWR_CLEAR_WKUPF ((uint32_t)PWR_CTRL_CLRWKUPF) + +/** PWR PVD output Flag definition **/ +#define PWR_PVD_OUTPUT_FLAG ((uint32_t)PWR_CTRLSTS_PVDO) + +/** PWR PD Flag definition **/ +#define PWR_DBGPD_FLAG ((uint32_t)PWR_CTRLSTS_DBGPDF) + +/** PWR PA2/PA1wakeup Flag definition **/ +#define PWR_WKUP_FLAG ((uint32_t)PWR_CTRLSTS_WKUPF) + +/** PWR LVR output Flag definition **/ +#define PWR_LVR_OUTPUT_FLAG ((uint32_t)PWR_CTRL2_LVRO) + +/** PWR PD mode definition **/ +#define PWR_PD_MODE ((uint32_t)PWR_CTRL_PDSTP) + +/** PWR control HSI definition **/ +#define PWR_CONTROL_HSI ((uint32_t)PWR_CTRL3_HSIPWR) + +/** PWR control PDR select signal definition **/ +#define PWR_CONTROL_PDR_SEL ((uint32_t)PWR_CTRL3_PDRSEL) + +/** PWR HSI 40M trim definition **/ +#define PWR_HSI_TRIM_40M ((uint32_t)PWR_CTRL3_HSISEL) + +/** PWR enable VDDD output voltage select definition **/ +#define PWR_VDDD_OUTPUT_SEL_EN ((uint32_t)PWR_CTRL6_STPMREN) + +/** PWR PVD threshold level definition **/ +#define PWR_PVD_LEVEL_1V8 ((uint32_t)(PWR_CTRL_PLS_0 \ + & PWR_CTRL_PLS_1 \ + & PWR_CTRL_PLS_2 \ + & PWR_CTRL_PLS_3)) /* 1.8v PWR_CTRL bit[8:5]:0000 */ + +#define PWR_PVD_LEVEL_2V0 ((uint32_t)PWR_CTRL_PLS_0) /* 2.0v PWR_CTRL bit[8:5]:0001 */ + +#define PWR_PVD_LEVEL_2V2 ((uint32_t)PWR_CTRL_PLS_1) /* 2.2v PWR_CTRL bit[8:5]:0010 */ + +#define PWR_PVD_LEVEL_2V4 ((uint32_t)(PWR_CTRL_PLS_0 \ + | PWR_CTRL_PLS_1)) /* 2.4v PWR_CTRL bit[8:5]:0011 */ + +#define PWR_PVD_LEVEL_2V6 ((uint32_t)PWR_CTRL_PLS_2) /* 2.6v PWR_CTRL bit[8:5]:0100 */ + +#define PWR_PVD_LEVEL_2V8 ((uint32_t)(PWR_CTRL_PLS_0 \ + | PWR_CTRL_PLS_2)) /* 2.8v PWR_CTRL bit[8:5]:0101 */ + +#define PWR_PVD_LEVEL_3V0 ((uint32_t)(PWR_CTRL_PLS_1 \ + | PWR_CTRL_PLS_2)) /* 3.0v PWR_CTRL bit[8:5]:0110 */ + +#define PWR_PVD_LEVEL_3V2 ((uint32_t)(PWR_CTRL_PLS_0 \ + | PWR_CTRL_PLS_1 \ + | PWR_CTRL_PLS_2)) /* 3.2v PWR_CTRL bit[8:5]:0111 */ + +#define PWR_PVD_LEVEL_3V4 ((uint32_t)PWR_CTRL_PLS_3) /* 3.4v PWR_CTRL bit[8:5]:1000 */ + +#define PWR_PVD_LEVEL_3V6 ((uint32_t)(PWR_CTRL_PLS_0 \ + | PWR_CTRL_PLS_3)) /* 3.6v PWR_CTRL bit[8:5]:1001 */ + +#define PWR_PVD_LEVEL_3V8 ((uint32_t)(PWR_CTRL_PLS_1 \ + | PWR_CTRL_PLS_3)) /* 3.8v PWR_CTRL bit[8:5]:1010 */ + +#define PWR_PVD_LEVEL_4V0 ((uint32_t)(PWR_CTRL_PLS_0 \ + | PWR_CTRL_PLS_1 \ + | PWR_CTRL_PLS_3)) /* 4.0v PWR_CTRL bit[8:5]:1011 */ + +#define PWR_PVD_LEVEL_4V2 ((uint32_t)(PWR_CTRL_PLS_2 \ + | PWR_CTRL_PLS_3)) /* 4.2v PWR_CTRL bit[8:5]:1100 */ + +#define PWR_PVD_LEVEL_4V4 ((uint32_t)(PWR_CTRL_PLS_0 \ + | PWR_CTRL_PLS_2 \ + | PWR_CTRL_PLS_3)) /* 4.4v PWR_CTRL bit[8:5]:1101 */ + +#define PWR_PVD_LEVEL_4V6 ((uint32_t)(PWR_CTRL_PLS_1 \ + | PWR_CTRL_PLS_2 \ + | PWR_CTRL_PLS_3)) /* 4.6v PWR_CTRL bit[8:5]:1110 */ + +#define PWR_PVD_LEVEL_4V8 ((uint32_t)(PWR_CTRL_PLS_0 \ + | PWR_CTRL_PLS_1 \ + | PWR_CTRL_PLS_2 \ + | PWR_CTRL_PLS_3)) /* 4.8v PWR_CTRL bit[8:5]:1111 */ + +/** PWR LVR threshold level definition **/ +#define PWR_LVR_LEVEL_1V8 ((uint32_t)(PWR_CTRL2_LVRLS_0 \ + & PWR_CTRL2_LVRLS_1 \ + & PWR_CTRL2_LVRLS_2 \ + & PWR_CTRL2_LVRLS_3)) /* 1.8v PWR_CTRL2 bit[14:11]:0000 */ + +#define PWR_LVR_LEVEL_2V0 ((uint32_t)PWR_CTRL2_LVRLS_0) /* 2.0v PWR_CTRL2 bit[14:11]:0001 */ + +#define PWR_LVR_LEVEL_2V2 ((uint32_t)PWR_CTRL2_LVRLS_1) /* 2.2v PWR_CTRL2 bit[14:11]:0010 */ + +#define PWR_LVR_LEVEL_2V4 ((uint32_t)(PWR_CTRL2_LVRLS_0 \ + | PWR_CTRL2_LVRLS_1)) /* 2.4v PWR_CTRL2 bit[14:11]:0011 */ + +#define PWR_LVR_LEVEL_2V6 ((uint32_t)PWR_CTRL2_LVRLS_2) /* 2.6v PWR_CTRL2 bit[14:11]:0100 */ + +#define PWR_LVR_LEVEL_2V8 ((uint32_t)(PWR_CTRL2_LVRLS_0 \ + | PWR_CTRL2_LVRLS_2)) /* 2.8v PWR_CTRL2 bit[14:11]:0101 */ + +#define PWR_LVR_LEVEL_3V0 ((uint32_t)(PWR_CTRL2_LVRLS_1 \ + | PWR_CTRL2_LVRLS_2)) /* 3.0v PWR_CTRL2 bit[14:11]:0110 */ + +#define PWR_LVR_LEVEL_3V2 ((uint32_t)(PWR_CTRL2_LVRLS_0 \ + | PWR_CTRL2_LVRLS_1 \ + | PWR_CTRL2_LVRLS_2)) /* 3.2v PWR_CTRL2 bit[14:11]:0111 */ + +#define PWR_LVR_LEVEL_3V4 ((uint32_t)PWR_CTRL2_LVRLS_3) /* 3.4v PWR_CTRL2 bit[14:11]:1000 */ + +#define PWR_LVR_LEVEL_3V6 ((uint32_t)(PWR_CTRL2_LVRLS_0 \ + | PWR_CTRL2_LVRLS_3)) /* 3.6v PWR_CTRL2 bit[14:11]:1001 */ + +#define PWR_LVR_LEVEL_3V8 ((uint32_t)(PWR_CTRL2_LVRLS_1 \ + | PWR_CTRL2_LVRLS_3)) /* 3.8v PWR_CTRL2 bit[14:11]:1010 */ + +#define PWR_LVR_LEVEL_4V0 ((uint32_t)(PWR_CTRL2_LVRLS_0 \ + | PWR_CTRL2_LVRLS_1 \ + | PWR_CTRL2_LVRLS_3)) /* 4.0v PWR_CTRL2 bit[14:11]:1011 */ + +#define PWR_LVR_LEVEL_4V2 ((uint32_t)(PWR_CTRL2_LVRLS_2 \ + | PWR_CTRL2_LVRLS_3)) /* 4.2v PWR_CTRL2 bit[14:11]:1100 */ + +#define PWR_LVR_LEVEL_4V4 ((uint32_t)(PWR_CTRL2_LVRLS_0 \ + | PWR_CTRL2_LVRLS_2 \ + | PWR_CTRL2_LVRLS_3)) /* 4.4v PWR_CTRL2 bit[14:11]:1101 */ + +#define PWR_LVR_LEVEL_4V6 ((uint32_t)(PWR_CTRL2_LVRLS_1 \ + | PWR_CTRL2_LVRLS_2 \ + | PWR_CTRL2_LVRLS_3)) /* 4.6v PWR_CTRL2 bit[14:11]:1110 */ + +#define PWR_LVR_LEVEL_4V8 ((uint32_t)(PWR_CTRL2_LVRLS_0 \ + | PWR_CTRL2_LVRLS_1 \ + | PWR_CTRL2_LVRLS_2 \ + | PWR_CTRL2_LVRLS_3)) /* 4.8v PWR_CTRL2 bit[14:11]:1111 */ + +/** PWR PDR trigger level definition **/ +#define PWR_PDR_LEVEL_0V8 ((uint32_t)PWR_CTRL_PDRS_0) /* 0.8v PWR_CTRL bit[10:9]:01 */ + +#define PWR_PDR_LEVEL_1V0 ((uint32_t)PWR_CTRL_PDRS_1) /* 1.0v PWR_CTRL bit[10:9]:10 */ + +#define PWR_PDR_LEVEL_1V2 ((uint32_t)(PWR_CTRL_PDRS_0 \ + | PWR_CTRL_PDRS_1)) /* 0.2v PWR_CTRL bit[10:9]:11 */ + +/** PWR VDDD output voltage definition **/ +#define PWR_VDDD_OUTPUT_1V5 ((uint32_t)PWR_CTRL5_STPMRSEL_0) /* 1.5v PWR_CTRL5 bit[3:2]:01 */ + +#define PWR_VDDD_OUTPUT_1V0 ((uint32_t)PWR_CTRL5_STPMRSEL_1) /* 1.0v PWR_CTRL5 bit[3:2]:10 */ + +#define PWR_VDDD_OUTPUT_1V2 ((uint32_t)(PWR_CTRL5_STPMRSEL_0 \ + | PWR_CTRL5_STPMRSEL_1)) /* 0.2v PWR_CTRL5 bit[3:2]:11 */ + +/** PWR STOP mode entry definition **/ +#define PWR_STOP_ENTRY_WFI ((uint8_t)0x01) /* enter STOP mode with WFI instruction */ +#define PWR_STOP_ENTRY_WFE ((uint8_t)0x02) /* enter STOP mode with WFE instruction */ + +/** PWR PD mode entry definition **/ +#define PWR_PD_ENTRY_WFI ((uint8_t)0x01) /* enter PD mode with WFI instruction */ +#define PWR_PD_ENTRY_WFE ((uint8_t)0x02) /* enter PD mode with WFE instruction */ + +/** PWR DBG_CTRL definition **/ +#define PWR_DBG_SLEEP ((uint32_t)DBG_CTRL_SLEEP) +#define PWR_DBG_STOP ((uint32_t)DBG_CTRL_STOP) +#define PWR_DBG_PD ((uint32_t)DBG_CTRL_PD) +#define PWR_DBG_IWDG ((uint32_t)DBG_CTRL_IWDGSTP) +#define PWR_DBG_TIM1 ((uint32_t)DBG_CTRL_TIM1STP) +#define PWR_DBG_TIM3 ((uint32_t)DBG_CTRL_TIM3STP) +#define PWR_DBG_TIM6 ((uint32_t)DBG_CTRL_TIM6STP) + +/** PWR registers write protection keys definition **/ +#define PWR_CTRL2_KEYS ((uint32_t)0xA5000000) +#define PWR_CTRL4_KEYS ((uint32_t)0x01753603) + +/** PWR bit shift number definition **/ +#define PWR_BIT_SHIFT_2 ((uint32_t)REG_BIT2_OFFSET) +#define PWR_BIT_SHIFT_10 ((uint32_t)REG_BIT10_OFFSET) + +/*** PWR Macro Definition End ***/ + +/*** PWR Driving Functions Declaration ***/ + +void PWR_Reset(void); +void PWR_PVD_Enable(void); +void PWR_PVD_Disable(void); +void PWR_PVD_Interrupt_Enable(void); +void PWR_PVD_Interrupt_Disable(void); +void PWR_PVD_Filter_Enable(void); +void PWR_PVD_Filter_Disable(void); +void PWR_PVD_Level_Config(uint32_t level); +void PWR_LVR_Enable(void); +void PWR_LVR_Disable(void); +void PWR_LVR_Reset_Enable(void); +void PWR_LVR_Reset_Disable(void); +void PWR_LVR_Filter_Enable(void); +void PWR_LVR_Filter_Disable(void); +void PWR_LVR_Level_Config(uint32_t level); +void PWR_Wakeup_Pin_Enable(WAKEUP_PINX pin, uint32_t polarity); +void PWR_Wakeup_Pin_Disable(WAKEUP_PINX pin); +void PWR_STOP_Mode_Enter(uint8_t enter_mode); +void PWR_PD_Mode_Enter(uint8_t enter_mode); +void PWR_HSI_40M_Trim_Select(void); +void PWR_PDR_Trigger_Level_Config(uint32_t level); +void PWR_VDDD_Output_Config(uint32_t voltage_output); +void PWR_CTRL2_write_Protection_Enable(void); +void PWR_CTRL4_write_Protection_Enable(void); +FlagStatus PWR_Flag_Status_Get(uint32_t flag); +void PWR_Flag_Status_Clear(uint32_t flag); +void DBG_Peripheral_ON(uint32_t DBG_Periph); +void DBG_Peripheral_OFF(uint32_t DBG_Periph); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32G003_PWR_H */ + diff --git a/firmware/n32g003_std_periph_driver/inc/n32g003_rcc.h b/firmware/n32g003_std_periph_driver/inc/n32g003_rcc.h new file mode 100644 index 0000000..11d54d7 --- /dev/null +++ b/firmware/n32g003_std_periph_driver/inc/n32g003_rcc.h @@ -0,0 +1,271 @@ +/** +* Copyright (c) 2022, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** +*\*\file n32g003_rcc.h +*\*\author Nations +*\*\version v1.0.0 +*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#ifndef __n32g003_RCC_H +#define __n32g003_RCC_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "n32g003.h" + +/** RCC_Exported_Types **/ + +typedef struct +{ + uint32_t SysclkFreq; /* returns SYSCLK clock frequency expressed in Hz */ + uint32_t HclkFreq; /* returns HCLK clock frequency expressed in Hz */ + uint32_t PclkFreq; /* returns PCLK clock frequency expressed in Hz */ + uint32_t Adc1MClkFreq; /* returns ADC1MHCLK clock frequency expressed in Hz */ + uint32_t AdcClkFreq; /* returns ADCHCLK clock frequency expressed in Hz */ +}RCC_ClocksType; + + +/** RCC registers bit mask **/ +#define HSI_FREQ_48M (48000000) +#define HSI_FREQ_40M (40000000) + +/** Register shift macro definition **/ +#define RCC_CFG_AHBPRES_OFFSET (REG_BIT4_OFFSET) +#define RCC_CFG_APBPRES_OFFSET (REG_BIT8_OFFSET) +#define RCC_CFG2_ADC1MPRES_OFFSET (REG_BIT10_OFFSET) + + +/* RCC Flag Mask */ +#define FLAG_Mask ((uint8_t)0x1F) + + +/** Internal High Speed clock trimming **/ +#define RCC_HSITRIM_MASK (~RCC_HSICTRL_HSITRIM) +/** Internal Low Speed clock trimming **/ +#define RCC_LSITRIM_MASK (~RCC_LSICTRL_LSITRIM) + + +/** SYS_clock_source **/ +#define RCC_HSICLK_DIV_MASK (~RCC_CFG_SYSPRES) +#define RCC_HSICLK_DIV1 (RCC_CFG_SYSPRES_DIV1) +#define RCC_HSICLK_DIV2 (RCC_CFG_SYSPRES_DIV2) +#define RCC_HSICLK_DIV5 (RCC_CFG_SYSPRES_DIV5) +#define RCC_HSICLK_DIV6 (RCC_CFG_SYSPRES_DIV6) + +/** AHB_clock_source **/ +#define RCC_SYSCLK_DIV_MASK (~RCC_CFG_AHBPRES) +#define RCC_SYSCLK_DIV1 (RCC_CFG_AHBPRES_DIV1) +#define RCC_SYSCLK_DIV2 (RCC_CFG_AHBPRES_DIV2) +#define RCC_SYSCLK_DIV4 (RCC_CFG_AHBPRES_DIV4) +#define RCC_SYSCLK_DIV8 (RCC_CFG_AHBPRES_DIV8) +#define RCC_SYSCLK_DIV12 (RCC_CFG_AHBPRES_DIV12) +#define RCC_SYSCLK_DIV16 (RCC_CFG_AHBPRES_DIV16) +#define RCC_SYSCLK_DIV24 (RCC_CFG_AHBPRES_DIV24) + +/** APB_clock_source **/ +#define RCC_APB_DIV_MASK (~RCC_CFG_APBPRES) +#define RCC_HCLK_DIV1 (RCC_CFG_APBPRES_DIV1) +#define RCC_HCLK_DIV2 (RCC_CFG_APBPRES_DIV2) +#define RCC_HCLK_DIV4 (RCC_CFG_APBPRES_DIV4) +#define RCC_HCLK_DIV8 (RCC_CFG_APBPRES_DIV8) +#define RCC_HCLK_DIV16 (RCC_CFG_APBPRES_DIV16) + +/** RCC_CFGR2_Config **/ +#define RCC_TIM1_CLKSRC_MASK (~RCC_CFG2_TIM1CLKSEL) +#define RCC_TIM1_CLKSRC_PCLK (RCC_CFG2_TIM1CLKSEL_PCLK) +#define RCC_TIM1_CLKSRC_SYSCLK (RCC_CFG2_TIM1CLKSEL_SYSCLK) + +#define RCC_ADC1MCLK_DIV_MASK (~RCC_CFG2_ADC1MPRES) +#define RCC_ADC1MCLK_DIV6 (RCC_CFG2_ADC1MPRES_DIV6) +#define RCC_ADC1MCLK_DIV12 (RCC_CFG2_ADC1MPRES_DIV12) +#define RCC_ADC1MCLK_DIV24 (RCC_CFG2_ADC1MPRES_DIV24) +#define RCC_ADC1MCLK_DIV40 (RCC_CFG2_ADC1MPRES_DIV40) +#define RCC_ADC1MCLK_DIV48 (RCC_CFG2_ADC1MPRES_DIV48) + +#define RCC_ADC_DIV_MASK (~RCC_CFG2_ADCPRES) +#define RCC_ADC_DIV1 (RCC_CFG2_ADCPRES_DIV1) +#define RCC_ADC_DIV2 (RCC_CFG2_ADCPRES_DIV2) +#define RCC_ADC_DIV3 (RCC_CFG2_ADCPRES_DIV3) +#define RCC_ADC_DIV4 (RCC_CFG2_ADCPRES_DIV4) +#define RCC_ADC_DIV6 (RCC_CFG2_ADCPRES_DIV6) +#define RCC_ADC_DIV8 (RCC_CFG2_ADCPRES_DIV8) +#define RCC_ADC_DIV10 (RCC_CFG2_ADCPRES_DIV10) +#define RCC_ADC_DIV12 (RCC_CFG2_ADCPRES_DIV12) +#define RCC_ADC_DIV24 (RCC_CFG2_ADCPRES_DIV24) +#define RCC_ADC_DIV32 (RCC_CFG2_ADCPRES_DIV32) +#define RCC_ADC_DIV_OTHERS (RCC_CFG2_ADCPRES_OTHERS) + +#define RCC_TIM6_CLKSRC_MASK (~RCC_CFG2_TIM6CLKSEL) +#define RCC_TIM6_CLKSRC_PCLK (RCC_CFG2_TIM6CLKSEL_PCLK) +#define RCC_TIM6_CLKSRC_LSI (RCC_CFG2_TIM6CLKSEL_LSI) + +/** Peripheral Reset**/ +#define RCC_RST_AFIORST (RCC_PRST_AFIORST) +#define RCC_RST_BEEPRST (RCC_PRST_BEEPRST) +#define RCC_RST_GPIOARST (RCC_PRST_GPIOARST) +#define RCC_RST_GPIOBRST (RCC_PRST_GPIOBRST) +#define RCC_RST_UART1RST (RCC_PRST_UART1RST) +#define RCC_RST_UART2RST (RCC_PRST_UART2RST) +#define RCC_RST_I2CRST (RCC_PRST_I2CRST) +#define RCC_RST_PWRRST (RCC_PRST_PWRRST) +#define RCC_RST_ADCRST (RCC_PRST_ADCRST) +#define RCC_RST_SPIRST (RCC_PRST_SPIRST) +#define RCC_RST_TIM1RST (RCC_PRST_TIM1RST) +#define RCC_RST_TIM3RST (RCC_PRST_TIM3RST) +#define RCC_RST_TIM6RST (RCC_PRST_TIM6RST) +#define RCC_RST_COMPRST (RCC_PRST_COMPRST) + +/** Peripheral Enable **/ + +/** AHB_peripheral **/ +#define RCC_AHB_PERIPH_CRC (RCC_AHBPCLKEN_CRCEN) +#define RCC_AHB_PERIPH_ADC (RCC_AHBPCLKEN_ADCEN) + +/** APB_peripheral **/ +#define RCC_APB_PERIPH_AFIO (RCC_APBPCLKEN_AFIOEN) +#define RCC_APB_PERIPH_BEEPER (RCC_APBPCLKEN_BEEPEREN) +#define RCC_APB_PERIPH_IOPA (RCC_APBPCLKEN_IOPAEN) +#define RCC_APB_PERIPH_IOPB (RCC_APBPCLKEN_IOPBEN) +#define RCC_APB_PERIPH_COMP (RCC_APBPCLKEN_COMPEN) +#define RCC_APB_PERIPH_COMP_FILT (RCC_APBPCLKEN_COMPFILTEN) +#define RCC_APB_PERIPH_UART1 (RCC_APBPCLKEN_UART1EN) +#define RCC_APB_PERIPH_UART2 (RCC_APBPCLKEN_UART2EN) +#define RCC_APB_PERIPH_I2C (RCC_APBPCLKEN_I2CEN) +#define RCC_APB_PERIPH_PWR (RCC_APBPCLKEN_PWREN) +#define RCC_APB_PERIPH_SPI (RCC_APBPCLKEN_SPIEN) +#define RCC_APB_PERIPH_TIM1 (RCC_APBPCLKEN_TIM1EN) +#define RCC_APB_PERIPH_TIM3 (RCC_APBPCLKEN_TIM3EN) +#define RCC_APB_PERIPH_TIM6 (RCC_APBPCLKEN_TIM6EN) +#define RCC_APB_PERIPH_IWDG (RCC_APBPCLKEN_IWDGEN) + +/** RCC_Exported_Constants **/ + +/** Register shift macro definition **/ +#define RCC_FLAG_OFFSET (REG_BIT5_OFFSET) +#define RCC_CTRL_HSITRIM_OFFSET (REG_BIT4_OFFSET) +#define RCC_CTRL_LSITRIM_OFFSET (REG_BIT2_OFFSET) + + +/** Clock_source_to_output_on_MCO_pin **/ +#define RCC_MCO_MASK (~RCC_CFG_MCO) +#define RCC_MCO_NOCLK (RCC_CFG_MCO_NOCLK) +#define RCC_MCO_LSI (RCC_CFG_MCO_LSI) +#define RCC_MCO_HSI (RCC_CFG_MCO_HSI) + +#define RCC_MCO_CLK_DIV_MASK (~RCC_CFG_MCOPRES) +#define RCC_MCO_CLK_DIV1 (RCC_CFG_MCOPRES_DIV1) +#define RCC_MCO_CLK_DIV2 (RCC_CFG_MCOPRES_DIV2) +#define RCC_MCO_CLK_DIV3 (RCC_CFG_MCOPRES_DIV3) +#define RCC_MCO_CLK_DIV4 (RCC_CFG_MCOPRES_DIV4) +#define RCC_MCO_CLK_DIV5 (RCC_CFG_MCOPRES_DIV5) +#define RCC_MCO_CLK_DIV6 (RCC_CFG_MCOPRES_DIV6) +#define RCC_MCO_CLK_DIV7 (RCC_CFG_MCOPRES_DIV7) +#define RCC_MCO_CLK_DIV8 (RCC_CFG_MCOPRES_DIV8) +#define RCC_MCO_CLK_DIV9 (RCC_CFG_MCOPRES_DIV9) +#define RCC_MCO_CLK_DIV10 (RCC_CFG_MCOPRES_DIV10) +#define RCC_MCO_CLK_DIV11 (RCC_CFG_MCOPRES_DIV11) +#define RCC_MCO_CLK_DIV12 (RCC_CFG_MCOPRES_DIV12) +#define RCC_MCO_CLK_DIV13 (RCC_CFG_MCOPRES_DIV13) +#define RCC_MCO_CLK_DIV14 (RCC_CFG_MCOPRES_DIV14) +#define RCC_MCO_CLK_DIV15 (RCC_CFG_MCOPRES_DIV15) +#define RCC_MCO_CLK_DIV32 (RCC_CFG_MCOPRES_DIV32) + +/** RCC_Flag **/ +#define RCC_FLAG_HSI40MRDF ((uint8_t)0x20) +#define RCC_FLAG_HSI48MRDF ((uint8_t)0x21) +#define RCC_FLAG_LSIRDF ((uint8_t)0x41) +#define RCC_FLAG_LSIDETFF ((uint8_t)0x58) +#define RCC_FLAG_PINRST ((uint8_t)0x63) +#define RCC_FLAG_PORRST ((uint8_t)0x64) +#define RCC_FLAG_SFTRST ((uint8_t)0x65) +#define RCC_FLAG_IWDGRST ((uint8_t)0x66) +#define RCC_FLAG_LVRRST ((uint8_t)0x67) +#define RCC_FLAG_LPWRRST ((uint8_t)0x68) +#define RCC_FLAG_EMCCLAMPF ((uint8_t)0x6B) + +/** RCC Reset Flag clear**/ +#define RCC_REMOVE_RESET_FLAG (RCC_CTRLSTS_RMRSTF) + +void RCC_Reset(void); +void RCC_HSI_Calibration_Value_Set(uint8_t calibration_value); +void RCC_LSI_Calibration_Value_Set(uint8_t calibration_value); +void RCC_Sysclk_Config(uint32_t HSI_div); +void RCC_Hclk_Config(uint32_t sysclk_div); +void RCC_Pclk_Config(uint32_t hclk_div); +void RCC_TIM1_Clock_Config(uint32_t timer_clksrc); +void RCC_ADC_1M_Clock_Config(uint32_t ADC1M_prescaler); +void RCC_ADC_Clock_Config(uint32_t ADC_prescaler); +void RCC_TIM6_Clock_Config(uint32_t timer_clksrc); +void RCC_Clocks_Frequencies_Value_Get(RCC_ClocksType* RCC_clocks); +void RCC_AHB_Peripheral_Clock_Enable(uint32_t AHB_periph); +void RCC_AHB_Peripheral_Clock_Disable(uint32_t AHB_periph); +void RCC_APB_Peripheral_Clock_Enable(uint32_t APB_periph); +void RCC_APB_Peripheral_Clock_Disable(uint32_t APB_periph); +void RCC_Peripheral_Reset(uint32_t Periph); +void RCC_MCO_Prescaler_Config(uint32_t MCO_prescaler); +void RCC_MCO_Source_Config(uint32_t MCO_source); +FlagStatus RCC_Flag_Status_Get(uint8_t RCC_flag); +void RCC_Reset_Flag_Clear(void); +void RCC_EMC_Reset_Disable(void); +void RCC_EMC_Reset_Enable(void); +void RCC_EMC_Detect_Disable(void); +void RCC_EMC_Detect_Enable(void); +void RCC_LSI_Detect_Disable(void); +void RCC_LSI_Detect_Enable(void); +uint16_t RCC_LSI_Clocks_Frequencies_Get(void); + + +#ifdef __cplusplus +} +#endif + +#endif /* __N32G003_RCC_H__ */ + + diff --git a/firmware/n32g003_std_periph_driver/inc/n32g003_spi.h b/firmware/n32g003_std_periph_driver/inc/n32g003_spi.h new file mode 100644 index 0000000..732ecf1 --- /dev/null +++ b/firmware/n32g003_std_periph_driver/inc/n32g003_spi.h @@ -0,0 +1,207 @@ +/** +* Copyright (c) 2022, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + + +/** +*\*\file n32g003_spi.h +*\*\author Nations +*\*\version v1.0.0 +*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. +**/ +#ifndef __N32G003_SPI_H__ +#define __N32G003_SPI_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32g003.h" + +/** SPI Init structure definition **/ +typedef struct +{ + uint16_t DataDirection; /* Specifies the SPI unidirectional or bidirectional data mode */ + + uint16_t SpiMode; /* Specifies the SPI operating mode */ + + uint16_t DataLen; /* Specifies the SPI data size */ + + uint16_t CLKPOL; /* Specifies the serial clock steady state */ + + uint16_t CLKPHA; /* Specifies the clock active edge for the bit capture */ + + + uint16_t NSS; /* Specifies whether the NSS signal is managed by + hardware (NSS pin) or by software using the SSI bit */ + + + uint16_t BaudRatePres; /* Specifies the Baud Rate prescaler value which will be + used to configure the transmit and receive SCK clock */ + + uint16_t FirstBit; /* Specifies whether data transfers start from MSB or LSB bit */ +} SPI_InitType; + + +/** SPI_data_direction **/ +#define SPI_DATADIRECTION_MASK (~(SPI_CTRL1_RONLY | SPI_CTRL1_BIDIROEN | SPI_CTRL1_BIDIRMODE)) /* direction [15:14] and [10] bits Mask */ +#define SPI_DIR_DOUBLELINE_FULLDUPLEX ((uint16_t)0x0000) +#define SPI_DIR_DOUBLELINE_RONLY_TX ((uint16_t)0x0000) +#define SPI_DIR_DOUBLELINE_RONLY_RX (SPI_CTRL1_RONLY) +#define SPI_DIR_SINGLELINE_RX (SPI_CTRL1_BIDIRMODE) +#define SPI_DIR_SINGLELINE_TX (SPI_CTRL1_BIDIRMODE | SPI_CTRL1_BIDIROEN) + +/** SPI mode **/ +#define SPI_MODE_MASK (~SPI_CTRL1_MSEL) /* MSEL bits Mask */ +#define SPI_MODE_MASTER (SPI_CTRL1_MSEL) +#define SPI_MODE_SLAVE ((uint16_t)0x0000) + +/** SPI_data_size **/ +#define SPI_DATALEN_MASK (~SPI_CTRL1_DATFF) /* DATFF bits Mask */ +#define SPI_DATA_SIZE_16BITS (SPI_CTRL1_DATFF) +#define SPI_DATA_SIZE_8BITS ((uint16_t)0x0000) + +/** SPI_Clock_Polarity **/ +#define SPI_CLKPOL_MASK (~SPI_CTRL1_CLKPOL) /* CLKPOL bits Mask */ +#define SPI_CLKPOL_LOW ((uint16_t)0x0000) +#define SPI_CLKPOL_HIGH (SPI_CTRL1_CLKPOL) + +/** SPI_Clock_Phase **/ +#define SPI_CLKPHA_MASK (~SPI_CTRL1_CLKPHA) /* CLKPHA bits Mask */ +#define SPI_CLKPHA_FIRST_EDGE ((uint16_t)0x0000) +#define SPI_CLKPHA_SECOND_EDGE (SPI_CTRL1_CLKPHA) + +/** SPI_Slave_Select_management **/ +#define SPI_NSS_MASK (~SPI_CTRL1_SSMEN) /* SSMEN bits Mask */ +#define SPI_NSS_SOFT (SPI_CTRL1_SSMEN) +#define SPI_NSS_HARD ((uint16_t)0x0000) + +#define SPI_NSS_OUTPUT_ENABLE SPI_CTRL2_SSOEN +#define SPI_NSS_OUTPUT_DISABLE (~SPI_CTRL2_SSOEN) + +/** SPI_BaudRate_Prescaler **/ +#define SPI_BAUDRATEPRES_MASK (~SPI_CTRL1_BR) /* BR[2:0] bits Mask */ +#define SPI_BR_PRESCALER_2 ((uint16_t)0x0000) +#define SPI_BR_PRESCALER_4 (SPI_CTRL1_BR0) +#define SPI_BR_PRESCALER_8 (SPI_CTRL1_BR1) +#define SPI_BR_PRESCALER_16 (SPI_CTRL1_BR1 | SPI_CTRL1_BR0) +#define SPI_BR_PRESCALER_32 (SPI_CTRL1_BR2) +#define SPI_BR_PRESCALER_64 (SPI_CTRL1_BR2 | SPI_CTRL1_BR0) +#define SPI_BR_PRESCALER_128 (SPI_CTRL1_BR2 | SPI_CTRL1_BR1) +#define SPI_BR_PRESCALER_256 (SPI_CTRL1_BR2 | SPI_CTRL1_BR1 | SPI_CTRL1_BR0) + +/** SPI_MSB_LSB_transmission **/ +#define SPI_FIRSTBIT_MASK (~SPI_CTRL1_LSBFF) /* LSBFF bits Mask */ +#define SPI_FB_MSB ((uint16_t)0x0000) +#define SPI_FB_LSB (SPI_CTRL1_LSBFF) + +/** SPI Converter **/ +#define SPI_TURN_ON (SPI_CTRL1_SPIEN) /* SPIEN ON bit */ +#define SPI_TURN_OFF (~SPI_CTRL1_SPIEN) /* SPIEN ON bit Mask */ + +/** SPI_NSS_internal_software_management **/ +#define SPI_NSS_HIGH (SPI_CTRL1_SSEL) +#define SPI_NSS_LOW (~SPI_CTRL1_SSEL) + +/** SPI_flags_definition **/ +#define SPI_FLAG_RNE (SPI_STS_RNE) +#define SPI_FLAG_TE (SPI_STS_TE) +#define SPI_FLAG_MODERR (SPI_STS_MODERR) +#define SPI_FLAG_OVER (SPI_STS_OVER) +#define SPI_FLAG_BUSY (SPI_STS_BUSY) + +#define SPI_INT_RNE (SPI_CTRL2_RNEINTEN) +#define SPI_INT_TE (SPI_CTRL2_TEINTEN) +#define SPI_INT_ERR (SPI_CTRL2_ERRINTEN) + +#define SPI_INT_FLAG_RNE (SPI_STS_RNE) +#define SPI_INT_FLAG_TE (SPI_STS_TE) +#define SPI_INT_FLAG_MODERR (SPI_STS_MODERR) +#define SPI_INT_FLAG_OVER (SPI_STS_OVER) +#define SPI_INT_FLAG_ERR (SPI_STS_MODERR | SPI_STS_OVER) + +/** SPI Macro Definition End **/ + +/** SPI Driving Functions Declaration **/ + +void SPI_Reset(void); + +void SPI_ON(void); +void SPI_OFF(void); + +void SPI_Initializes_Structure(SPI_InitType* SPI_InitStruct); + +void SPI_DataDirection_Config(uint16_t DataDirection); +void SPI_SpiMode_Config(uint16_t SpiMode); +void SPI_DataLen_Config(uint16_t DataLen); +void SPI_CLKPOL_Config(uint16_t CLKPOL); +void SPI_CLKPHA_Config(uint16_t CLKPHA); +void SPI_NSS_Config(uint16_t NSS); +void SPI_BaudRatePres_Config(uint16_t BaudRatePres); +void SPI_FirstBit_Config(uint16_t FirstBit); +void SPI_Initializes(SPI_InitType* SPI_InitStruct); + +void SPI_Set_Nss_Level(uint16_t SPI_NSS_Internal_Soft); +void SPI_NSS_Output_Enable(void); +void SPI_NSS_Output_Disable(void); + +void SPI_Data_Transmit(uint16_t Data); +uint16_t SPI_Data_Get(void); + +void SPI_Interrupts_Enable(uint8_t spi_interrupt); +void SPI_Interrupts_Disable(uint8_t spi_interrupt); + +FlagStatus SPI_Flag_Status_Get(uint8_t spi_flag); +FlagStatus SPI_Interrupt_Flag_Status_Get(uint16_t spi_flag); +void SPI_OVER_Flag_Clear(void); + + +#ifdef __cplusplus +} +#endif + +#endif /*__N32G003_SPI_H__ */ + diff --git a/firmware/n32g003_std_periph_driver/inc/n32g003_tim.h b/firmware/n32g003_std_periph_driver/inc/n32g003_tim.h new file mode 100644 index 0000000..1deee5f --- /dev/null +++ b/firmware/n32g003_std_periph_driver/inc/n32g003_tim.h @@ -0,0 +1,716 @@ +/** +* Copyright (c) 2022, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** +*\*\file n32g003_tim.h +*\*\author Nations +*\*\version v1.0.0 +*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. +**/ +#ifndef __N32G003_TIM_H__ +#define __N32G003_TIM_H__ + +#ifdef __cplusplus +extern "C" { +#endif +#include "n32g003.h" +#include "stdbool.h" + + +/** +*\*\brief TIM Time Base Init structure definition +*\*\note This structure is used with all TIMx except for TIM6 and TIM7. +**/ + +typedef struct +{ + uint16_t Prescaler; /* Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t CntMode; /* Specifies the counter mode. + This parameter can be a value of TIM_Counter_Mode */ + + uint16_t Period; /* Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter must be a number between 0x0000 and 0xFFFF. */ + + uint16_t ClkDiv; /* Specifies the clock division. + This parameter can be a value of TIM_Clock_Division_CKD */ + + uint8_t RepetCnt; /* Specifies the repetition counter value. Each time the REPCNT downcounter + reaches zero, an update event is generated and counting restarts + from the REPCNT value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + This parameter must be a number between 0x00 and 0xFF. + @note This parameter is valid only for TIM1 and TIM8. */ + + bool CapCh1Sel; /* channel 1 select capture in from comp if 1, from IOM if 0 + Tim1,Tim3 valid*/ + bool CapEtrClrFromCompEn; /* etr clearref select from comp if 1, from ETR IOM if 0 + Tim1,Tim3 valid*/ + bool CapEtrSelFromTscEn; +} TIM_TimeBaseInitType; + +/** +*\*\brief TIM Output Compare Init structure definition +**/ + +typedef struct +{ + uint16_t OcMode; /* Specifies the TIM mode. + This parameter can be a value of TIM_Output_Compare_and_PWM_modes */ + + uint16_t OutputState; /* Specifies the TIM Output Compare state. + This parameter can be a value of TIM_Output_Compare_state */ + + uint16_t OutputNState; /* Specifies the TIM complementary Output Compare state. + This parameter can be a value of TIM_Output_Compare_N_state + - note This parameter is valid only for TIM1. */ + + uint16_t Pulse; /* Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t OcPolarity; /* Specifies the output polarity. + This parameter can be a value of TIM_Output_Compare_Polarity */ + + uint16_t OcNPolarity; /* Specifies the complementary output polarity. + This parameter can be a value of TIM_Output_Compare_N_Polarity + - note This parameter is valid only for TIM1. */ + + uint16_t OcIdleState; /* Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of TIM_Output_Compare_Idle_State + - note This parameter is valid only for TIM1. */ + + uint16_t OcNIdleState; /* Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of TIM_Output_Compare_N_Idle_State + - note This parameter is valid only for TIM1. */ +} OCInitType; + +/** +*\*\brief TIM Input Capture Init structure definition +**/ + +typedef struct +{ + uint16_t Channel; /*! Specifies the TIM channel.This parameter can be a value of Channel */ + + uint16_t IcPolarity; /* Specifies the active edge of the input signal. */ + + uint16_t IcSelection; /* Specifies the input. */ + + uint16_t IcPrescaler; /* Specifies the Input Capture Prescaler. */ + + uint16_t IcFilter; /* Specifies the input capture filter. */ +} TIM_ICInitType; + +/** +*\*\brief BKDT structure definition +*\*\note This structure is used only with TIM1 and TIM8. +**/ + +typedef struct +{ + uint16_t OssrState; /* Specifies the Off-State selection used in Run mode. + This parameter can be a value of OSSR_Off_State_Selection_for_Run_mode_state */ + + uint16_t OssiState; /* Specifies the Off-State used in Idle state. + This parameter can be a value of OSSI_Off_State_Selection_for_Idle_mode_state */ + + uint16_t LockLevel; /* Specifies the LOCK level parameters. + This parameter can be a value of Lock_level */ + + uint16_t DeadTime; /* Specifies the delay time between the switching-off and the + switching-on of the outputs. + This parameter can be a number between 0x00 and 0xFF */ + + uint16_t Break; /* Specifies whether the TIM Break input is enabled or not. + This parameter can be a value of Break_Input_enable_disable */ + + uint16_t BreakPolarity; /* Specifies the TIM Break Input pin polarity. + This parameter can be a value of Break_Polarity */ + + uint16_t AutomaticOutput; /* Specifies whether the TIM Automatic Output feature is enabled or not. + This parameter can be a value of TIM_AOE_Bit_Set_Reset */ + bool IomBreakEn; /* EXTENDMODE valid, open iom as break in*/ + bool LockUpBreakEn; /* EXTENDMODE valid, open lockup(hardfault) as break in*/ + bool PvdBreakEn; /* EXTENDMODE valid, open pvd(sys voltage too high or too low) as break in*/ +} TIM_BDTRInitType; + + + + +#define TIM_REG16_BIT_ZERO ((uint16_t)0x0000) +#define TIM_REG32_BIT_ZERO ((uint32_t)0x00000000) + +#define TIM_AR_PRELOAD_MASK (TIM_CTRL1_ARPEN) +/** TIM_AR_PRELOAD **/ +#define TIM_AR_PRELOAD_ENABLE (TIM_CTRL1_ARPEN) +#define TIM_AR_PRELOAD_DISABLE (TIM_REG32_BIT_ZERO) + +#define TIM_UPRS_MASK (TIM_CTRL1_UPRS) +/** TIM_Update_Source **/ +#define TIM_UPRS_GLOBAL (TIM_REG32_BIT_ZERO) +#define TIM_UPRS_REGULAR (TIM_CTRL1_UPRS) + +#define TIM_UPDATE_SRC_GLOBAL (TIM_REG16_BIT_ZERO) /* Source of update is the counter overflow/underflow \ + or the setting of UG bit, or an update generation \ + through the slave mode controller. */ +#define TIM_UPDATE_SRC_REGULAR ((uint16_t)0x0001) /* Source of update is counter overflow/underflow. */ + +#define TIM_UPDIS_MASK (TIM_CTRL1_UPDIS) +/** TIM_Update_Disable **/ +#define TIM_UPDATE_EVENT_DISABLE (TIM_CTRL1_UPDIS) +#define TIM_UPDATE_EVENT_ENABLE (TIM_REG32_BIT_ZERO) + +#define TIM_ON_MASK (TIM_CTRL1_CNTEN) +/** TIM_On **/ +#define TIM_ON (TIM_CTRL1_CNTEN) + +/* TIM_Break_In_Source */ +#define TIM_LOCKUP_AS_BREAK_IN (TIM_CTRL1_LBKPEN) +#define TIM_PVD_AS_BREAK_IN (TIM_CTRL1_PBKPEN) +#define TIM_COMP_AS_BREAK_IN (TIM_CTRL1_IOMBKPEN) + +#define TIM_CCUSEL_MASK (TIM_CTRL2_CCUSEL) +/** TIM_CCUSEL **/ +#define TIM_CCUSEL_COM_AND_TRIG (TIM_CTRL2_CCUSEL) +#define TIM_CCUSEL_COM (TIM_REG32_BIT_ZERO) + +/** TIM_CCPCTL **/ +#define TIM_CCPCTL_MASK (TIM_CTRL2_CCPCTL) +#define TIM_CCPCTL_PRELOAD (TIM_CTRL2_CCPCTL) +#define TIM_CCPCTL_NOT_PRELOAD (TIM_REG32_BIT_ZERO) + +/** TIM_REPCNT MASK**/ +#define TIM_REPCNT_MASK (TIM_REPCNT_REPCNT) + +#define TIM_OC1MODE_MASK (TIM_CCMOD1_OC1MD) +#define TIM_OC2MODE_MASK (TIM_CCMOD1_OC2MD) +#define TIM_OC3MODE_MASK (TIM_CCMOD2_OC3MD) +#define TIM_OC4MODE_MASK (TIM_CCMOD2_OC4MD) +#define TIM_OC5MODE_MASK (TIM_CCMOD3_OC5MD) +/** TIM_Output_Compare_and_PWM_modes**/ +#define TIM_OCMODE_TIMING (TIM_REG16_BIT_ZERO) +#define TIM_OCMODE_ACTIVE (TIM_CCMOD1_OC1MD_0) +#define TIM_OCMODE_INACTIVE (TIM_CCMOD1_OC1MD_1) +#define TIM_OCMODE_TOGGLE (TIM_CCMOD1_OC1MD_0 | TIM_CCMOD1_OC1MD_1) +#define TIM_OCMODE_PWM1 (TIM_CCMOD1_OC1MD_2 | TIM_CCMOD1_OC1MD_1) +#define TIM_OCMODE_PWM2 (TIM_CCMOD1_OC1MD_2 | TIM_CCMOD1_OC1MD_1 | TIM_CCMOD1_OC1MD_2 | TIM_CCMOD1_OC1MD_0) +#define TIM_FORCED_ACTION_ACTIVE (TIM_CCMOD1_OC1MD_2 | TIM_CCMOD1_OC1MD_0) +#define TIM_FORCED_ACTION_INACTIVE (TIM_CCMOD1_OC1MD_2) + +#define TIM_OPMODE_MASK (TIM_CTRL1_ONEPM) +/** TIM_One_Pulse_Mode **/ +#define TIM_OPMODE_SINGLE (TIM_CTRL1_ONEPM) +#define TIM_OPMODE_REPET (TIM_REG16_BIT_ZERO) + +/** Channel **/ +#define TIM_CH_1 ((uint16_t)0x0000) +#define TIM_CH_2 ((uint16_t)0x0004) +#define TIM_CH_3 ((uint16_t)0x0008) +#define TIM_CH_4 ((uint16_t)0x000C) +#define TIM_CH_5 ((uint16_t)0x0010) + +#define TIM_CLK_DIV_MASK (TIM_CTRL1_CLKD) +/** TIM_Clock_Division_CKD **/ +#define TIM_CLK_DIV1 (TIM_REG16_BIT_ZERO) +#define TIM_CLK_DIV2 (TIM_CTRL1_CLKD_0) +#define TIM_CLK_DIV4 (TIM_CTRL1_CLKD_1) + +#define TIM_CNT_MODE_MASK (TIM_CTRL1_DIR | TIM_CTRL1_CAMSEL) +/** TIM_Counter_Mode **/ +#define TIM_CNT_MODE_UP (TIM_REG16_BIT_ZERO) +#define TIM_CNT_MODE_DOWN (TIM_CTRL1_DIR) +#define TIM_CNT_MODE_CENTER_ALIGN1 (TIM_CTRL1_CAMSEL_0) +#define TIM_CNT_MODE_CENTER_ALIGN2 (TIM_CTRL1_CAMSEL_1) +#define TIM_CNT_MODE_CENTER_ALIGN3 (TIM_CTRL1_CAMSEL_1 | TIM_CTRL1_CAMSEL_0) + + + + + +/** TIM_CHxSEL **/ +#define TIM_CH1_SEL (TIM_CTRL1_C1SEL) + + +/** TIM_OCREF_CLEAR_SEL **/ +#define TIM_OCREF_CLEAR_SEL (TIM_CTRL1_CLRSEL) + +/** TIM_TI1_SEL **/ +#define TIM_TI1_SEL (TIM_CTRL2_TI1SEL) + + +/** TIM_ETR_Selection **/ +#define TIM_ETR_SEL (TIM_CTRL2_TSCSEL) + + +#define TIM_OC_POLARITY_MASK (TIM_CCEN_CC1P) +/** TIM_Output_Compare_Polarity **/ +#define TIM_OC_POLARITY_HIGH (TIM_REG16_BIT_ZERO) +#define TIM_OC_POLARITY_LOW (TIM_CCEN_CC1P) + +#define TIM_OCN_POLARITY_MASK (TIM_CCEN_CC1NP) +/** TIM_Output_Compare_N_Polarity **/ +#define TIM_OCN_POLARITY_HIGH (TIM_REG16_BIT_ZERO) +#define TIM_OCN_POLARITY_LOW (TIM_CCEN_CC1NP) + +/** TIM_Output_Compare_state **/ +#define TIM_OUTPUT_STATE_DISABLE (TIM_REG16_BIT_ZERO) +#define TIM_OUTPUT_STATE_ENABLE (TIM_CCEN_CC1EN) + +/** TIM_Output_Compare_N_state **/ +#define TIM_OUTPUT_NSTATE_DISABLE (TIM_REG16_BIT_ZERO) +#define TIM_OUTPUT_NSTATE_ENABLE (TIM_CCEN_CC1NEN) + +/** TIM_Capture_Compare_state **/ +#define TIM_CAP_CMP_ENABLE (TIM_CCEN_CC1EN) +#define TIM_CAP_CMP_DISABLE (TIM_REG16_BIT_ZERO) + +/** TIM_Capture_Compare_N_state **/ +#define TIM_CAP_CMP_N_ENABLE (TIM_CCEN_CC1NEN) +#define TIM_CAP_CMP_N_DISABLE (TIM_REG16_BIT_ZERO) + +/** Break_Input_enable_disable **/ +#define TIM_BREAK_IN_ENABLE (TIM_BKDT_BKEN) +#define TIM_BREAK_IN_DISABLE (TIM_REG16_BIT_ZERO) + +/** Break_Polarity **/ +#define TIM_BREAK_POLARITY_LOW (TIM_REG16_BIT_ZERO) +#define TIM_BREAK_POLARITY_HIGH (TIM_BKDT_BKP) + +/** TIM_AOEN_Bit_Set_Reset **/ +#define TIM_AUTO_OUTPUT_ENABLE (TIM_BKDT_AOEN) +#define TIM_AUTO_OUTPUT_DISABLE (TIM_REG16_BIT_ZERO) + +/** TIM_MOEN_Bit_Set_Reset **/ +#define TIM_MAIN_OUTPUT_ENABLE (TIM_BKDT_MOEN) +#define TIM_MAIN_OUTPUT_DISABLE (TIM_REG16_BIT_ZERO) + +/** Lock_level **/ +#define TIM_LOCK_LEVEL_OFF (TIM_REG16_BIT_ZERO) +#define TIM_LOCK_LEVEL_1 (TIM_BKDT_LCKCFG_0) +#define TIM_LOCK_LEVEL_2 (TIM_BKDT_LCKCFG_1) +#define TIM_LOCK_LEVEL_3 (TIM_BKDT_LCKCFG_1 | TIM_BKDT_LCKCFG_0) + +/** OSSI_Off_State_Selection_for_Idle_mode_state **/ +#define TIM_OSSI_STATE_ENABLE (TIM_BKDT_OSSI) +#define TIM_OSSI_STATE_DISABLE (TIM_REG16_BIT_ZERO) + +/** OSSR_Off_State_Selection_for_Run_mode_state **/ +#define TIM_OSSR_STATE_ENABLE (TIM_BKDT_OSSR) +#define TIM_OSSR_STATE_DISABLE (TIM_REG16_BIT_ZERO) + +#define TIM_OC1_IDLE_STATE_MASK (TIM_CTRL2_OI1) +#define TIM_OC2_IDLE_STATE_MASK (TIM_CTRL2_OI2) +#define TIM_OC3_IDLE_STATE_MASK (TIM_CTRL2_OI3) +#define TIM_OC4_IDLE_STATE_MASK (TIM_CTRL2_OI4) +#define TIM_OC5_IDLE_STATE_MASK (TIM_CTRL2_OI5) +/** TIM_Output_Compare_Idle_State **/ +#define TIM_OC_IDLE_STATE_SET (TIM_CTRL2_OI1) +#define TIM_OC_IDLE_STATE_RESET (TIM_REG16_BIT_ZERO) + +#define TIM_OC1N_IDLE_STATE_MASK (TIM_CTRL2_OI1N) +#define TIM_OC2N_IDLE_STATE_MASK (TIM_CTRL2_OI2N) +#define TIM_OC3N_IDLE_STATE_MASK (TIM_CTRL2_OI3N) +/** TIM_Output_Compare_N_Idle_State **/ +#define TIM_OCN_IDLE_STATE_SET (TIM_CTRL2_OI1N) +#define TIM_OCN_IDLE_STATE_RESET (TIM_REG16_BIT_ZERO) + +/** TIM_Input_Capture_Polarity **/ +#define TIM_IC_POLARITY_RISING (TIM_REG16_BIT_ZERO) +#define TIM_IC_POLARITY_FALLING (TIM_CCEN_CC1P) +#define TIM_IC_POLARITY_BOTHEDGE (TIM_CCEN_CC1P | TIM_CCEN_CC1NP) + +#define TIM_IC1_SELECTION_MASK (TIM_CCMOD1_CC1SEL) +#define TIM_IC2_SELECTION_MASK (TIM_CCMOD1_CC2SEL) +#define TIM_IC3_SELECTION_MASK (TIM_CCMOD2_CC3SEL) +#define TIM_IC4_SELECTION_MASK (TIM_CCMOD2_CC4SEL) +/** TIM_Input_Capture_Selection **/ +#define TIM_IC_SELECTION_DIRECTTI (TIM_CCMOD1_CC1SEL_0) /* TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_IC_SELECTION_INDIRECTTI (TIM_CCMOD1_CC1SEL_1) /* TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively. */ +#define TIM_IC_SELECTION_TRC (TIM_CCMOD1_CC1SEL_1 | TIM_CCMOD1_CC1SEL_0) /* TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ + +/** TIM_Input_Capture1_Filter **/ +#define TIM_IC1_FILTER_MASK (TIM_CCMOD1_IC1F) + +/** TIM_Input_Capture2_Filter **/ +#define TIM_IC2_FILTER_MASK (TIM_CCMOD1_IC2F) + +/** TIM_Input_Capture3_Filter **/ +#define TIM_IC3_FILTER_MASK (TIM_CCMOD2_IC3F) + +/** TIM_Input_Capture4_Filter **/ +#define TIM_IC4_FILTER_MASK (TIM_CCMOD2_IC4F) + +#define TIM_IC1_PSC_MASK (TIM_CCMOD1_IC1PSC) +#define TIM_IC2_PSC_MASK (TIM_CCMOD1_IC2PSC) +#define TIM_IC3_PSC_MASK (TIM_CCMOD2_IC3PSC) +#define TIM_IC4_PSC_MASK (TIM_CCMOD2_IC4PSC) +/** TIM_Input_Capture_Prescaler **/ +#define TIM_IC_PSC_DIV1 (TIM_REG16_BIT_ZERO) +#define TIM_IC_PSC_DIV2 (TIM_CCMOD1_IC1PSC_0) /* Capture performed once every 2 events. */ +#define TIM_IC_PSC_DIV4 (TIM_CCMOD1_IC1PSC_1) /* Capture performed once every 4 events. */ +#define TIM_IC_PSC_DIV8 (TIM_CCMOD1_IC1PSC_1 | TIM_CCMOD1_IC1PSC_0) /* Capture performed once every 8 events. */ + +/** TIM_interrupt_sources **/ +#define TIM_INT_UPDATE (TIM_STS_UDITF) +#define TIM_INT_CC1 (TIM_STS_CC1ITF) +#define TIM_INT_CC2 (TIM_STS_CC2ITF) +#define TIM_INT_CC3 (TIM_STS_CC3ITF) +#define TIM_INT_CC4 (TIM_STS_CC4ITF) +#define TIM_INT_COM (TIM_STS_COMITF) +#define TIM_INT_TRIG (TIM_STS_TITF) +#define TIM_INT_BREAK (TIM_STS_BITF) + + +/** TIM_External_Trigger_Prescaler **/ +#define TIM_EXT_TRG_PSC_MASK (TIM_SMCTRL_EXTPS) +#define TIM_EXT_TRG_PSC_OFF (TIM_REG16_BIT_ZERO) +#define TIM_EXT_TRG_PSC_DIV2 (TIM_SMCTRL_EXTPS_0) +#define TIM_EXT_TRG_PSC_DIV4 (TIM_SMCTRL_EXTPS_1) +#define TIM_EXT_TRG_PSC_DIV8 (TIM_SMCTRL_EXTPS_1 | TIM_SMCTRL_EXTPS_0) + +#define TIM_TRIG_SEL_MASK (TIM_SMCTRL_TSEL) +/** TIM_Internal_Trigger_Selection **/ +#define TIM_TRIG_SEL_IN_TR0 (TIM_REG16_BIT_ZERO) +#define TIM_TRIG_SEL_IN_TR1 (TIM_SMCTRL_TSEL_0) +#define TIM_TRIG_SEL_IN_TR2 (TIM_SMCTRL_TSEL_1) +#define TIM_TRIG_SEL_IN_TR3 (TIM_SMCTRL_TSEL_1 | TIM_SMCTRL_TSEL_0) +#define TIM_TRIG_SEL_TI1F_ED (TIM_SMCTRL_TSEL_2) +#define TIM_TRIG_SEL_TI1FP1 (TIM_SMCTRL_TSEL_2 | TIM_SMCTRL_TSEL_0) +#define TIM_TRIG_SEL_TI2FP2 (TIM_SMCTRL_TSEL_2 | TIM_SMCTRL_TSEL_1) +#define TIM_TRIG_SEL_ETRF (TIM_SMCTRL_TSEL_2 | TIM_SMCTRL_TSEL_1 | TIM_SMCTRL_TSEL_0) + +/** TIM_TIx_External_Clock_Source **/ +#define TIM_EXT_CLK_SRC_TI1 (TIM_SMCTRL_TSEL_2 | TIM_SMCTRL_TSEL_0) +#define TIM_EXT_CLK_SRC_TI2 (TIM_SMCTRL_TSEL_2 | TIM_SMCTRL_TSEL_1) +#define TIM_EXT_CLK_SRC_TI1ED (TIM_SMCTRL_TSEL_2) + +/** TIM_External_Trigger_Polarity **/ +#define TIM_EXT_TRIG_POLARITY_INVERTED (TIM_SMCTRL_EXTP) +#define TIM_EXT_TRIG_POLARITY_NONINVERTED (TIM_REG16_BIT_ZERO) + +/** TIM_TIx_External_Clock_Filter **/ +#define TIM_EXT_TRIG_FILTER_MASK (TIM_SMCTRL_EXTF) + +/** TIM_External_Clock_Mode2 **/ +#define TIM_EXT_CLOCK_MODE2_ENABLE (TIM_SMCTRL_EXCEN) + +#define TIM_PSC_RELOAD_MODE_MASK (TIM_EVTGEN_UDGN) +/** TIM_Prescaler_Reload_Mode **/ +#define TIM_PSC_RELOAD_MODE_UPDATE (TIM_REG16_BIT_ZERO) +#define TIM_PSC_RELOAD_MODE_IMMEDIATE (TIM_EVTGEN_UDGN) + + + +/** TIM_Event_Source **/ +#define TIM_EVT_SRC_UPDATE (TIM_EVTGEN_UDGN) +#define TIM_EVT_SRC_CC1 (TIM_EVTGEN_CC1GN) +#define TIM_EVT_SRC_CC2 (TIM_EVTGEN_CC2GN) +#define TIM_EVT_SRC_CC3 (TIM_EVTGEN_CC3GN) +#define TIM_EVT_SRC_CC4 (TIM_EVTGEN_CC4GN) +#define TIM_EVT_SRC_COM (TIM_EVTGEN_CCUDGN) +#define TIM_EVT_SRC_TRIG (TIM_EVTGEN_TGN) +#define TIM_EVT_SRC_BREAK (TIM_EVTGEN_BGN) + +#define TIM_OC1_PRELOAD_MASK (TIM_CCMOD1_OC1PEN) +#define TIM_OC2_PRELOAD_MASK (TIM_CCMOD1_OC2PEN) +#define TIM_OC3_PRELOAD_MASK (TIM_CCMOD2_OC3PEN) +#define TIM_OC4_PRELOAD_MASK (TIM_CCMOD2_OC4PEN) +#define TIM_OC5_PRELOAD_MASK (TIM_CCMOD3_OC5PEN) +/** TIM_Output_Compare_Preload_State **/ +#define TIM_OC_PRELOAD_ENABLE (TIM_CCMOD1_OC1PEN) +#define TIM_OC_PRELOAD_DISABLE (TIM_REG16_BIT_ZERO) + + + + +#define TIM_OC1_FAST_MASK (TIM_CCMOD1_OC1FEN) +#define TIM_OC2_FAST_MASK (TIM_CCMOD1_OC2FEN) +#define TIM_OC3_FAST_MASK (TIM_CCMOD2_OC3FEN) +#define TIM_OC4_FAST_MASK (TIM_CCMOD2_OC4FEN) +#define TIM_OC5_FAST_MASK (TIM_CCMOD3_OC5FEN) +/** TIM_Output_Compare_Fast_State **/ +#define TIM_OC_FAST_ENABLE (TIM_CCMOD1_OC1FEN) +#define TIM_OC_FAST_DISABLE (TIM_REG16_BIT_ZERO) + + +#define TIM_OC1_CLEAR_MASK (TIM_CCMOD1_OC1CEN) +#define TIM_OC2_CLEAR_MASK (TIM_CCMOD1_OC2CEN) +#define TIM_OC3_CLEAR_MASK (TIM_CCMOD2_OC3CEN) +#define TIM_OC4_CLEAR_MASK (TIM_CCMOD2_OC4CEN) +#define TIM_OC5_CLEAR_MASK (TIM_CCMOD3_OC5CEN) +/** TIM_Output_Compare_Clear_State **/ +#define TIM_OC_CLEAR_ENABLE (TIM_CCMOD1_OC1CEN) +#define TIM_OC_CLEAR_DISABLE (TIM_REG16_BIT_ZERO) + +#define TIM_TRGO_SRC_MASK (TIM_CTRL2_MMSEL) +/** TIM_Trigger_Output_Source **/ +#define TIM_TRGO_SRC_RESET (TIM_REG16_BIT_ZERO) +#define TIM_TRGO_SRC_ENABLE (TIM_CTRL2_MMSEL_0) +#define TIM_TRGO_SRC_UPDATE (TIM_CTRL2_MMSEL_1) +#define TIM_TRGO_SRC_OC1 (TIM_CTRL2_MMSEL_1 | TIM_CTRL2_MMSEL_0) +#define TIM_TRGO_SRC_OC1REF (TIM_CTRL2_MMSEL_2) +#define TIM_TRGO_SRC_OC2REF (TIM_CTRL2_MMSEL_2 | TIM_CTRL2_MMSEL_0) +#define TIM_TRGO_SRC_OC3REF (TIM_CTRL2_MMSEL_2 | TIM_CTRL2_MMSEL_1) +#define TIM_TRGO_SRC_OC4REF (TIM_CTRL2_MMSEL_2 | TIM_CTRL2_MMSEL_1 | TIM_CTRL2_MMSEL_0) + +/** ETR selection **/ +#define TIM_ETR_Seletct_ExtGpio (TIM_REG16_BIT_ZERO) +#define TIM_ETR_Seletct_innerTsc (TIM_CTRL2_TSCSEL) + +#define TIM_SLAVE_MODE_MASK (TIM_SMCTRL_SMSEL) +/** TIM_Slave_Mode **/ +#define TIM_SLAVE_MODE_RESET (TIM_SMCTRL_SMSEL_2) +#define TIM_SLAVE_MODE_GATED (TIM_SMCTRL_SMSEL_2 | TIM_SMCTRL_SMSEL_0) +#define TIM_SLAVE_MODE_TRIG (TIM_SMCTRL_SMSEL_2 | TIM_SMCTRL_SMSEL_1) +#define TIM_SLAVE_MODE_EXT1 (TIM_SMCTRL_SMSEL_2 | TIM_SMCTRL_SMSEL_1 | TIM_SMCTRL_SMSEL_0) + +#define TIM_MASTER_SLAVE_MODE_MASK (TIM_SMCTRL_MSMD) +/** TIM_Master_Slave_Mode **/ +#define TIM_MASTER_SLAVE_MODE_ENABLE (TIM_SMCTRL_MSMD) +#define TIM_MASTER_SLAVE_MODE_DISABLE (TIM_REG16_BIT_ZERO) + +/** TIM_Flags **/ +#define TIM_FLAG_UPDATE (TIM_STS_UDITF) +#define TIM_FLAG_CC1 (TIM_STS_CC1ITF) +#define TIM_FLAG_CC2 (TIM_STS_CC2ITF) +#define TIM_FLAG_CC3 (TIM_STS_CC3ITF) +#define TIM_FLAG_CC4 (TIM_STS_CC4ITF) +#define TIM_FLAG_COM (TIM_STS_COMITF) +#define TIM_FLAG_TRIG (TIM_STS_TITF) +#define TIM_FLAG_BREAK (TIM_STS_BITF) +#define TIM_FLAG_CC1OF (TIM_STS_CC1OCF) +#define TIM_FLAG_CC2OF (TIM_STS_CC2OCF) +#define TIM_FLAG_CC3OF (TIM_STS_CC3OCF) +#define TIM_FLAG_CC4OF (TIM_STS_CC4OCF) +#define TIM_FLAG_CC5 (TIM_STS_CC5ITF) + +/** TIM_CCxEN **/ +#define TIM_CC1EN (TIM_CCEN_CC1EN) +#define TIM_CC1NEN (TIM_CCEN_CC1NEN) +#define TIM_CC2EN (TIM_CCEN_CC2EN) +#define TIM_CC2NEN (TIM_CCEN_CC2NEN) +#define TIM_CC3EN (TIM_CCEN_CC3EN) +#define TIM_CC3NEN (TIM_CCEN_CC3NEN) +#define TIM_CC4EN (TIM_CCEN_CC4EN) +#define TIM_CC5EN (TIM_CCEN_CC5EN) + + +/** TIM_CCxP **/ +#define TIM_CC1P (TIM_CCEN_CC1P) +#define TIM_CC1NP (TIM_CCEN_CC1NP) +#define TIM_CC2P (TIM_CCEN_CC2P) +#define TIM_CC2NP (TIM_CCEN_CC2NP) +#define TIM_CC3P (TIM_CCEN_CC3P) +#define TIM_CC3NP (TIM_CCEN_CC3NP) +#define TIM_CC4P (TIM_CCEN_CC4P) +#define TIM_CC5P (TIM_CCEN_CC5P) + +/* TIM_CCDATx*/ +#define TIM_CCDAT1_MASK (TIM_CCDAT1_CCDAT1) +#define TIM_CCDAT2_MASK (TIM_CCDAT2_CCDAT2) +#define TIM_CCDAT3_MASK (TIM_CCDAT3_CCDAT3) +#define TIM_CCDAT4_MASK (TIM_CCDAT4_CCDAT4) + + +/* ---------------------- TIM registers bit mask ------------------------ */ +#define SMCTRL_ETRP_MASK ((uint16_t)0x8000) +#define SMCTRL_ETRCEN_MASK ((uint16_t)0x4000) +#define SMCTRL_ETRPSC_MASK ((uint16_t)0x3000) +#define SMCTRL_ETRFIL_MASK ((uint16_t)0x0f00) +#define CAPCMPMOD_OFFSET ((uint16_t)0x0018) +#define CAPCMPEN_CCE_SET ((uint16_t)0x0001) +#define CAPCMPEN_CCNE_SET ((uint16_t)0x0004) + + +void TIM_Reset(TIM_Module* TIMx); + +/** TIM_Base functions **/ +void TIM_Base_Count_Mode_Set(TIM_Module* TIMx, uint32_t cnt_mode); + +/* function in N32G003 */ +void TIM_Base_Auto_Reload_Set(TIM_Module* TIMx, uint16_t auto_reload); +void TIM_Base_Prescaler_Set(TIM_Module* TIMx, uint16_t prescaler); +void TIM_Base_Reload_Mode_Set(TIM_Module* TIMx, uint16_t reload_mode); +void TIM_Base_Count_Set(TIM_Module* TIMx, uint16_t count); +uint16_t TIM_Base_Count_Get(TIM_Module* TIMx); +uint16_t TIM_Auto_Reload_Get(TIM_Module* TIMx); +uint16_t TIM_Base_Prescaler_Get(TIM_Module* TIMx); +void TIM_Base_Repeat_Count_Set(TIM_Module* TIMx, uint8_t repeat_cnt); +void TIM_Base_Channel1(TIM_Module* TIMx, bool channel_selection); +void TIM_Base_OCrefClear(TIM_Module* TIMx, bool OCrefClear_selection); +void TIM_Base_Initialize(TIM_Module* TIMx, TIM_TimeBaseInitType* TIM_TimeBaseInitStruct); +void TIM_Base_Struct_Initialize(TIM_TimeBaseInitType* TIM_TimeBaseInitStruct); +void TIM_On(TIM_Module* TIMx); +void TIM_Off(TIM_Module* TIMx); + +/** Preload functions **/ +void TIM_Output_Channel1_Preload_Set(TIM_Module* TIMx, uint16_t TIM_output_channel_preload); +void TIM_Output_Channel2_Preload_Set(TIM_Module* TIMx, uint16_t TIM_output_channel_preload); +void TIM_Output_Channel3_Preload_Set(TIM_Module* TIMx, uint16_t TIM_output_channel_preload); +void TIM_Output_Channel4_Preload_Set(TIM_Module* TIMx, uint16_t TIM_output_channel_preload); +void TIM_Output_Channel5_Preload_Set(TIM_Module* TIMx, uint16_t TIM_output_channel_preload); +void TIM_Auto_Reload_Preload_Enable(TIM_Module* TIMx); +void TIM_Auto_Reload_Preload_Disable(TIM_Module* TIMx); +void TIM_Update_Event_Enable(TIM_Module* TIMx); +void TIM_Update_Event_Disable(TIM_Module* TIMx); +void TIM_Update_Request_Source_Set(TIM_Module* TIMx, uint16_t TIM_update_source); +void TIM_Event_Generate(TIM_Module* TIMx, uint16_t TIM_event_source); +void TIM_Commutation_Event_Enable(TIM_Module* TIMx); +void TIM_Commutation_Event_Disable(TIM_Module* TIMx); +void TIM_Capture_Compare_Control_Preload_Enable(TIM_Module* TIMx); +void TIM_Capture_Compare_Control_Preload_Disable(TIM_Module* TIMx); + +/** Channel functions **/ +void TIM_Compare1_Set(TIM_Module* TIMx, uint16_t compare1); +void TIM_Compare2_Set(TIM_Module* TIMx, uint16_t compare2); +void TIM_Compare3_Set(TIM_Module* TIMx, uint16_t compare3); +void TIM_Compare4_Set(TIM_Module* TIMx, uint16_t compare4); +void TIM_Compare5_Set(TIM_Module* TIMx, uint16_t compare5); +uint16_t TIM_Compare_Capture1_Get(TIM_Module* TIMx); +uint16_t TIM_Compare_Capture2_Get(TIM_Module* TIMx); +uint16_t TIM_Compare_Capture3_Get(TIM_Module* TIMx); +uint16_t TIM_Compare_Capture4_Get(TIM_Module* TIMx); +uint16_t TIM_Compare_Capture5_Get(TIM_Module* TIMx); +FlagStatus TIM_CCEN_Status_Get(TIM_Module* TIMx, uint32_t TIM_CCEN); + +/** Chanel input&Cascade functions **/ +void TIM_Trigger_Source_Select(TIM_Module* TIMx, uint16_t TIM_trigger_source); +void Input_Channel1_Config(TIM_Module* TIMx, uint16_t input_channel_polarity, + uint16_t input_channel_selection, uint16_t input_channel_filter); +void Input_Channel2_Config(TIM_Module* TIMx, uint16_t input_channel_polarity, + uint16_t input_channel_selection, uint16_t input_channel_filter); +void Input_Channel3_Config(TIM_Module* TIMx, uint16_t input_channel_polarity, + uint16_t input_channel_selection, uint16_t input_channel_filter); +void Input_Channel4_Config(TIM_Module* TIMx, uint16_t input_channel_polarity, + uint16_t input_channel_selection, uint16_t input_channel_filter); +void TIM_External_Trigger_Polarity_Set(TIM_Module* TIMx, + uint16_t external_trigger_polarity); +void TIM_External_Trigger_Filter_Set(TIM_Module* TIMx, + uint16_t external_trigger_filter); +void TIM_External_Trigger_Prescaler_Set(TIM_Module* TIMx, + uint16_t external_trigger_prescaler); +void TIM_Clock_Division_Set(TIM_Module* TIMx, uint16_t clock_division); +void TIM_Internal_Clock_Set(TIM_Module* TIMx); +void TIM_Input_Capture1_Prescaler_Set(TIM_Module* TIMx, uint16_t TIM_input_capture_prescaler); +void TIM_Input_Capture2_Prescaler_Set(TIM_Module* TIMx, uint16_t TIM_input_capture_prescaler); +void TIM_Input_Capture3_Prescaler_Set(TIM_Module* TIMx, uint16_t TIM_input_capture_prescaler); +void TIM_Input_Capture4_Prescaler_Set(TIM_Module* TIMx, uint16_t TIM_input_capture_prescaler); +void TIM_Internal_Trig_To_Ext_Set(TIM_Module* TIMx, uint16_t input_trigger_source); +void TIM_Trigger_As_External_Clock(TIM_Module* TIMx, uint16_t external_clock_source, uint16_t input_channel_polarity, uint16_t input_channel_filter); +void TIM_External_Clock_Mode1_Set(TIM_Module* TIMx, uint16_t external_trigger_prescaler, uint16_t external_trigger_polarity, uint16_t external_trigger_filter); +void TIM_External_Clock_Mode2_Set(TIM_Module* TIMx, uint16_t external_trigger_prescaler, uint16_t external_trigger_polarity, uint16_t external_trigger_filter); +void TIM_Slave_Mode_Select(TIM_Module* TIMx, uint16_t TIM_slave_mode); +void TIM_Master_Slave_Mode_Set(TIM_Module* TIMx, uint16_t TIM_master_slave_mode); +void TIM_Output_Trigger_Select(TIM_Module* TIMx, uint16_t TIM_trigger_output_source); +void TIM_One_Pulse_Mode_Select(TIM_Module* TIMx, uint16_t TIM_one_pulse_mode); +void TIM_Input_Channel_Initialize(TIM_Module* TIMx, TIM_ICInitType* TIM_ICInitStruct); +void TIM_PWM_Input_Channel_Config(TIM_Module* TIMx, TIM_ICInitType* TIM_ICInitStruct); +void TIM_Input_Struct_Initialize(TIM_ICInitType* TIM_ICInitStruct); + +/** Channel output functions **/ +void TIM_Output_Channel_Polarity_Set(TIM_Module* TIMx, uint32_t output_channel_polarity, uint16_t channel); +void TIM_Output_Channel_N_Polarity_Set(TIM_Module* TIMx, uint32_t output_channel_N_polarity, uint16_t channel); +void TIM_Capture_Compare_Ch_Enable(TIM_Module* TIMx, uint16_t channel); +void TIM_Capture_Compare_Ch_Disable(TIM_Module* TIMx, uint16_t channel); +void TIM_Capture_Compare_Ch_N_Enable(TIM_Module* TIMx, uint16_t channel); +void TIM_Capture_Compare_Ch_N_Disable(TIM_Module* TIMx, uint16_t channel); +void TIM_Output_Channel_Mode_Set(TIM_Module* TIMx, uint32_t output_channel_mode, uint16_t channel); +void TIM_Forced_Output_Channel1_Set(TIM_Module* TIMx, uint16_t TIM_ForcedAction); +void TIM_Forced_Output_Channel2_Set(TIM_Module* TIMx, uint16_t TIM_ForcedAction); +void TIM_Forced_Output_Channel3_Set(TIM_Module* TIMx, uint16_t TIM_ForcedAction); +void TIM_Forced_Output_Channel4_Set(TIM_Module* TIMx, uint16_t TIM_ForcedAction); +void TIM_Forced_Output_Channel5_Set(TIM_Module* TIMx, uint16_t TIM_ForcedAction); +void TIM_Output_Channel1_Fast_Set(TIM_Module* TIMx, uint16_t TIM_output_channel_fast); +void TIM_Output_Channel2_Fast_Set(TIM_Module* TIMx, uint16_t TIM_output_channel_fast); +void TIM_Output_Channel3_Fast_Set(TIM_Module* TIMx, uint16_t TIM_output_channel_fast); +void TIM_Output_Channel4_Fast_Set(TIM_Module* TIMx, uint16_t TIM_output_channel_fast); +void TIM_Output_Channel5_Fast_Set(TIM_Module* TIMx, uint16_t TIM_output_channel_fast); +void TIM_Output_Channel1_Reference_Clear(TIM_Module* TIMx, uint16_t TIM_output_chanenl_clear); +void TIM_Output_Channel2_Reference_Clear(TIM_Module* TIMx, uint16_t TIM_output_chanenl_clear); +void TIM_Output_Channel3_Reference_Clear(TIM_Module* TIMx, uint16_t TIM_output_chanenl_clear); +void TIM_Output_Channel4_Reference_Clear(TIM_Module* TIMx, uint16_t TIM_output_chanenl_clear); +void TIM_Output_Channel5_Reference_Clear(TIM_Module* TIMx, uint16_t TIM_output_chanenl_clear); +void TIM_PWM_Output_Enable(TIM_Module* TIMx); +void TIM_PWM_Output_Disable(TIM_Module* TIMx); +void TIM_Output_Channel1_Initialize(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct); +void TIM_Output_Channel2_Initialize(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct); +void TIM_Output_Channel3_Initialize(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct); +void TIM_Output_Channel4_Initialize(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct); +void TIM_Output_Channel5_Initialize(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct); +void TIM_Output_Channel_Struct_Initialize(OCInitType* TIM_OCInitStruct); + +/** Brake functions **/ +void TIM_Lock_Up_Break_Enable(TIM_Module* TIMx); +void TIM_Lock_Up_Break_Disable(TIM_Module* TIMx); +void TIM_Pvd_Break_Enable(TIM_Module* TIMx); +void TIM_Pvd_Break_Disable(TIM_Module* TIMx); +void TIM_IOM_Comp_Break(TIM_Module* TIMx, bool IOM_Comp_Selection); +void TIM_Break_And_Dead_Time_Set(TIM_Module* TIMx, TIM_BDTRInitType* TIM_BDTRInitStruct); +void TIM_Break_And_Dead_Time_Struct_Initialize(TIM_BDTRInitType* TIM_BDTRInitStruct); + +/** Interrupt functions **/ +void TIM_Interrupt_Enable(TIM_Module* TIMx, uint16_t TIM_IT); +void TIM_Interrupt_Disable(TIM_Module* TIMx, uint16_t TIM_IT); +FlagStatus TIM_Flag_Status_Get(TIM_Module* TIMx, uint32_t TIM_FLAG); +ITStatus TIM_Interrupt_Status_Get(TIM_Module* TIMx, uint32_t TIM_IT); +void TIM_Flag_Clear(TIM_Module* TIMx, uint32_t TIM_FLAG); +void TIM_Interrupt_Status_Clear(TIM_Module* TIMx, uint32_t TIM_IT); + + + + + + +#ifdef __cplusplus +} +#endif + +#endif /* _N32G003_TIM_H__ */ diff --git a/firmware/n32g003_std_periph_driver/inc/n32g003_uart.h b/firmware/n32g003_std_periph_driver/inc/n32g003_uart.h new file mode 100644 index 0000000..cb94c75 --- /dev/null +++ b/firmware/n32g003_std_periph_driver/inc/n32g003_uart.h @@ -0,0 +1,182 @@ +/** +* Copyright (c) 2022, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** +*\*\file n32g003_uart.h +*\*\author Nations +*\*\version v1.0.0 +*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. +**/ + +#ifndef __N32G003_UART_H +#define __N32G003_UART_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "n32g003.h" + +/*** UART Structure Definition Start ***/ + +/** UART Init structure definition **/ +typedef struct +{ + uint32_t BaudRate; /* Configures the UART communication baud rate. */ + + uint16_t WordLength; /* Specifies the number of data bits transmitted or received in a frame. */ + + uint16_t StopBits; /* Specifies the number of stop bits transmitted. */ + + uint16_t Parity; /* Specifies the parity mode. */ + + uint16_t Mode; /* Specifies wether the Receive or Transmit mode is enabled or disabled. */ + +} UART_InitType; + +/*** UART Macro Definition Start ***/ + +/** All register bits are configure to 0 **/ +#define UART_REG_BIT_MASK ((uint16_t)0x0000) + +/** Configures the word length of UART **/ +#define UART_WL_MASK (~UART_CTRL1_WL) /* word length Mask */ +#define UART_WL_8B (UART_REG_BIT_MASK) /* 8 bits */ +#define UART_WL_9B (UART_CTRL1_WL) /* 9 bits */ + +/** UART STOP bits **/ +#define CTRL2_STPB_CLR_MASK (~UART_CTRL2_STPB) /* UART CTRL2 STOP Bits Mask */ +#define UART_STPB_1 (UART_REG_BIT_MASK) /* 1 STOP bit */ +#define UART_STPB_2 (UART_CTRL2_STPB_1) /* 2 STOP bits */ + +/** UART parity selection **/ +#define UART_PE_MASK (~(UART_CTRL1_PCEN | UART_CTRL1_PSEL)) /* UART parity Mask */ +#define UART_PE_NO (UART_REG_BIT_MASK) /* UART parity disable */ +#define UART_PE_EVEN (UART_CTRL1_PCEN) /* Even parity */ +#define UART_PE_ODD (UART_CTRL1_PCEN | UART_CTRL1_PSEL) /* Odd parity */ + +/** UART is configured as RX or TX **/ +#define UART_MODE_MASK (~(UART_CTRL1_RXEN | UART_CTRL1_TXEN)) /* UART mode Mask */ +#define UART_MODE_RX (UART_CTRL1_RXEN) /* Transmitter enable */ +#define UART_MODE_TX (UART_CTRL1_TXEN) /* Receiver enable */ + +/** UART enable or disable **/ +#define CTRL1_UEN_SET (UART_CTRL1_UEN) /* UART Enable */ +#define CTRL1_UEN_RESET (~UART_CTRL1_UEN) /* UART Disable */ + +/** Configure interrupt **/ +#define INT_MASK ((uint16_t)0x001F) /* UART Interrupt Mask */ +#define UART_INT_PEF ((uint16_t)0x0028) /* Parity error interrupt */ +#define UART_INT_TXDE ((uint16_t)0x0727) /* TXDE interrupt */ +#define UART_INT_TXC ((uint16_t)0x0626) /* Transmission complete interrupt */ +#define UART_INT_RXDNE ((uint16_t)0x0525) /* RXDEN interrupt */ +#define UART_INT_IDLEF ((uint16_t)0x0424) /* IDLE interrupt */ +#define UART_INT_OREF ((uint16_t)0x0325) /* ORE interrupt */ + +/** UART address Mask **/ +#define CTRL2_ADDR_MASK (~UART_CTRL2_ADDR) + +/** Wake up methods **/ +#define CTRL1_WUM_MASK (~UART_CTRL1_WUM) /* UART WakeUp Method Mask */ +#define UART_WUM_IDLELINE (UART_REG_BIT_MASK) /* Idle frame wake up */ +#define UART_WUM_ADDRMASK (UART_CTRL1_WUM) /* Address mark wake up */ + +/** Receiver wakeup **/ +#define CTRL1_RCVWU_SET (UART_CTRL1_RCVWU) /* UART mute mode Enable */ +#define CTRL1_RCVWU_RESET (~UART_CTRL1_RCVWU) /* UART mute mode Disable */ + +/** UART Break Character send Mask **/ +#define CTRL1_SDBRK_SET (UART_CTRL1_SDBRK) + +/** UART Half-Duplex Enable or Disable **/ +#define CTRL3_HDMEN_SET (UART_CTRL3_HDMEN) /* UART Half-Duplex Enable */ +#define CTRL3_HDMEN_RESET (~UART_CTRL3_HDMEN) /* UART Half-Duplex Disable */ + +/* Specifies the flag to check */ +#define UART_FLAG_TXDE (UART_STS_TXDE) /* Transmit data register empty flag */ +#define UART_FLAG_TXC (UART_STS_TXC) /* Transmission complete flag*/ +#define UART_FLAG_RXDNE (UART_STS_RXDNE) /* Read data register not empty flag*/ +#define UART_FLAG_IDLEF (UART_STS_IDLEF) /* IDLE line detected flag */ +#define UART_FLAG_OREF (UART_STS_OREF) /* OverRun error flag */ +#define UART_FLAG_NEF (UART_STS_NEF) /* Noise error flag */ +#define UART_FLAG_FEF (UART_STS_FEF) /* Framing error flag*/ +#define UART_FLAG_PEF (UART_STS_PEF) /* Parity error flag */ + +void UART_Reset(UART_Module* UARTx); +void UART_Initializes(UART_Module* UARTx, UART_InitType* UART_InitStruct); +void UART_Baud_Rate_Config(UART_Module* UARTx,uint32_t buad_rate); +void UART_Word_Length_Config(UART_Module* UARTx,uint16_t word_length); +void UART_Stop_Bits_Config(UART_Module* UARTx,uint16_t stop_bits); +void UART_Parity_Config(UART_Module* UARTx,uint16_t parity); +void UART_Mode_Config(UART_Module* UARTx,uint16_t mode); +void UART_Structure_Initializes(UART_InitType* UART_InitStruct); +void UART_Enable(UART_Module* UARTx); +void UART_Disable(UART_Module* UARTx); +void UART_Interrput_Enable(UART_Module* UARTx, uint16_t UART_interrupt); +void UART_Interrput_Disable(UART_Module* UARTx, uint16_t UART_interrupt); +void UART_Address_Set(UART_Module* UARTx, uint8_t UART_address); +void UART_WakeUp_Mode_Set(UART_Module* UARTx, uint16_t UART_wake_up_mode); +void UART_Receiver_Wakeup_Enable(UART_Module* UARTx); +void UART_Receiver_Wakeup_Disable(UART_Module* UARTx); +void UART_Data_Send(UART_Module* UARTx, uint16_t data); +uint16_t UART_Data_Receive(UART_Module* UARTx); +void UART_Break_Frame_Send(UART_Module* UARTx); +void UART_Half_Duplex_Enable(UART_Module* UARTx); +void UART_Half_Duplex_Disable(UART_Module* UARTx); +FlagStatus UART_Flag_Status_Get(UART_Module* UARTx, uint16_t UART_flag); +void UART_Flag_Clear(UART_Module* UARTx, uint16_t UART_flag); +ITStatus UART_Interrupt_Status_Get(UART_Module* UARTx, uint16_t UART_interrupt); +void UART_Interrupt_Status_Clear(UART_Module* UARTx, uint16_t UART_Interrupt); + +#ifdef __cplusplus +} +#endif + +#endif /* __N32G003_UART_H */ + + +/******************* (C) COPYRIGHT 2022 NATIONZ *****END OF FILE****/ diff --git a/firmware/n32g003_std_periph_driver/src/misc.c b/firmware/n32g003_std_periph_driver/src/misc.c new file mode 100644 index 0000000..4f808ad --- /dev/null +++ b/firmware/n32g003_std_periph_driver/src/misc.c @@ -0,0 +1,139 @@ +/** +* Copyright (c) 2022, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** +*\*\file misc.c +*\*\author Nations +*\*\version v1.0.0 +*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. +**/ +#include "misc.h" + +/** MISC Driving Functions Declaration **/ + +/** +*\*\name NVIC_Initializes +*\*\fun Initializes the NVIC peripheral according to the specified parameters in the NVIC_structure_initializes. +*\*\param NVIC_structure_initializes : +*\*\ - NVIC_IRQChannel : +*\*\ - IRQn_Type N32G003 Interrupt Number Definition +*\*\ - NVIC_IRQChannelPriority : +*\*\ - NVIC_PRIORITY_0 +*\*\ - NVIC_PRIORITY_1 +*\*\ - NVIC_PRIORITY_2 +*\*\ - NVIC_PRIORITY_3 +*\*\ - NVIC_IRQChannelCmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void NVIC_Initializes(NVIC_InitType* NVIC_structure_initializes) +{ + /* Set Interrupt Priority */ + NVIC_SetPriority(NVIC_structure_initializes->NVIC_IRQChannel, NVIC_structure_initializes->NVIC_IRQChannelPriority); + + if (NVIC_structure_initializes->NVIC_IRQChannelCmd != DISABLE) + { + /* Enable the Selected IRQ Channels */ + NVIC_EnableIRQ(NVIC_structure_initializes->NVIC_IRQChannel); + } + else + { + /* Disable the Selected IRQ Channels */ + NVIC_DisableIRQ(NVIC_structure_initializes->NVIC_IRQChannel); + } +} + +/** +*\*\name NVIC_System_Low_Power_Enable +*\*\fun Selects the condition for the system to enter low power mode. +*\*\param low_power_mode Specifies the new mode for the system to enter low power mode. +*\*\ This parameter can be one of the following values: +*\*\ - NVIC_LP_SEVONPEND +*\*\ - NVIC_LP_SLEEPDEEP +*\*\ - NVIC_LP_SLEEPONEXIT +*\*\return none +**/ +void NVIC_System_LowPower_Enable(uint8_t low_power_mode) +{ + SCB->SCR |= low_power_mode; +} + +/** +*\*\name NVIC_System_Low_Power_Disable +*\*\fun Selects the condition for the system to enter low power mode. +*\*\param low_power_mode : +*\*\ - NVIC_LP_SEVONPEND +*\*\ - NVIC_LP_SLEEPDEEP +*\*\ - NVIC_LP_SLEEPONEXIT +*\*\return none +**/ +void NVIC_System_Low_Power_Disable(uint8_t low_power_mode) +{ + SCB->SCR &= (uint32_t)(~(uint32_t)low_power_mode); +} + +/** +*\*\name SysTick_Clock_Source_Set +*\*\fun Configures the SysTick clock source. +*\*\param systick_clock_source : +*\*\ - SYSTICK_CLKSOURCE_HCLK_DIV8 External clock selected as SysTick clock source. +*\*\ - SYSTICK_CLKSOURCE_HCLK AHB clock selected as SysTick clock source. +*\*\return none +**/ +void SysTick_Clock_Source_Set(uint32_t systick_clock_source) +{ + if (systick_clock_source == SYSTICK_CLKSOURCE_HCLK) + { + SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; + } + else + { + SysTick->CTRL &= SYSTICK_CLKSOURCE_HCLK_DIV8; + } +} + diff --git a/firmware/n32g003_std_periph_driver/src/n32g003_adc.c b/firmware/n32g003_std_periph_driver/src/n32g003_adc.c new file mode 100644 index 0000000..ea04d73 --- /dev/null +++ b/firmware/n32g003_std_periph_driver/src/n32g003_adc.c @@ -0,0 +1,742 @@ +/** +* Copyright (c) 2022, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** +*\*\file n32g003_adc.c +*\*\author Nations +*\*\version v1.0.0 +*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. +**/ + +#include "n32g003_adc.h" +#include "n32g003_rcc.h" +/** +*\*\name ADC_Reset. +*\*\fun Reset the ADC registers. +*\*\return none +**/ +void ADC_Reset(void) +{ + RCC_Peripheral_Reset(RCC_RST_ADCRST); +} + + +/** +*\*\name ADC_Multichannels_Enable. +*\*\fun Configures the ADC according conversion is performed in +*\*\ Scan (multichannels) mode. +*\*\return none +**/ +void ADC_Multichannels_Enable(void) +{ + /* Set ADC_CTRL1 SCANMD bit */ + ADC->CTRL2 |= ADC_MULTCH_ENABLE; +} +/** +*\*\name ADC_Multichannels_Disable. +*\*\fun Configures the ADC according conversion is performed in +*\*\ Single (one channel) mode. +*\*\return none +**/ +void ADC_Multichannels_Disable(void) +{ + /* Clear ADC_CTRL1 SCANMD bit */ + ADC->CTRL2 &= ADC_MULTCH_DISABLE; +} + +/** +*\*\name ADC_Continue_Conversion_Enable. +*\*\fun Configures the ADC according conversion is performed in +*\*\ Continuous mode. +*\*\return none +**/ +void ADC_Continue_Conversion_Enable(void) +{ + /* Set ADC_CTRL2 CTU bit */ + ADC->CTRL2 |= ADC_CTU_ENABLE; +} + +/** +*\*\name ADC_Continue_Conversion_Disable. +*\*\fun Configures the ADC according conversion is performed in +*\*\ Single mode. +*\*\return none +**/ +void ADC_Continue_Conversion_Disable(void) +{ + /* Clear ADC_CTRL2 CTU bit */ + ADC->CTRL2 &= ADC_CTU_DISABLE; +} + +/** +*\*\name ADC_Regular_Group_External_Trigger_Source_Config. +*\*\fun Configures the ADC external trigger source for regular group channels. +*\*\param external_trigger_sources : +*\*\ - ADC_EXT_TRIGCONV_REGULAR_T1_CC1 +*\*\ - ADC_EXT_TRIGCONV_REGULAR_T1_CC2 +*\*\ - ADC_EXT_TRIGCONV_REGULAR_T1_CC3 +*\*\ - ADC_EXT_TRIGCONV_REGULAR_T1_CC4 +*\*\ - ADC_EXT_TRIGCONV_REGULAR_T1_TRGO +*\*\ - ADC_EXT_TRIGCONV_REGULAR_T3_TRGO +*\*\ - ADC_EXT_TRIGCONV_REGULAR_T3_CC1 +*\*\ - ADC_EXT_TRIGCONV_REGULAR_T3_CC2 +*\*\ - ADC_EXT_TRIGCONV_REGULAR_EXT_INT11 +*\*\ - ADC_EXT_TRIGCONV_REGULAR_SWSTRRCH +*\*\return none +**/ +void ADC_Regular_Group_External_Trigger_Source_Config(uint32_t external_trigger_sources) +{ + /* Clear ADC_CTRL2 EXTRSEL[3:0] and EXTRTRIG bit */ + ADC->CTRL2 &= ADC_EXT_TRIGCONV_REGULAR_MASK; + /* Set ADC_CTRL2 EXTRSEL[3:0] and EXTRTRIG bit */ + ADC->CTRL2 |= external_trigger_sources; +} + +/** +*\*\name ADC_Data_Alignment_Config. +*\*\fun Configures the ADC data alignment is left or right. +*\*\param data_alignment : +*\*\ - ADC_DAT_ALIGN_R +*\*\ - ADC_DAT_ALIGN_L +*\*\return none +**/ +void ADC_Data_Alignment_Config(uint32_t data_alignment) +{ + /* Clear ADC_CTRL2 ALIG bit */ + ADC->CTRL2 &= ADC_ALIG_MASK; + /* Set ADC_CTRL2 ALIG bit */ + ADC->CTRL2 |= data_alignment; +} + +/** +*\*\name ADC_Regular_Channels_Number_Config. +*\*\fun Configures the ADC total number of conversion channels. +*\*\param channels_number : +*\*\ - ADC_REGULAR_LEN_1 +*\*\ - ADC_REGULAR_LEN_2 +*\*\ - ADC_REGULAR_LEN_3 +*\*\ - ADC_REGULAR_LEN_4 +*\*\ - ADC_REGULAR_LEN_5 +*\*\return none +**/ +void ADC_Regular_Channels_Number_Config(uint32_t channels_number) +{ + /* Clear ADC_RSEQ1 LEN[3:0] bit */ + ADC->CTRL2 &= ADC_REGULAR_LEN_MSAK; + /* Set ADC_RSEQ1 LEN[3:0] bit */ + ADC->CTRL2 |= channels_number; +} + + + +/** +*\*\name ADC_Initializes. +*\*\fun Initializes the ADC according to ADC_initstruct. +*\*\param ADC_initstruct : +*\*\ - MultiChEn +*\*\ - DISABLE +*\*\ - ENABLE +*\*\ - ContinueConvEn +*\*\ - DISABLE +*\*\ - ENABLE +*\*\ - ExtTrigSelect +*\*\ - ADC_EXT_TRIGCONV_REGULAR_T1_CC1 +*\*\ - ADC_EXT_TRIGCONV_REGULAR_T1_CC2 +*\*\ - ADC_EXT_TRIGCONV_REGULAR_T1_CC3 +*\*\ - ADC_EXT_TRIGCONV_REGULAR_T1_CC4 +*\*\ - ADC_EXT_TRIGCONV_REGULAR_T1_TRGO +*\*\ - ADC_EXT_TRIGCONV_REGULAR_T3_TRGO +*\*\ - ADC_EXT_TRIGCONV_REGULAR_T3_CC1 +*\*\ - ADC_EXT_TRIGCONV_REGULAR_T3_CC2 +*\*\ - ADC_EXT_TRIGCONV_REGULAR_EXT_INT11 +*\*\ - ADC_EXT_TRIGCONV_REGULAR_SWSTRRCH +*\*\ - DatAlign +*\*\ - ADC_DAT_ALIGN_R +*\*\ - ADC_DAT_ALIGN_L +*\*\ - ChsNumber +*\*\ - ADC_REGULAR_LEN_1 +*\*\ - ADC_REGULAR_LEN_2 +*\*\ - ADC_REGULAR_LEN_3 +*\*\ - ADC_REGULAR_LEN_4 +*\*\ - ADC_REGULAR_LEN_5 +*\*\return none +**/ +void ADC_Initializes(ADC_InitType* ADC_initstruct) +{ + if(ADC_initstruct->MultiChEn) + { + ADC_Multichannels_Enable(); + } + else + { + ADC_Multichannels_Disable(); + } + + if(ADC_initstruct->ContinueConvEn) + { + ADC_Continue_Conversion_Enable(); + } + else + { + ADC_Continue_Conversion_Disable(); + } + + ADC_Regular_Group_External_Trigger_Source_Config(ADC_initstruct->ExtTrigSelect); + ADC_Data_Alignment_Config(ADC_initstruct->DatAlign); + ADC_Regular_Channels_Number_Config(ADC_initstruct->ChsNumber); +} + + +/** +*\*\name ADC_Initializes_Structure. +*\*\fun Fills each ADC_initstruct member with its default value. +*\*\param ADC_initstruct : +*\*\ - MultiChEn +*\*\ - ContinueConvEn +*\*\ - ExtTrigSelect +*\*\ - DatAlign +*\*\ - ChsNumber +*\*\return none +**/ +void ADC_Initializes_Structure(ADC_InitType* ADC_initstruct) +{ + /* Reset ADC init structure parameters values */ + /* initialize the MultiChEn member */ + ADC_initstruct->MultiChEn = DISABLE; + /* Initialize the ContinueConvEn member */ + ADC_initstruct->ContinueConvEn = DISABLE; + /* Initialize the ExtTrigSelect member */ + ADC_initstruct->ExtTrigSelect = ADC_EXT_TRIGCONV_REGULAR_T1_CC1; + /* Initialize the DatAlign member */ + ADC_initstruct->DatAlign = ADC_DAT_ALIGN_R; + /* Initialize the ChsNumber member */ + ADC_initstruct->ChsNumber = ADC_REGULAR_LEN_1; +} + +/** +*\*\name ADC_ON. +*\*\fun ADC turn ON. +*\*\return none +**/ +void ADC_ON(void) +{ + /* Set the ADC_CTRL2 ON bit to wake up the ADC from power down mode */ + ADC->CTRL2 |= ADC_TURN_ON; +} + +/** +*\*\name ADC_OFF. +*\*\fun ADC turn OFF. +*\*\return none +**/ +void ADC_OFF(void) +{ + /* Clear the ADC_CTRL2 ON bit, then ADC go to power down mode */ + ADC->CTRL2 &= ADC_TURN_OFF; +} + +/** +*\*\name ADC_Interrupts_Enable. +*\*\fun Enable ADC interrupts. +*\*\param eoc_any : +*\*\ - ADC_SET_INT_TYPE_ENDCA +*\*\ - ADC_SET_INT_TYPE_OTHER +*\*\param ADC_SET_INT_TYPE_ENDCA: +*\*\ - ADC_INT_ENDCA ADC_CTRL3 +*\*\param ADC_SET_INT_TYPE_OTHER: +*\*\ - ADC_INT_ENDC ADC_CTRL1 +*\*\ - ADC_INT_AWD ADC_CTRL1 +*\*\return none +**/ +void ADC_Interrupts_Enable(u8 eoc_any, uint32_t adc_interrupt) +{ + if(eoc_any == ADC_SET_INT_TYPE_ENDCA) + { + /* Set the ADC_CTRL3 ADC_INT_ENDCA bit to enable ADC interrupts */ + ADC->CTRL3 |= adc_interrupt; + } + else + { + /* Set the ADC_CTRL1 ADC_INT_ENDC/ADC_INT_AWD bit to enable ADC interrupts */ + ADC->CTRL1 |= adc_interrupt; + } +} + +/** +*\*\name ADC_Interrupts_Disable. +*\*\fun Disable ADC interrupts. +*\*\param eoc_any : +*\*\ - ADC_SET_INT_TYPE_ENDCA +*\*\ - ADC_SET_INT_TYPE_OTHER +*\*\param ADC_SET_INT_TYPE_ENDCA: +*\*\ - ADC_INT_ENDCA ADC_CTRL3 +*\*\param ADC_SET_INT_TYPE_OTHER: +*\*\ - ADC_INT_ENDC ADC_CTRL1 +*\*\ - ADC_INT_AWD ADC_CTRL1 +*\*\return none +**/ +void ADC_Interrupts_Disable(u8 eoc_any, uint32_t adc_interrupt) +{ + if(eoc_any == ADC_SET_INT_TYPE_ENDCA) + { + /* Clear the ADC_CTRL3 ADC_INT_ENDCA bit to disable ADC interrupts */ + ADC->CTRL3 &= (~adc_interrupt); + } + else + { + /* Clear the ADC_CTRL1 ADC_INT_ENDC/ADC_INT_AWD bit to disable ADC interrupts */ + ADC->CTRL1 &= (~adc_interrupt); + } +} + +/** +*\*\name ADC_Regular_Channels_Software_Conversion_Operation. +*\*\fun ADC regular channels software conversion operation. +*\*\param conversion_operation : +*\*\ - ADC_EXTRTRIG_SWSTRRCH_ENABLE +*\*\ - ADC_EXTRTRIG_SWSTRRCH_DISABLE +*\*\ - ADC_EXTRTRIG_SWSTRRCH_GET_STS +*\*\return FlagStatus: +*\*\ - SET +*\*\ - RESET +**/ +FlagStatus ADC_Regular_Channels_Software_Conversion_Operation(uint32_t conversion_operation) +{ + if(conversion_operation == ADC_EXTRTRIG_SWSTRRCH_ENABLE) + { + /* Enable the ADC external trigger conversion mode for regular channels */ + ADC->CTRL2 |= conversion_operation; + } + else if(conversion_operation == ADC_EXTRTRIG_SWSTRRCH_DISABLE) + { + /* Disable the ADC external trigger conversion mode for regular channels */ + ADC->CTRL2 &= conversion_operation; + } + else if(conversion_operation == ADC_EXTRTRIG_SWSTRRCH_GET_STS) + { + /* Get ADC_CTRL2 SWSTRRCH bit */ + if ((ADC->CTRL2 & conversion_operation) != (uint32_t)RESET) + { + return SET; + } + else + { + return RESET; + } + } + return RESET; +} + +/** +*\*\name ADC_Channel_Sample_Time_Config. +*\*\fun Configures ADC channel sample time. +*\*\param sample_time : +*\*\ - ADC_SAMP_TIME_8CYCLES +*\*\ - ADC_SAMP_TIME_12CYCLES +*\*\ - ADC_SAMP_TIME_14CYCLES +*\*\ - ADC_SAMP_TIME_20CYCLES +*\*\ - ADC_SAMP_TIME_26CYCLES +*\*\ - ADC_SAMP_TIME_30CYCLES +*\*\ - ADC_SAMP_TIME_42CYCLES +*\*\ - ADC_SAMP_TIME_56CYCLES +*\*\ - ADC_SAMP_TIME_72CYCLES +*\*\ - ADC_SAMP_TIME_88CYCLES +*\*\ - ADC_SAMP_TIME_120CYCLES +*\*\ - ADC_SAMP_TIME_182CYCLES +*\*\ - ADC_SAMP_TIME_240CYCLES +*\*\ - ADC_SAMP_TIME_380CYCLES +*\*\ - ADC_SAMP_TIME_760CYCLES +*\*\ - ADC_SAMP_TIME_1520CYCLES +*\*\ - ADC_SAMP_TIME_3040CYCLES +*\*\return none +**/ +void ADC_Channel_Sample_Time_Config(uint8_t sample_time) +{ + ADC->SAMPT &= (uint32_t)(ADC_SAMP_TIME_MASK); + ADC->SAMPT |= (uint32_t)(sample_time); +} + +/** +*\*\name ADC_External_Trigger_Conversion_Config. +*\*\fun ADC conversion through external trigger enable. +*\*\param group_operation : +*\*\ - ADC_EXTTRIGCONV_REGULAR_ENABLE +*\*\ - ADC_EXTTRIGCONV_REGULAR_DISABLE +*\*\return none +**/ +void ADC_External_Trigger_Conversion_Config(uint32_t group_operation) +{ + if(group_operation == ADC_EXTTRIGCONV_REGULAR_ENABLE) + { + /* Enable ADC regular group channels conversion on external event */ + ADC->CTRL2 |= group_operation; + } + else if(group_operation == ADC_EXTTRIGCONV_REGULAR_DISABLE) + { + /* Disables ADC regular group channels conversion on external event */ + ADC->CTRL2 &= group_operation; + } +} +/** +*\*\name ADC_Regular_Conversion_Data_Get. +*\*\fun Get ADC regular conversion data. +*\*\return ADC regular group conversion data. +**/ +uint16_t ADC_Regular_Conversion_Data_Get(void) +{ + /* Return the conversion value */ + return (uint16_t)ADC->DAT0; +} +/** +*\*\name ADC_Regular_Group_Conversion_Data_Get. +*\*\fun Get ADC regular group conversion data. +*\*\param number : +*\*\ - 0~4 +*\*\return ADC regular group conversion data. +**/ +uint16_t ADC_Regular_Group_Conversion_Data_Get(uint8_t number) +{ + /* Return the conversion value */ + return ADC_DATA_REG_READ(ADC->DAT0,number); +} + +/** +*\*\name ADC_Analog_Watchdog_Mode_Channel_Config. +*\*\fun Configures ADC analog watchdog single mode or scan mode, +*\*\ and single mode channel operation. +*\*\param mode : +*\*\ - ADC_ANALOG_WTDG_SINGLE_MODE +*\*\ - ADC_ANALOG_WTDG_SCAN_MODE +*\*\param channel : +*\*\ - ADC_ANALOG_WTDG_SINGLE_CH0 +*\*\ - ADC_ANALOG_WTDG_SINGLE_CH1 +*\*\ - ADC_ANALOG_WTDG_SINGLE_CH2 +*\*\ - ADC_ANALOG_WTDG_SINGLE_CH3 +*\*\ - ADC_ANALOG_WTDG_SINGLE_CH4 +*\*\ - ADC_ANALOG_WTDG_SINGLE_CH5 +*\*\ - ADC_ANALOG_WTDG_SINGLE_CH6 +*\*\ - ADC_ANALOG_WTDG_SINGLE_CH7 +*\*\ - ADC_ANALOG_WTDG_SINGLE_CH8 +*\*\ - ADC_ANALOG_WTDG_SINGLE_CH9 +*\*\ - ADC_ANALOG_WTDG_SINGLE_CH10 +*\*\return none +**/ +void ADC_Analog_Watchdog_Mode_Channel_Config(uint32_t mode, uint8_t channel) +{ + /* ADC analog watchdog single mode */ + if(mode == ADC_ANALOG_WTDG_SINGLE_MODE) + { + ADC->CTRL1 |= mode; + /* Clear ADC analog watchdog single mode channel */ + ADC->CTRL1 &= ADC_ANALOG_WTDG_SINGLE_CH_MASK; + /* Select ADC analog watchdog single mode channel */ + ADC->CTRL1 |= (uint32_t)channel; + } + /* ADC analog watchdog scan mode */ + else + { + ADC->CTRL1 &= ADC_ANALOG_WTDG_MODE_MASK; + } +} + +/** +*\*\name ADC_Analog_Watchdog_Enable. +*\*\fun Enable ADC Analog watchdog. +*\*\param wcdg_mode : +*\*\ - ADC_ANALOG_WTDG_REGULAR +*\*\return none +**/ +void ADC_Analog_Watchdog_Enable(uint32_t wcdg_mode) +{ + /* Set the ADC_CTRL1 AWDGERCH bit */ + ADC->CTRL1 |= wcdg_mode; +} + +/** +*\*\name ADC_Analog_Watchdog_Disable. +*\*\fun Disable ADC Analog watchdog. +*\*\param wcdg_mode : +*\*\ - ADC_ANALOG_WTDG_REGULAR +*\*\return none +**/ +void ADC_Analog_Watchdog_Disable(uint32_t wcdg_mode) +{ + /* Clean the ADC_CTRL1 AWDGERCH bit */ + ADC->CTRL1 &= (~wcdg_mode); +} + +/** +*\*\name ADC_Analog_Watchdog_HighThresholds_Config. +*\*\fun Configures the high thresholds of the analog watchdog. +*\*\param high_thresholds : 12bit high thresholds value(0 ~ 0xFFF) +*\*\return none +**/ +void ADC_Analog_Watchdog_HighThresholds_Config(uint16_t high_thresholds) +{ + /* Set the ADC high thresholds */ + ADC->WDGHIGH = high_thresholds; +} + +/** +*\*\name ADC_Analog_Watchdog_LowThresholds_Config. +*\*\fun Configures the low thresholds of the analog watchdog. +*\*\param low_thresholds : 12bit low thresholds value(0 ~ 0xFFF) +*\*\return none +**/ +void ADC_Analog_Watchdog_LowThresholds_Config(uint16_t low_thresholds) +{ + /* Set the ADC low thresholds */ + ADC->WDGLOW = low_thresholds; +} + + + + +/** +*\*\name ADC_INTFlag_Status_Get. +*\*\fun Get ADC flag Status. +*\*\param adc_flag : +*\*\ - ADC_INT_FLAG_AWDG +*\*\ - ADC_INT_FLAG_ENDC +*\*\ - ADC_INT_FLAG_ENDCA +*\*\return SET or RESET +**/ +FlagStatus ADC_INTFlag_Status_Get(uint8_t adc_flag) +{ + /* Check the status of ADC flag */ + if ((ADC->STS & adc_flag) != (uint8_t)RESET) + { + /* ADC_FLAG is set */ + return SET; + } + else + { + /* ADC_FLAG is reset */ + return RESET; + } +} + +/** +*\*\name ADC_Flag_Status_Get. +*\*\fun Get ADC flag Status. +*\*\param selflag : +*\*\ - ADC_RUN_FLAG +*\*\ - ADC_RD_FLAG +*\*\param adc_runflag : +*\*\ - ADC_FLAG_AWDG +*\*\ - ADC_FLAG_ENDC +*\*\ - ADC_FLAG_STR +*\*\ - ADC_FLAG_ENDCA +*\*\param adc_rdflag : +*\*\ - ADC_FLAG_BUF_RDY +*\*\ - ADC_FLAG_RDY +*\*\ - ADC_FLAG_PD_RDY +*\*\return SET or RESET +**/ +FlagStatus ADC_Flag_Status_Get(uint8_t selflag, uint8_t adc_runflag, uint8_t adc_rdflag) +{ + if(selflag == ADC_RUN_FLAG) + { + /* Check the status of ADC flag */ + if ((ADC->STS & adc_runflag) != (uint8_t)RESET) + { + /* ADC_FLAG is set */ + return SET; + } + else + { + /* ADC_FLAG is reset */ + return RESET; + } + } + else + { + if ((ADC->CTRL3 & adc_rdflag) != (uint8_t)RESET) + { + /* ADC_FLAG is set */ + return SET; + } + else + { + /* ADC_FLAG is reset */ + return RESET; + } + } +} + +/** +*\*\name ADC_INTFlag_Status_Clear. +*\*\fun Clear ADC flag Status. +*\*\param adc_flag : +*\*\ - ADC_INT_FLAG_AWDG +*\*\ - ADC_INT_FLAG_ENDC +*\*\ - ADC_INT_FLAG_ENDCA +*\*\return SET or RESET +**/ +void ADC_INTFlag_Status_Clear(uint8_t adc_flag) +{ + /* Clear the selected ADC flag Status */ + ADC->STS &= ~(uint32_t)adc_flag; +} + +/** +*\*\name ADC_Flag_Status_Clear. +*\*\fun Clear ADC flag Status. +*\*\param adc_flag : +*\*\ - ADC_FLAG_AWDG +*\*\ - ADC_FLAG_ENDC +*\*\ - ADC_FLAG_STR +*\*\ - ADC_FLAG_ENDCA +*\*\return SET or RESET +**/ +void ADC_Flag_Status_Clear(uint8_t adc_flag) +{ + /* Clear the selected ADC flag Status */ + ADC->STS &= ~(uint32_t)adc_flag; +} + +/** +*\*\name ADC_Regular_Sequence_Single_Config. +*\*\fun Configures ADC channel Single in regular sequence. +*\*\param channel : +*\*\ - ADC_CH_0 +*\*\ - ADC_CH_1 +*\*\ - ADC_CH_2 +*\*\ - ADC_CH_3 +*\*\ - ADC_CH_4 +*\*\ - ADC_CH_5 +*\*\ - ADC_CH_6 +*\*\ - ADC_CH_7 +*\*\ - ADC_CH_8 +*\*\ - ADC_CH_9 +*\*\ - ADC_CH_10 +*\*\return none +**/ +void ADC_Regular_Sequence_Single_Config(uint8_t channel) +{ + /* ADC regular sequence register configures channelx */ + ADC->DAT0 &= ADC_SQR_MASK; + ADC->DAT0 |= (channel<DAT0 &= ADC_SQR_MASK; + ADC->DAT0 |= (channel<DAT1 &= ADC_SQR_MASK; + ADC->DAT1 |= (channel<DAT2 &= ADC_SQR_MASK; + ADC->DAT2 |= (channel<DAT3 &= ADC_SQR_MASK; + ADC->DAT3 |= (channel<DAT4 &= ADC_SQR_MASK; + ADC->DAT4 |= (channel<CTRL3 |= ADC_IN_BUFFER_ENABLE; + +} + +/** +*\*\name ADC_Vbat_Monitor_Disable. +*\*\fun ADC internal input buffer disable +*\*\return none +**/ +void ADC_Internal_Input_Buffer_Disable(void) +{ + /* Disable Vbat monitor */ + ADC->CTRL3 &= ADC_IN_BUFFER_DISABLE; + +} + diff --git a/firmware/n32g003_std_periph_driver/src/n32g003_beeper.c b/firmware/n32g003_std_periph_driver/src/n32g003_beeper.c new file mode 100644 index 0000000..6c37b1f --- /dev/null +++ b/firmware/n32g003_std_periph_driver/src/n32g003_beeper.c @@ -0,0 +1,127 @@ +/** +* Copyright (c) 2022, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** +*\*\file n32g003_beeper.c +*\*\author Nations +*\*\version v1.0.0 +*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. +**/ + +#include "n32g003_beeper.h" + +/** +*\*\name BEEPER_Reset. +*\*\fun Reset the BEEPER register to it's default reset values. +*\*\param none. +*\*\return none. +**/ + +void BEEPER_Reset(void) +{ + RCC_Peripheral_Reset(RCC_RST_BEEPRST); +} + +/** +*\*\name BEEPER_Frequency_Select. +*\*\fun Beeper output frequency selection. +*\*\param freq_selection: + -BEEPER_FREQ_8KHZ + -BEEPER_FREQ_4KHZ + -BEEPER_FREQ_2KHZ + -BEEPER_FREQ_1KHZ +*\*\return none. +**/ +void BEEPER_Frequency_Select(uint32_t freq_selection) +{ + BEEPER->CTRL &= BEEPER_FREQ_SEL_MASK; + BEEPER->CTRL |= freq_selection; +} +/** +*\*\name BEEPER_Inverted_Enable. +*\*\fun Beeper complementary output enable. +*\*\param none. +*\*\return none. +**/ +void BEEPER_Inverted_Enable(void) +{ + BEEPER->CTRL |= BEEPER_INV_ENABLE; +} + +/** +*\*\name BEEPER_Inverted_Disable. +*\*\fun Beeper complementary output disable. +*\*\param none. +*\*\return none. +**/ +void BEEPER_Inverted_Disable(void) +{ + BEEPER->CTRL &= BEEPER_INV_DISABLE; +} + +/** +*\*\name BEEPER_Enable. +*\*\fun Enable beeper. +*\*\param none. +*\*\return none. +**/ +void BEEPER_Enable(void) +{ + BEEPER->CTRL |= BEEPER_ENABLE; +} + +/** +*\*\name BEEPER_Disable. +*\*\fun Disable beeper. +*\*\param none. +*\*\return none. +**/ +void BEEPER_Disable(void) +{ + BEEPER->CTRL &= BEEPER_DISABLE; +} + diff --git a/firmware/n32g003_std_periph_driver/src/n32g003_comp.c b/firmware/n32g003_std_periph_driver/src/n32g003_comp.c new file mode 100644 index 0000000..5987550 --- /dev/null +++ b/firmware/n32g003_std_periph_driver/src/n32g003_comp.c @@ -0,0 +1,508 @@ +/** +* Copyright (c) 2022, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** +*\*\file n32g003_comp.c +*\*\author Nations +*\*\version v1.0.0 +*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. +**/ + +#include "n32g003_comp.h" +#include "n32g003_rcc.h" + + +/** COMP Driving Functions Declaration**/ + + +/** +*\*\name COMP_Reset. +*\*\fun Reset the COMP registers. +*\*\return none +**/ +void COMP_Reset(void) +{ + RCC_Peripheral_Reset(RCC_RST_COMPRST); +} + +/** +*\*\name COMP_Initializes_Structure. +*\*\fun Fills all COMP_initstruct member with default value. +*\*\param COMP_initstruct : +*\*\ - Blking +*\*\ - Hyst +*\*\ - PolRev +*\*\ - OutSel +*\*\ - SubSel +*\*\ - InpSel +*\*\ - InmSel +*\*\ - FilterEn +*\*\ - ClkPsc +*\*\ - SampWindow +*\*\ - Threshold +*\*\ - En +*\*\return none +**/ +void COMP_Initializes_Structure(COMP_InitType* COMP_initstruct) +{ + /* Reset COMP init structure parameters values */ + /* Initialize the Blking */ + COMP_initstruct->Blking = COMP_BLANKING_NO; + /* Initialize the Hyst */ + COMP_initstruct->Hyst = COMP_HYST_NO; + /* Initialize the PolRev */ + COMP_initstruct->PolRev = COMP_OUTPOL_NFLIP; + /* Initialize the OutSel */ + COMP_initstruct->OutSel = COMP_OUTSEL_RES; + /* Initialize the SubSel */ + COMP_initstruct->SubSel = COMP_SUB_NO; + /* Initialize the InpSel */ + COMP_initstruct->InpSel = COMP_INPSEL_RES; + /* Initialize the InmSel */ + COMP_initstruct->InmSel = COMP_INMSEL_RES; + /* Initialize the FilterEn */ + COMP_initstruct->FilterEn = DISABLE; + /* Initialize the ClkPsc */ + COMP_initstruct->ClkPsc = 0; + /* Initialize the SampWindow */ + COMP_initstruct->SampWindow = 0; + /* Initialize the Threshold */ + COMP_initstruct->Threshold = 0; + /* Initialize the En */ + COMP_initstruct->En = DISABLE; +} + +/** +*\*\name COMP_Filter_SampWindow_Config. +*\*\fun Configures the COMP filter sampwindow with a correct value. +*\*\param sampwin;_value: +*\*\ - from 0 to 31. +*\*\return none +**/ +void COMP_Filter_SampWindow_Config(uint8_t sampwin_value) +{ + /* Clear COMP_FILC SAMPW[4:0] bits */ + COMP->FILC &= COMP_FILTER_SAMPW_MASK; + /* Set COMP_FILC SAMPW[4:0] bits */ + COMP->FILC |= sampwin_value << REG_BIT6_OFFSET; +} + +/** +*\*\name COMP_Filter_Threshold_Config. +*\*\fun Configures the COMP filter Threshold with a correct value. +*\*\param Threshold_value: +*\*\ - Value must be greater than SAMPW / 2 . +*\*\return none +**/ +void COMP_Filter_Threshold_Config(uint8_t Threshold_value) +{ + /* Clear COMP_FILC THRESH[4:0] bits */ + COMP->FILC &= COMP_FILTER_THRESHOLD_MASK; + /* Set COMP_FILC THRESH[4:0] bits */ + COMP->FILC |= Threshold_value << REG_BIT1_OFFSET; + +} + +/** +*\*\name COMP_Filter_Enable. +*\*\fun Configures COMP filter enable. +*\*\ - Before the COMP filter is enabled, the clock of the COMP filter must be turned on. +*\*\ - Configure RCC_APB1PCLKEN. COMPFILTEN = 1 to enable COMP filter, the RCC driver function can configure this. +*\*\return none +**/ +void COMP_Filter_Enable(void) +{ + /* Set COMP_FILC FILTER bits */ + COMP->FILC |= COMP_FILTER_ENABLE; +} + +/** +*\*\name COMP_Filter_Disable. +*\*\fun Configures COMP filter disable. +*\*\return none +**/ +void COMP_Filter_Disable(void) +{ + /* Clear COMP_FILC FILTER bits */ + COMP->FILC &= COMP_FILTER_DISABLE; +} + +/** +*\*\name COMP_Filter_Clock_Prescale_Config. +*\*\fun Configures The COMP low filter prescale . +*\*\param clkpsc_value: +*\*\ Value can be set from 0 to 65535. +*\*\return none +**/ +void COMP_Filter_Clock_Prescale_Config(uint16_t clkpsc_value) +{ + /* Clear COMP_FILP CLKPSC[15:0] bits */ + COMP->FILP &= COMP_FILTER_CLKPSC_MASK; + /* Set COMP_FILP CLKPSC[15:0] bits */ + COMP->FILP |= clkpsc_value; +} + +/** +*\*\name COMP_Blking_Soucre_Config. +*\*\fun Configures TIM1 output signal to control COMP Blking. +*\*\param blking_mode : +*\*\ - COMP_BLANKING_NO +*\*\ - COMP_BLANKING_TIM1_OC5 +*\*\return none +**/ +void COMP_Blking_Soucre_Config(uint32_t blking_mode) +{ + /* Clear COMP_CTRL BLKING bit */ + COMP->CTRL &= COMP_BLANKING_MASK; + /* Set COMP_CTRL BLKING bit */ + COMP->CTRL |= blking_mode; +} + +/** +*\*\name COMP_Subtract_Level_Config. +*\*\fun Configures COMP Subtract level. +*\*\param sub_mode : +*\*\ - COMP_SUB_NO +*\*\ - COMP_SUB_100mV +*\*\ - COMP_SUB_200mV +*\*\ - COMP_SUB_300mV +*\*\return none +**/ +void COMP_Subtract_Level_Config(uint32_t sub_mode) +{ + /* Clear COMP_CTRL CMPVOS[1:0] bits */ + COMP->CTRL &= COMP_SUB_MASK; + /* Set COMP_CTRL CMPVOS[1:0] bits */ + COMP->CTRL |= sub_mode; +} + +/** +*\*\name COMP_Hysteresis_Level_Config. +*\*\fun Configures COMP hysteresis level. +*\*\param hyst_mode : +*\*\ - COMP_HYST_NO +*\*\ - COMP_HYST_LOW 5.1mV-level +*\*\ - COMP_HYST_MID 15mV-level +*\*\ - COMP_HYST_HIGH 25mV-level +*\*\return none +**/ +void COMP_Hysteresis_Level_Config(uint32_t hyst_mode) +{ + /* Clear COMP_CTRL HYST[1:0] bits */ + COMP->CTRL &= COMP_HYST_MASK; + /* Set COMP_CTRL HYST[1:0] bits */ + COMP->CTRL |= hyst_mode; +} + +/** +*\*\name COMP_Output_Polarity_Config. +*\*\fun Configures COMP output signal polarity overturn or not. +*\*\param output_pol : +*\*\ - COMP_OUTPOL_FLIP +*\*\ - COMP_OUTPOL_NFLIP +*\*\return none +**/ +void COMP_Output_Polarity_Config(uint32_t output_pol) +{ + /* Clear COMP_CTRL POL bits */ + COMP->CTRL &= COMP_OUTPOL_MASK; + /* Set COMP_CTRL POL bits */ + COMP->CTRL |= output_pol; +} + +/** +*\*\name COMP_InpSel_Config. +*\*\fun Configures COMP inpsel. +*\*\param vpsel : +*\*\ comp inp sel +*\*\ - COMP_INPSEL_PB0 +*\*\ - COMP_INPSEL_PA5 +*\*\return none +**/ +void COMP_InpSel_Config(uint32_t vpsel) +{ + /* Clear COMP_CTRL INPSEL bit */ + COMP->CTRL &= COMP_INPSEL_MASK; + /* Set COMP_CTRL INPSEL bit */ + COMP->CTRL |= vpsel; +} + +/** +*\*\name COMP_InmSel_Config. +*\*\fun Configures COMP inmsel. +*\*\param vpsel : +*\*\ comp inm sel +*\*\ - COMP_INMSEL_PB1 +*\*\ - COMP_INMSEL_PA4 +*\*\return none +**/ +void COMP_InmSel_Config(uint32_t vpsel) +{ + /* Clear COMP_CTRL INMSEL bit */ + COMP->CTRL &= COMP_INMSEL_MASK; + /* Set COMP_CTRL INMSEL bit */ + COMP->CTRL |= vpsel; +} + +/** +*\*\name COMP_Output_Trigger_Config. +*\*\fun Configures which Timer input must be connected with the comparator output. +*\*\param outtrgsel : +*\*\ comp out trig +*\*\ - COMP_OUTSEL_NO +*\*\ - COMP_OUTSEL_TIM1_BKIN +*\*\ - COMP_OUTSEL_TIM1_IC1 +*\*\ - COMP_OUTSEL_TIM1_OCREFCLEAR +*\*\ - COMP_OUTSEL_TIM3_IC1 +*\*\ - COMP_OUTSEL_TIM3_OCREFCLEAR +*\*\return none +**/ +void COMP_Output_Trigger_Config(uint32_t outtrgsel) +{ + /* Clear COMP_CSR OUTSEL[3:0] bits */ + COMP->CTRL &= COMP_OUTSEL_MASK; + /* Set COMP_CSR OUTSEL[3:0] bits */ + COMP->CTRL |= outtrgsel; +} + +/** +*\*\name COMP_ON. +*\*\fun Enable COMP. +*\*\return none +**/ +void COMP_ON(void) +{ + /* Set the COMP_CTRL EN bit to wake up the COMP from power down mode */ + COMP->CTRL |= COMP_ENABLE; +} + +/** +*\*\name COMP_OFF. +*\*\fun Disable COMP. +*\*\return none +**/ +void COMP_OFF(void) +{ + /* Clear the COMP_CTRL EN bit, The COMP go to power down mode */ + COMP->CTRL &= COMP_DISABLE; +} + +/** +*\*\name COMP_Lock_Config. +*\*\fun Configures COMP will be Locked. +*\*\return none +**/ +void COMP_Lock_Config(void) +{ + COMP->LOCK |= COMP_LOCK ; +} + +/** +*\*\name COMP_Interrupt_Enable. +*\*\fun Configures COMP interrupt enable. +*\*\param IntEn : +*\*\ - COMP_INTEN +*\*\return none +**/ +void COMP_Interrupt_Enable(uint32_t inten) +{ + COMP->INTEN |= inten; +} + +/** +*\*\name COMP_Interrupt_Disable. +*\*\fun Configures COMP interrupt disable. +*\*\param IntEn : +*\*\ - COMP_INTEN +*\*\return none +**/ +void COMP_Interrupt_Disable(uint32_t inten) +{ + COMP->INTEN &= ~inten; +} + +/** +*\*\name COMP_Interrupt_Status_Get. +*\*\fun Get COMP interrupt Status. +*\*\return +*\*\ - COMP_INTSTS +**/ +uint8_t COMP_Interrupt_Status_Get(void) +{ + return COMP->INTSTS; +} + +/** +*\*\name COMP_Interrupt_Status_Clear. +*\*\fun Clear COMP interrupt flag. +*\*\return none +**/ +void COMP_Interrupt_Status_Clear(void) +{ + COMP->INTSTS &= COMP_INTS_CLEAR; +} + +/** +*\*\name COMP_Output_Status_Get. +*\*\fun Get COMP Output Status. +*\*\return FlagStatus: +*\*\ - SET +*\*\ - RESET +**/ +FlagStatus COMP_Output_Status_Get(void) +{ + return (COMP->CTRL & COMP_OUT) ? SET : RESET; +} + +/** +*\*\name COMP_Filter_Control_Config. +*\*\fun Configures the COMP filter control value. +*\*\param sw : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\param threshnum : +*\*\ - Threshold Value need > SampWindow/2. +*\*\param sampwindow : +*\*\ - Value can be set from 0 to 31. +*\*\return none +**/ +void COMP_Filter_Control_Config(uint32_t sw, uint8_t threshold , uint8_t sampwindow) +{ + COMP_Filter_SampWindow_Config(sampwindow); + COMP_Filter_Threshold_Config(threshold); + if(sw == ENABLE) + { + COMP_Filter_Enable(); + } + else + { + COMP_Filter_Disable(); + } +} + +/** +*\*\name COMP_Initializes. +*\*\fun Initializes the COMP according to COMP_initstruct. +*\*\param COMP_initstruct : +*\*\ - Blking +*\*\ - COMP_BLANKING_NO +*\*\ - COMP_BLANKING_TIM1_OC5 +*\*\ - Hyst +*\*\ - COMP_HYST_NO +*\*\ - COMP_HYST_LOW +*\*\ - COMP_HYST_MID +*\*\ - COMP_HYST_HIGH +*\*\ - PolRev +*\*\ - COMP_OUTPOL_FLIP +*\*\ - COMP_OUTPOL_NFLIP +*\*\ - OutSel +*\*\ comp out trig +*\*\ - COMP_OUTSEL_NO +*\*\ - COMP_OUTSEL_TIM1_BKIN +*\*\ - COMP_OUTSEL_TIM1_IC1 +*\*\ - COMP_OUTSEL_TIM1_OCREFCLEAR +*\*\ - COMP_OUTSEL_TIM3_IC1 +*\*\ - COMP_OUTSEL_TIM3_OCREFCLEAR +*\*\ - SubSel +*\*\ - COMP_SUB_NO +*\*\ - COMP_SUB_100mV +*\*\ - COMP_SUB_200mV +*\*\ - COMP_SUB_300mV +*\*\ - InpSel +*\*\ comp inp sel +*\*\ - COMP_INPSEL_PB0 +*\*\ - COMP_INPSEL_PA5 +*\*\ - InmSel +*\*\ comp inm sel +*\*\ - COMP_INMSEL_PB1 +*\*\ - COMP_INMSEL_PA4 +*\*\ - En +*\*\ - ENABLE +*\*\ - DISABLE +*\*\ - SampWindow +*\*\ - SampWindow Value ranges from 0~31. +*\*\ - Threshold +*\*\ - Threshold Value need > SampWindow/2. +*\*\ - FilterEn +*\*\ - ENABLE +*\*\ - DISABLE +*\*\ - ClkPsc +*\*\ - ClkPsc Value ranges from 0~36635. +*\*\return none +**/ +void COMP_Initializes(COMP_InitType* COMP_initstruct) +{ + /** filter configures **/ + COMP_Filter_SampWindow_Config(COMP_initstruct->SampWindow); + COMP_Filter_Threshold_Config( COMP_initstruct->Threshold); + if(COMP_initstruct->FilterEn == ENABLE) + { + COMP_Filter_Enable(); + } + else + { + COMP_Filter_Disable(); + } + /** filter clock Prescale configures **/ + COMP_Filter_Clock_Prescale_Config(COMP_initstruct->ClkPsc); + + /** ctrl configures**/ + COMP_Blking_Soucre_Config(COMP_initstruct->Blking); + COMP_Hysteresis_Level_Config(COMP_initstruct->Hyst); + COMP_Output_Polarity_Config(COMP_initstruct->PolRev); + COMP_Subtract_Level_Config(COMP_initstruct->SubSel); + COMP_InpSel_Config(COMP_initstruct->InpSel); + COMP_InmSel_Config(COMP_initstruct->InmSel); + COMP_Output_Trigger_Config(COMP_initstruct->OutSel); + + /** comp enable or disable configures*/ + if (COMP_initstruct->En == ENABLE) + COMP_ON(); + else + COMP_OFF(); +} + diff --git a/firmware/n32g003_std_periph_driver/src/n32g003_crc.c b/firmware/n32g003_std_periph_driver/src/n32g003_crc.c new file mode 100644 index 0000000..d75a8e0 --- /dev/null +++ b/firmware/n32g003_std_periph_driver/src/n32g003_crc.c @@ -0,0 +1,193 @@ +/** +* Copyright (c) 2022, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** +*\*\file n32g003_crc.c +*\*\author Nations +*\*\version v1.0.0 +*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ + +#include "n32g003_crc.h" + +/** CRC Private Defines **/ + + +/** CRC Driving Functions Declaration **/ + +/** +*\*\name CRC16_Calculate. +*\*\fun Computes the 16-bit CRC of a given data word(8-bit). +*\*\param data : +*\*\ - data word(8-bit) to compute its CRC +*\*\return 16-bit CRC +**/ +uint16_t CRC16_Calculate(uint8_t data) +{ + /* Write data to the CRC16DAT register */ + CRC->CRC16DAT = data; + /* Returns the computed CRC16 result */ + return (CRC->CRC16D); +} + +/** +*\*\name CRC16_Buffer_Calculate. +*\*\fun Computes the 16-bit CRC of a given buffer of data word(8-bit). +*\*\param p_buf : +*\*\ - pointer to the buffer containing the data to be computed +*\*\param buf_len : +*\*\ - length of the buffer to be computed +*\*\return 16-bit CRC +**/ +uint16_t CRC16_Buffer_Calculate(uint8_t p_buf[], uint32_t buf_len) +{ + uint32_t index = 0; + CRC->CRC16D = 0x00; + for (index = 0; index < buf_len; index++) + { + /* Write data to the CRC16DAT register */ + CRC->CRC16DAT = p_buf[index]; + } + /* Returns the computed CRC16 result */ + return (CRC->CRC16D); +} + +/** +*\*\name CRC16_Set. +*\*\fun write a 8-bit data in the 16-bit CRC Data register. +*\*\param data : +*\*\ - 8-bit data value to be writed in the 16-bit CRC Data register +*\*\return none +**/ +void CRC16_Set(uint8_t data) +{ + /* Writes 8-bit data to the CRC16DAT register */ + CRC->CRC16DAT = data; +} + +/** +*\*\name CRC16_Get. +*\*\fun Returns the current CRC value. +*\*\param none +*\*\return 16-bit CRC +**/ +uint16_t CRC16_Get(void) +{ + /* Returns the CRC16 calculation result */ + return (CRC->CRC16D); +} + +/** +*\*\name CRC16_Little_Endian_Format_Set. +*\*\fun Set the calculate data to little endian format. +*\*\param none +*\*\return none +**/ +void CRC16_Little_Endian_Format_Set(void) +{ + CRC->CRC16CTRL |= CRC_LITTLE_ENDIAN_ENABLE; +} + +/** +*\*\name CRC16_Big_Endian_Format_Set. +*\*\fun Set the calculate data to big endian format. +*\*\param none +*\*\return none +**/ +void CRC16_Big_Endian_Format_Set(void) +{ + CRC->CRC16CTRL &= CRC_BIG_ENDIAN_ENABLE; +} + +/** +*\*\name CRC16_Value_Clean_Enable. +*\*\fun Enable Clean CRC16 value. +*\*\param none +*\*\return none +**/ +void CRC16_Value_Clean_Enable(void) +{ + CRC->CRC16CTRL |= CRC_CRC16_VALUE_CLEAR; +} + +/** +*\*\name CRC16_Value_Clean_Disable. +*\*\fun Disable Clean CRC16 value. +*\*\param none +*\*\return none +**/ +void CRC16_Value_Clean_Disable(void) +{ + CRC->CRC16CTRL &= CRC_CRC16_VALUE_NO_CLEAR; +} + +/** +*\*\name CRC_LRC_Set. +*\*\fun Write LRC initial value. +*\*\param data : +*\*\ - 8-bit data +*\*\return none +**/ +void CRC_LRC_Set(uint8_t data) +{ + /* Write LRC to verify the initial value */ + CRC->LRC = data; +} + +/** +*\*\name CRC_LRC_Get. +*\*\fun Returns the current LRC value. +*\*\param none +*\*\return 8-bit LRC +**/ +uint8_t CRC_LRC_Get(void) +{ + /* Returns the LRC check value */ + return (CRC->LRC); +} + + diff --git a/firmware/n32g003_std_periph_driver/src/n32g003_dbg.c b/firmware/n32g003_std_periph_driver/src/n32g003_dbg.c new file mode 100644 index 0000000..884fbb3 --- /dev/null +++ b/firmware/n32g003_std_periph_driver/src/n32g003_dbg.c @@ -0,0 +1,143 @@ +/** +* Copyright (c) 2022, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** +*\*\file n32g003_dbg.c +*\*\author Nations +*\*\version v1.0.0 +*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. +**/ + +#ifndef __N32G003_DBG_H__ +#define __N32G003_DBG_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "n32g003.h" + +#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF) + +/** +*\*\name UCID_Get. +*\*\fun get unique customer id. +*\*\param UCIDbuf +*\*\return none +**/ +void UCID_Get(uint8_t *UCIDbuf) +{ + uint8_t num = 0; + uint32_t* ucid_addr = (void*)0; + uint32_t temp = 0; + + ucid_addr = (uint32_t*)UCID_BASE; + + for (num = 0; num < UCID_LENGTH;) + { + temp = *(__IO uint32_t*)(ucid_addr++); + UCIDbuf[num++] = (temp & 0xFF); + UCIDbuf[num++] = (temp & 0xFF00) >> 8; + UCIDbuf[num++] = (temp & 0xFF0000) >> 16; + UCIDbuf[num++] = (temp & 0xFF000000) >> 24; + } +} + +/** +*\*\name UID_Get. +*\*\fun get unique device id. +*\*\param UIDbuf +*\*\return none +**/ +void UID_Get(uint8_t *UIDbuf) +{ + uint8_t num = 0; + uint32_t* uid_addr = (void*)0; + uint32_t temp = 0; + + uid_addr = (uint32_t*)UID_BASE; + + for (num = 0; num < UID_LENGTH;) + { + temp = *(__IO uint32_t*)(uid_addr++); + UIDbuf[num++] = (temp & 0xFF); + UIDbuf[num++] = (temp & 0xFF00) >> 8; + UIDbuf[num++] = (temp & 0xFF0000) >> 16; + UIDbuf[num++] = (temp & 0xFF000000) >> 24; + } +} + +/** +*\*\name DBGMCU_ID_Get. +*\*\fun get debug MCU id. +*\*\param DBGIDbuf +*\*\return none +**/ +void DBGMCU_ID_Get(uint8_t *DBGIDbuf) +{ + uint8_t num = 0; + uint32_t* dbgid_addr = (void*)0; + uint32_t temp = 0; + + dbgid_addr = (uint32_t*)DBGMCU_ID_BASE; + + for (num = 0; num < DBGMCU_ID_LENGTH;) + { + temp = *(__IO uint32_t*)(dbgid_addr++); + DBGIDbuf[num++] = (temp & 0xFF); + DBGIDbuf[num++] = (temp & 0xFF00) >> 8; + DBGIDbuf[num++] = (temp & 0xFF0000) >> 16; + DBGIDbuf[num++] = (temp & 0xFF000000) >> 24; + } +} + + +#ifdef __cplusplus +} +#endif + +#endif /*__N32G003_DBG_H__ */ diff --git a/firmware/n32g003_std_periph_driver/src/n32g003_exti.c b/firmware/n32g003_std_periph_driver/src/n32g003_exti.c new file mode 100644 index 0000000..97bb684 --- /dev/null +++ b/firmware/n32g003_std_periph_driver/src/n32g003_exti.c @@ -0,0 +1,453 @@ +/** +* Copyright (c) 2022, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** +*\*\file n32g003_exti.c +*\*\author Nations +*\*\version v1.0.0 +*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. +**/ +#include "n32g003_exti.h" + + +/** +*\*\name EXTI_Reset. +*\*\fun Reset the EXTI registers. +*\*\return none +**/ +void EXTI_Reset(void) +{ + EXTI->IMASK = 0x00000000; + EXTI->EMASK = 0x00000000; + EXTI->RT_CFG = 0x00000000; + EXTI->FT_CFG = 0x00000000; + EXTI->PEND = 0x000FFFFF; +} + +/** +*\*\name EXTI_Peripheral_Initializes. +*\*\fun Initializes the EXTI according to EXTI_InitStruct. +*\*\param EXTI_InitStruct : +*\*\ - EXTI_Mode +*\*\ - EXTI_Mode_Interrupt +*\*\ - EXTI_Mode_Event +*\*\ - EXTI_Trigger +*\*\ - EXTI_Trigger_Rising +*\*\ - EXTI_Trigger_Falling +*\*\ - EXTI_Trigger_Rising_Falling +*\*\ - EXTI_Line +*\*\ - EXTI_LINE0 +*\*\ - EXTI_LINE1 +*\*\ - EXTI_LINE2 +*\*\ - EXTI_LINE3 +*\*\ - EXTI_LINE4 +*\*\ - EXTI_LINE5 +*\*\ - EXTI_LINE6 +*\*\ - EXTI_LINE7 +*\*\ - EXTI_LINE8 +*\*\ - EXTI_LINE9 +*\*\ - EXTI_LINE10 +*\*\ - EXTI_LINE11 +*\*\ - EXTI_LINE12 +*\*\ - EXTI_LINE13 +*\*\ - EXTI_LINE14 +*\*\ - EXTI_LINE15 +*\*\ - EXTI_LINE16 +*\*\ - EXTI_LINE17 +*\*\ - EXTI_LINE18 +*\*\ - EXTI_LINE19 +*\*\ - EXTI_LineCmd +*\*\ - ENABLE +*\*\ - DISABLE +*\*\return none +**/ +void EXTI_Peripheral_Initializes(EXTI_InitType* EXTI_InitStruct) +{ + EXTI_Work_Mode_Config(EXTI_InitStruct->EXTI_Line,EXTI_InitStruct->EXTI_Mode); + EXTI_Trigger_Config(EXTI_InitStruct->EXTI_Line,EXTI_InitStruct->EXTI_Trigger); + EXTI_LineCmd_Disable(EXTI_InitStruct->EXTI_Line,EXTI_InitStruct->EXTI_LineCmd,EXTI_InitStruct->EXTI_Mode); +} + + +/** +*\*\name EXTI_Work_Mode_Config. +*\*\fun Config the EXTI according to EXTI_Mode. +*\*\param exti_mode : +*\*\ - EXTI_Mode_Interrupt +*\*\ - EXTI_Mode_Event +*\*\param exti_line : +*\*\ - EXTI_LINE0 +*\*\ - EXTI_LINE1 +*\*\ - EXTI_LINE2 +*\*\ - EXTI_LINE3 +*\*\ - EXTI_LINE4 +*\*\ - EXTI_LINE5 +*\*\ - EXTI_LINE6 +*\*\ - EXTI_LINE7 +*\*\ - EXTI_LINE8 +*\*\ - EXTI_LINE9 +*\*\ - EXTI_LINE10 +*\*\ - EXTI_LINE11 +*\*\ - EXTI_LINE12 +*\*\ - EXTI_LINE13 +*\*\ - EXTI_LINE14 +*\*\ - EXTI_LINE15 +*\*\ - EXTI_LINE16 +*\*\ - EXTI_LINE17 +*\*\ - EXTI_LINE18 +*\*\ - EXTI_LINE19 +*\*\return none +**/ +void EXTI_Work_Mode_Config(uint32_t exti_line,uint32_t exti_mode) +{ + uint32_t temp_value = 0; + temp_value = (uint32_t)EXTI_BASE; + + /* Clear EXTI line configuration */ + EXTI->IMASK &= ~exti_line; + EXTI->EMASK &= ~exti_line; + /* Select the work mode */ + temp_value += exti_mode; + *(__IO uint32_t*)temp_value |= exti_line; +} + +/** +*\*\name EXTI_EXTI_Trigger_Config. +*\*\fun Config the EXTI according to EXTI_Trigger. +*\*\param exti_trigger : +*\*\ - EXTI_Trigger_Rising +*\*\ - EXTI_Trigger_Falling +*\*\ - EXTI_Trigger_Rising_Falling +*\*\param exti_line : +*\*\ - EXTI_LINE0 +*\*\ - EXTI_LINE1 +*\*\ - EXTI_LINE2 +*\*\ - EXTI_LINE3 +*\*\ - EXTI_LINE4 +*\*\ - EXTI_LINE5 +*\*\ - EXTI_LINE6 +*\*\ - EXTI_LINE7 +*\*\ - EXTI_LINE8 +*\*\ - EXTI_LINE9 +*\*\ - EXTI_LINE10 +*\*\ - EXTI_LINE11 +*\*\ - EXTI_LINE12 +*\*\ - EXTI_LINE13 +*\*\ - EXTI_LINE14 +*\*\ - EXTI_LINE15 +*\*\ - EXTI_LINE16 +*\*\ - EXTI_LINE17 +*\*\ - EXTI_LINE18 +*\*\ - EXTI_LINE19 +*\*\return none +**/ +void EXTI_Trigger_Config(uint32_t exti_line,uint32_t exti_trigger) +{ + uint32_t temp_value = 0;// + temp_value = (uint32_t)EXTI_BASE; // + /* Clear Rising Falling edge configuration */ + EXTI->RT_CFG &= ~exti_line; + EXTI->FT_CFG &= ~exti_line; + /* Select the trigger for the selected external interrupts */ + if(exti_trigger == EXTI_Trigger_Rising_Falling) + { + /* Rising Falling edge */ + EXTI->RT_CFG |= exti_line; + EXTI->FT_CFG |= exti_line; + } + else + { + temp_value = (uint32_t)EXTI_BASE; + temp_value += exti_trigger; + + *(__IO uint32_t*)temp_value |= exti_line; + } +} + +/** +*\*\name EXTI_EXTI_LineCmd_Disable. +*\*\fun Config the EXTI according to EXTI_LineCmd. +*\*\param exti_linecmd : +*\*\ - ENABLE +*\*\ - DISABLE +*\*\param exti_mode : +*\*\ - EXTI_Mode_Interrupt +*\*\ - EXTI_Mode_Event +*\*\param exti_line : +*\*\ - EXTI_LINE0 +*\*\ - EXTI_LINE1 +*\*\ - EXTI_LINE2 +*\*\ - EXTI_LINE3 +*\*\ - EXTI_LINE4 +*\*\ - EXTI_LINE5 +*\*\ - EXTI_LINE6 +*\*\ - EXTI_LINE7 +*\*\ - EXTI_LINE8 +*\*\ - EXTI_LINE9 +*\*\ - EXTI_LINE10 +*\*\ - EXTI_LINE11 +*\*\ - EXTI_LINE12 +*\*\ - EXTI_LINE13 +*\*\ - EXTI_LINE14 +*\*\ - EXTI_LINE15 +*\*\ - EXTI_LINE16 +*\*\ - EXTI_LINE17 +*\*\ - EXTI_LINE18 +*\*\ - EXTI_LINE19 +*\*\return none +**/ +void EXTI_LineCmd_Disable(uint32_t exti_line,uint32_t exti_linecmd,uint32_t exti_mode) +{ + uint32_t temp_value = 0; + temp_value = (uint32_t)EXTI_BASE; + /* Disable the selected external lines */ + if(exti_linecmd == DISABLE) + { + temp_value += exti_mode; + /* Disable the selected external lines */ + *(__IO uint32_t*)temp_value &= ~exti_line; + } +} + +/** +*\*\name EXTI_Structure_Initializes. +*\*\fun Fills each EXTI_InitStruct member with its default value. +*\*\param EXTI_InitStruct : +*\*\ - EXTI_Line +*\*\ - EXTI_Mode +*\*\ - EXTI_Trigger +*\*\ - EXTI_LineCmd +*\*\return none +**/ +void EXTI_Structure_Initializes(EXTI_InitType* EXTI_InitStruct) +{ + EXTI_InitStruct->EXTI_Line = EXTI_LINENONE; + EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt; + EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling; + EXTI_InitStruct->EXTI_LineCmd = DISABLE; +} + +/** +*\*\name EXTI_Software_Interrupt_Trigger. +*\*\fun Generates a Software interrupt. +*\*\param exti_line : +*\*\ - EXTI_LINE0 +*\*\ - EXTI_LINE1 +*\*\ - EXTI_LINE2 +*\*\ - EXTI_LINE3 +*\*\ - EXTI_LINE4 +*\*\ - EXTI_LINE5 +*\*\ - EXTI_LINE6 +*\*\ - EXTI_LINE7 +*\*\ - EXTI_LINE8 +*\*\ - EXTI_LINE9 +*\*\ - EXTI_LINE10 +*\*\ - EXTI_LINE11 +*\*\ - EXTI_LINE12 +*\*\ - EXTI_LINE13 +*\*\ - EXTI_LINE14 +*\*\ - EXTI_LINE15 +*\*\ - EXTI_LINE16 +*\*\ - EXTI_LINE17 +*\*\ - EXTI_LINE18 +*\*\ - EXTI_LINE19 +*\*\return none +**/ +void EXTI_Software_Interrupt_Trigger(uint32_t exti_line) +{ + /* Set the EXTI_SWIE ON bit, The EXTI generates a Software interrupt */ + EXTI->SWIE |= exti_line; +} + +/** +*\*\name EXTI_Flag_Status_Get. +*\*\fun Get EXTI line flag status. +*\*\param exti_line : +*\*\ - EXTI_LINE0 +*\*\ - EXTI_LINE1 +*\*\ - EXTI_LINE2 +*\*\ - EXTI_LINE3 +*\*\ - EXTI_LINE4 +*\*\ - EXTI_LINE5 +*\*\ - EXTI_LINE6 +*\*\ - EXTI_LINE7 +*\*\ - EXTI_LINE8 +*\*\ - EXTI_LINE9 +*\*\ - EXTI_LINE10 +*\*\ - EXTI_LINE11 +*\*\ - EXTI_LINE12 +*\*\ - EXTI_LINE13 +*\*\ - EXTI_LINE14 +*\*\ - EXTI_LINE15 +*\*\ - EXTI_LINE16 +*\*\ - EXTI_LINE17 +*\*\ - EXTI_LINE18 +*\*\ - EXTI_LINE19 +*\*\return SET or RESET +**/ +FlagStatus EXTI_Flag_Status_Get(uint32_t exti_line) +{ + if ((EXTI->PEND & exti_line) != (uint32_t)RESET) + { + /* EXTI line flag status is set */ + return SET; + } + else + { + /* EXTI line flag status is reset */ + return RESET; + } +} + +/** +*\*\name EXTI_Flag_Status_Clear. +*\*\fun Clear EXTI line flag status. +*\*\param exti_line : +*\*\ - EXTI_LINE0 +*\*\ - EXTI_LINE1 +*\*\ - EXTI_LINE2 +*\*\ - EXTI_LINE3 +*\*\ - EXTI_LINE4 +*\*\ - EXTI_LINE5 +*\*\ - EXTI_LINE6 +*\*\ - EXTI_LINE7 +*\*\ - EXTI_LINE8 +*\*\ - EXTI_LINE9 +*\*\ - EXTI_LINE10 +*\*\ - EXTI_LINE11 +*\*\ - EXTI_LINE12 +*\*\ - EXTI_LINE13 +*\*\ - EXTI_LINE14 +*\*\ - EXTI_LINE15 +*\*\ - EXTI_LINE16 +*\*\ - EXTI_LINE17 +*\*\ - EXTI_LINE18 +*\*\ - EXTI_LINE19 +*\*\return none +**/ +void EXTI_Flag_Status_Clear(uint32_t exti_line) +{ + /* Clear EXTI line flag status. */ + EXTI->PEND = exti_line; +} + +/** +*\*\name EXTI_Interrupt_Status_Get. +*\*\fun GET EXTI line interrupt status. +*\*\param exti_line : +*\*\ - EXTI_LINE0 +*\*\ - EXTI_LINE1 +*\*\ - EXTI_LINE2 +*\*\ - EXTI_LINE3 +*\*\ - EXTI_LINE4 +*\*\ - EXTI_LINE5 +*\*\ - EXTI_LINE6 +*\*\ - EXTI_LINE7 +*\*\ - EXTI_LINE8 +*\*\ - EXTI_LINE9 +*\*\ - EXTI_LINE10 +*\*\ - EXTI_LINE11 +*\*\ - EXTI_LINE12 +*\*\ - EXTI_LINE13 +*\*\ - EXTI_LINE14 +*\*\ - EXTI_LINE15 +*\*\ - EXTI_LINE16 +*\*\ - EXTI_LINE17 +*\*\ - EXTI_LINE18 +*\*\ - EXTI_LINE19 +*\*\ - EXTI_LINE20 +*\*\ - EXTI_LINE21 +*\*\ - EXTI_LINE22 +*\*\ - EXTI_LINE23 +*\*\return SET or RESET +**/ +ITStatus EXTI_Interrupt_Status_Get(uint32_t exti_line) +{ + if (((EXTI->PEND & exti_line) != (uint32_t)RESET) && ((EXTI->IMASK & exti_line) != (uint32_t)RESET))// + { + /* EXTI line interrupt status is set */ + return SET; + } + else + { + /* EXTI line interrupt status is reset */ + return RESET; + } +} + +/** +*\*\name EXTI_Interrupt_Status_Clear. +*\*\fun Clear EXTI line interrupt pend bit. +*\*\param exti_line : +*\*\ - EXTI_LINE0 +*\*\ - EXTI_LINE1 +*\*\ - EXTI_LINE2 +*\*\ - EXTI_LINE3 +*\*\ - EXTI_LINE4 +*\*\ - EXTI_LINE5 +*\*\ - EXTI_LINE6 +*\*\ - EXTI_LINE7 +*\*\ - EXTI_LINE8 +*\*\ - EXTI_LINE9 +*\*\ - EXTI_LINE10 +*\*\ - EXTI_LINE11 +*\*\ - EXTI_LINE12 +*\*\ - EXTI_LINE13 +*\*\ - EXTI_LINE14 +*\*\ - EXTI_LINE15 +*\*\ - EXTI_LINE16 +*\*\ - EXTI_LINE17 +*\*\ - EXTI_LINE18 +*\*\ - EXTI_LINE19 +*\*\return none +**/ +void EXTI_Interrupt_Status_Clear(uint32_t exti_line) +{ + /* Clear EXTI line interrupt pend bit. */ + EXTI->PEND = exti_line; +} + diff --git a/firmware/n32g003_std_periph_driver/src/n32g003_flash.c b/firmware/n32g003_std_periph_driver/src/n32g003_flash.c new file mode 100644 index 0000000..40276f4 --- /dev/null +++ b/firmware/n32g003_std_periph_driver/src/n32g003_flash.c @@ -0,0 +1,1409 @@ +/** +* Copyright (c) 2022, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** +*\*\file system_n32g003.c +*\*\author Nations +*\*\version v1.0.0 +*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. +**/ +#include "n32g003_flash.h" + + +/** +*\*\name FLASH_Latency_Set +*\*\fun Sets the code latency value. +*\*\note This function can be used for N32G003 devices. +*\*\param flash_latency : +*\*\ - FLASH_LATENCY_0 FLASH Zero Latency cycle, 0 < HCLK <= 24MHz +*\*\ - FLASH_LATENCY_1 FLASH One Latency cycle, 24MHz < HCLK<= 48MHz +*\*\return none +**/ + +void FLASH_Latency_Set(uint32_t flash_latency) +{ + uint32_t temp_value = 0; + + /* Read the AC register */ + temp_value = FLASH->AC; + + /* Sets the Latency value */ + temp_value &= (~FLASH_LATENCY_MASK); + temp_value |= flash_latency; + + /* Write the AC register */ + FLASH->AC = temp_value; +} + +/** +*\*\name FLASH_Latency_Get +*\*\fun Get the code latency value. +*\*\note This function can be used for N32G003 devices. +*\*\param none +*\*\return FLASH_LATENCY : +*\*\ - FLASH_LATENCY_0 FLASH Zero Latency cycle, 0 < HCLK <= 24MHz +*\*\ - FLASH_LATENCY_1 FLASH One Latency cycle, 24MHz < HCLK<= 48MHz +**/ +uint8_t FLASH_Latency_Get(void) +{ + /* Read the AC register */ + return (uint8_t)(FLASH->AC & FLASH_LATENCY_MASK); +} + + +/** +*\*\name FLASH_Prefetch_Buffer_Enable +*\*\fun Enables the Prefetch Buffer. +*\*\note This function can be used for N32G003 devices. +*\*\param none +*\*\return none +**/ +void FLASH_Prefetch_Buffer_Enable(void) +{ + /* Enable the Prefetch Buffer */ + FLASH->AC |= FLASH_PREFETCHBUF_EN; +} + +/** +*\*\name FLASH_Prefetch_Buffer_Disable +*\*\fun Disables the Prefetch Buffer. +*\*\note This function can be used for N32G003 devices. +*\*\param none +*\*\return none +**/ +void FLASH_Prefetch_Buffer_Disable(void) +{ + /* Disable the Prefetch Buffer */ + FLASH->AC &= FLASH_PREFETCHBUF_DIS; +} + +/** +*\*\name FLASH_Unlock +*\*\fun Unlocks the FLASH Program Erase Controller. +*\*\note This function can be used for N32G003 devices. +*\*\param none +*\*\return none +**/ +void FLASH_Unlock(void) +{ + FLASH->KEY = FLASH_KEY1; + FLASH->KEY = FLASH_KEY2; +} + + + +/** +*\*\name FLASH_Lock +*\*\fun Locks the FLASH Program Erase Controller. +*\*\note This function can be used for N32G003 devices. +*\*\param none +*\*\return none +**/ +void FLASH_Lock(void) +{ + FLASH->CTRL |= FLASH_CTRL_SET_LOCK; +} + + +/** +*\*\name Option_Bytes_Unlock +*\*\fun Unlocks the Option_Bytes Program Erase Controller. +*\*\note This function can be used for N32G003 devices. +*\*\param none +*\*\return none +**/ +void Option_Bytes_Unlock(void) +{ + FLASH->OPTKEY = FLASH_KEY1; + FLASH->OPTKEY = FLASH_KEY2; +} + + +/** +*\*\name Option_Bytes_Lock +*\*\fun Locks the Option_Bytes Program Erase Controller. +*\*\note This function can be used for N32G003 devices. +*\*\param none +*\*\return none +**/ +void Option_Bytes_Lock(void) +{ + /* Set the FLASH_CTRL_SET_OPTWE Bit to lock */ + FLASH->CTRL &= (~FLASH_CTRL_SET_OPTWE); +} + + +/** +*\*\name Option_Bytes_Lock_Status_Get +*\*\fun Get the Option Bytes lock status. +*\*\note This function can be used for N32G003 devices. +*\*\param none +*\*\return FlagStatus : +*\*\ - SET +*\*\ - RESET +**/ +FlagStatus Option_Bytes_Lock_Status_Get(void) +{ + if ((FLASH->CTRL & FLASH_CTRL_SET_OPTWE) != (uint32_t)RESET) + { + return SET; + } + else + { + return RESET; + } +} + + +/** +*\*\name FLASH_One_Page_Erase +*\*\fun Erases a specified FLASH page. +*\*\note This function can be used for N32G003 devices. +*\*\param page_address : +*\*\ - It ranges from 0x08000000 to 0x0800FFFF +*\*\return FLASH_STS : +*\*\ - FLASH_BUSY +*\*\ - FLASH_ERR_PG +*\*\ - FLASH_ERR_WRP +*\*\ - FLASH_EOP +*\*\ - FLASH_TIMEOUT +**/ +FLASH_STS FLASH_One_Page_Erase(uint32_t page_address) +{ + FLASH_STS status_value = FLASH_EOP; + + /* Clears the FLASH's pending flags */ + FLASH_Flag_Status_Clear(FLASH_STS_CLRFLAG); + /* Wait for last operation to be completed */ + status_value = FLASH_Last_Operation_Wait(ERASE_TIMEOUT); + + if (status_value == FLASH_EOP) + { + /* if the previous operation is completed, proceed to erase the page */ + FLASH->CTRL |= FLASH_CTRL_SET_PER; + FLASH->ADD = page_address; + FLASH->CTRL |= FLASH_CTRL_SET_START; + + /* Wait for last operation to be completed */ + status_value = FLASH_Last_Operation_Wait(ERASE_TIMEOUT); + + /* Disable the PER Bit */ + FLASH->CTRL &= FLASH_CTRL_RESET_PER; + } + else + { + /*No process*/ + } + + /* Return the Erase status_value */ + return status_value; +} + + +/** +*\*\name FLASH_Mass_Erase +*\*\fun Erases all FLASH pages. +*\*\note This function can be used for all N32G003 devices. +*\*\param none +*\*\return FLASH_STS : +*\*\ - FLASH_BUSY +*\*\ - FLASH_ERR_PG +*\*\ - FLASH_ERR_WRP +*\*\ - FLASH_EOP +*\*\ - FLASH_TIMEOUT +**/ +FLASH_STS FLASH_Mass_Erase(void) +{ + FLASH_STS status_value = FLASH_EOP; + + /* Clears the FLASH's pending flags */ + FLASH_Flag_Status_Clear(FLASH_STS_CLRFLAG); + /* Wait for last operation to be completed */ + status_value = FLASH_Last_Operation_Wait(ERASE_TIMEOUT); + + if (status_value == FLASH_EOP) + { + /* if the previous operation is completed, proceed to erase all pages */ + FLASH->CTRL |= FLASH_CTRL_SET_MER; + FLASH->CTRL |= FLASH_CTRL_SET_START; + + /* Wait for last operation to be completed */ + status_value = FLASH_Last_Operation_Wait(ERASE_TIMEOUT); + + /* Disable the MER Bit */ + FLASH->CTRL &= FLASH_CTRL_RESET_MER; + } + else + { + /*No process*/ + } + + /* Return the Erase status_value */ + return status_value; +} + + +/** +*\*\name FLASH_48Page_Mass_Erase +*\*\fun Erases first 48 pages FLASH. +*\*\note This function can be used for all N32G003 devices. +*\*\param none +*\*\return FLASH_STS : +*\*\ - FLASH_BUSY +*\*\ - FLASH_ERR_PG +*\*\ - FLASH_ERR_WRP +*\*\ - FLASH_EOP +*\*\ - FLASH_TIMEOUT +**/ +FLASH_STS FLASH_48Page_Mass_Erase(void) +{ + FLASH_STS status_value = FLASH_EOP; + + /* Clears the FLASH's pending flags */ + FLASH_Flag_Status_Clear(FLASH_STS_CLRFLAG); + /* Wait for last operation to be completed */ + status_value = FLASH_Last_Operation_Wait(ERASE_TIMEOUT); + + if (status_value == FLASH_EOP) + { + /* if the previous operation is completed, proceed to erase all pages */ + FLASH->CTRL |= FLASH_CTRL_SET_MMER; + FLASH->CTRL |= FLASH_CTRL_SET_START; + + /* Wait for last operation to be completed */ + status_value = FLASH_Last_Operation_Wait(ERASE_TIMEOUT); + + /* Disable the MER Bit */ + FLASH->CTRL &= FLASH_CTRL_RESET_MMER; + } + else + { + /*No process*/ + } + + /* Return the Erase status_value */ + return status_value; +} + + + +/** +*\*\name FLASH_Word_Program +*\*\fun Programs a word at a specified address. +*\*\note This function can be used for N32G003 devices. +*\*\param address : +*\*\ - It ranges from 0x08000000 to 0x080075FF +*\*\param data : +*\*\ - It ranges from 0x00000000 to 0xFFFFFFFF +*\*\return FLASH_STS : +*\*\ - FLASH_BUSY +*\*\ - FLASH_ERR_PG +*\*\ - FLASH_ERR_WRP +*\*\ - FLASH_EOP +*\*\ - FLASH_ERR_ADD +*\*\ - FLASH_TIMEOUT +**/ +FLASH_STS FLASH_Word_Program(uint32_t address, uint32_t data) +{ + FLASH_STS status_value = FLASH_EOP; + + if((address & FLASH_WORD_LENGTH) != RESET) + { + /* The programming address is not a multiple of 4 */ + return FLASH_ERR_ADD; + } + else + { + /*No process*/ + } + + /* Clears the FLASH's pending flags */ + FLASH_Flag_Status_Clear(FLASH_STS_CLRFLAG); + /* Wait for last operation to be completed */ + status_value = FLASH_Last_Operation_Wait(PROGRAM_TIMEOUT); + + if (status_value == FLASH_EOP) + { + /* if the previous operation is completed, proceed to program the new word */ + FLASH->CTRL |= FLASH_CTRL_SET_PG; + + *(__IO uint32_t*)address = (uint32_t)data; + /* Wait for last operation to be completed */ + status_value = FLASH_Last_Operation_Wait(PROGRAM_TIMEOUT); + + /* Disable the PG Bit */ + FLASH->CTRL &= FLASH_CTRL_RESET_PG; + } + else + { + /*No process*/ + } + + /* Return the Program status_value */ + return status_value; +} + + +/** +*\*\name FLASH_Option_Bytes_Erase +*\*\fun Erases the FLASH option bytes. +*\*\note This functions erases all option bytes except the Read protection (RDP). +*\*\ This function can be used for N32G003 devices. +*\*\param none +*\*\return FLASH_STS : +*\*\ - FLASH_BUSY +*\*\ - FLASH_ERR_PG +*\*\ - FLASH_ERR_WRP +*\*\ - FLASH_EOP +*\*\ - FLASH_ERR_RDP2 +*\*\ - FLASH_ERR_ADD +*\*\ - FLASH_TIMEOUT +**/ +FLASH_STS FLASH_Option_Bytes_Erase(void) +{ + FLASH_STS status_value = FLASH_EOP; + + /* Get the actual read protection L2 Option Byte value */ + if (FLASH_Read_Out_Protection_L2_Status_Get() != RESET) + { + return FLASH_ERR_RDP2; + } + else + { + /*No process*/ + } + + /* Clears the FLASH's pending flags */ + FLASH_Flag_Status_Clear(FLASH_STS_CLRFLAG); + /* Wait for last operation to be completed */ + status_value = FLASH_Last_Operation_Wait(ERASE_TIMEOUT); + + if (status_value == FLASH_EOP) + { + Option_Bytes_Unlock(); + + /* if the previous operation is completed, proceed to erase the option bytes */ + FLASH->CTRL |= FLASH_CTRL_SET_OPTER; + FLASH->CTRL |= FLASH_CTRL_SET_START; + /* Wait for last operation to be completed */ + status_value = FLASH_Last_Operation_Wait(ERASE_TIMEOUT); + + if (status_value == FLASH_EOP) + { + /* Clears the FLASH's pending flags */ + FLASH_Flag_Status_Clear(FLASH_STS_CLRFLAG); + + /* if the erase operation is completed, disable the OPTER Bit */ + FLASH->CTRL &= FLASH_CTRL_RESET_OPTER; + } + else + { + if (status_value != FLASH_TIMEOUT) + { + /* Disable the OPTER Bit */ + FLASH->CTRL &= FLASH_CTRL_RESET_OPTER; + } + else + { + /*No process*/ + } + } + } + else + { + /*No process*/ + } + /* Return the erase status_value */ + return status_value; +} + + +/** +*\*\name FLASH_Option_Bytes_User_RDP1_Program +*\*\fun Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_PD / +*\*\ LOCK_BOOT / PA0_NRST / RDP1. +*\*\note This function can be used for N32G003 devices. +*\*\param option_byte_rdp1 : +*\*\ - FLASH_OB_RDP1_ENABLE +*\*\ - FLASH_OB_RDP1_DISABLE +*\*\param option_byte_iwdg : +*\*\ - FLASH_OB_IWDG_SW Software IWDG selected +*\*\ - FLASH_OB_IWDG_HW Hardware IWDG selected +*\*\param option_byte_stop : +*\*\ - FLASH_OB_STOP_NORST No reset generated when entering in STOP +*\*\ - FLASH_OB_STOP_RST Reset generated when entering in STOP +*\*\param option_byte_PD : +*\*\ - FLASH_OB_PD_NORST No reset generated when entering in PD +*\*\ - FLASH_OB_PD_RST Reset generated when entering in PD +*\*\param option_byte_lock_boot : +*\*\ - FLASH_OB_LOCK_BOOT First 3KB FLASH LOCK +*\*\ - FLASH_OB_NOLOCK_BOOT First 3KB FLASH NOLOCK +*\*\param option_byte_PA0_NRST : +*\*\ - FLASH_OB_PA0_IO PA0 is general pin +*\*\ - FLASH_OB_PA0_NRST PA0 is RESET pin +*\*\return FLASH_STS : +*\*\ - FLASH_BUSY +*\*\ - FLASH_ERR_PG +*\*\ - FLASH_ERR_WRP +*\*\ - FLASH_EOP +*\*\ - FLASH_ERR_RDP2 +*\*\ - FLASH_TIMEOUT +**/ +FLASH_STS FLASH_Option_Bytes_User_RDP1_Program(uint8_t option_byte_rdp1, uint16_t option_byte_iwdg, \ + uint16_t option_byte_stop, uint16_t option_byte_PD, \ + uint16_t option_byte_lock_boot, uint16_t option_byte_PA0_NRST) +{ + FLASH_STS status_value = FLASH_EOP; + + /* Get the actual read protection L2 Option Byte value */ + if (FLASH_Read_Out_Protection_L2_Status_Get() != RESET) + { + return FLASH_ERR_RDP2; + } + else + { + /*No process*/ + } + + Option_Bytes_Unlock(); + + /* Clears the FLASH's pending flags */ + FLASH_Flag_Status_Clear(FLASH_STS_CLRFLAG); + /* Wait for last operation to be completed */ + status_value = FLASH_Last_Operation_Wait(ERASE_TIMEOUT); + + if (status_value == FLASH_EOP) + { + /* Enable the Option Bytes Programming operation */ + FLASH->CTRL |= FLASH_CTRL_SET_OPTPG; + /* Restore the last read protection Option Byte value */ + OBT->USER_RDP = + (uint32_t)option_byte_rdp1 + | (((uint32_t)(option_byte_iwdg | option_byte_stop | option_byte_PD | option_byte_lock_boot + | option_byte_PA0_NRST)) << FLASH_USER_RDP_OFFSET); + + /* Wait for last operation to be completed */ + status_value = FLASH_Last_Operation_Wait(PROGRAM_TIMEOUT); + if (status_value != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CTRL &= FLASH_CTRL_RESET_OPTPG; + } + else + { + /*No process*/ + } + } + else + { + /*No process*/ + } + + /* Return the Option Byte program status_value */ + return status_value; +} + +/** +*\*\name FLASH_Option_Bytes_DATA_Program +*\*\fun Programs a half word at a specified Option Byte Data0 and Data1. +*\*\note This function can be used for N32G003 devices. +*\*\param option_byte_data0: +*\*\ - 0x00 to 0xFF +*\*\param option_byte_data1: +*\*\ - 0x00 to 0xFF +*\*\return FLASH_STS: The returned value can be: +*\*\ - FLASH_BUSY +*\*\ - FLASH_ERR_PG +*\*\ - FLASH_ERR_WRP +*\*\ - FLASH_EOP +*\*\ - FLASH_ERR_RDP2 +*\*\ - FLASH_TIMEOUT +**/ +FLASH_STS FLASH_Option_Bytes_DATA_Program(uint8_t option_byte_data0,uint8_t option_byte_data1) +{ + FLASH_STS status_value = FLASH_EOP; + + /* Get the actual read protection L2 Option Byte value */ + if (FLASH_Read_Out_Protection_L2_Status_Get() != RESET) + { + return FLASH_ERR_RDP2; + } + else + { + /*No process*/ + } + + /* Clears the FLASH's pending flags */ + FLASH_Flag_Status_Clear(FLASH_STS_CLRFLAG); + /* Wait for last operation to be completed */ + status_value = FLASH_Last_Operation_Wait(PROGRAM_TIMEOUT); + + if (status_value == FLASH_EOP) + { + Option_Bytes_Unlock(); + /* Enables the Option Bytes Programming operation */ + FLASH->CTRL |= FLASH_CTRL_SET_OPTPG; + OBT->Data1_Data0 = (((uint32_t)option_byte_data1) << FLASH_DATA0_DATA1_OFFSET) \ + | ((uint32_t)option_byte_data0); + + /* Wait for last operation to be completed */ + status_value = FLASH_Last_Operation_Wait(PROGRAM_TIMEOUT); + if (status_value != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CTRL &= FLASH_CTRL_RESET_OPTPG; + } + else + { + /*No process*/ + } + } + else + { + /*No process*/ + } + /* Return the Option Byte Data Program status_value */ + return status_value; +} + + +/** +*\*\name FLASH_Option_Bytes_User2_User3_Program +*\*\fun Programs a half word at a specified Option Byte USER2 and USER3. +*\*\note This function can be used for N32G003 devices. +*\*\param option_byte_user2: +*\*\ - 0x00 to 0xFF LVR filter control count value +*\*\param option_byte_LVR_cnt : +*\*\ - 0x00 to 0x0F LVR gear selection +*\*\param option_byte_LVR : +*\*\ - FLASH_OB_USER_LVR_ENABLE LVR enable +*\*\ - FLASH_OB_USER_LVR_DISABLE LVR disable +*\*\param option_byte_LVR_filter : +*\*\ - FLASH_OB_USER_LVRFIL_ENABLE LVR filter enable +*\*\ - FLASH_OB_USER_LVRFIL_DISABLE LVR filter disable +*\*\param option_byte_LVR_reset : +*\*\ - FLASH_OB_USER_LVRRST_ENABLE LVR reset enable +*\*\ - FLASH_OB_USER_LVRRST_DISABLE LVR reset disable +*\*\return FLASH_STS: The returned value can be: +*\*\ - FLASH_BUSY +*\*\ - FLASH_ERR_PG +*\*\ - FLASH_ERR_WRP +*\*\ - FLASH_EOP +*\*\ - FLASH_ERR_RDP2 +*\*\ - FLASH_TIMEOUT +**/ +FLASH_STS FLASH_Option_Bytes_User2_User3_Program(uint8_t option_byte_user2,uint8_t option_byte_LVR_cnt, \ + uint8_t option_byte_LVR,uint8_t option_byte_LVR_filter,uint8_t option_byte_LVR_reset) +{ + FLASH_STS status_value = FLASH_EOP; + + /* Clears the FLASH's pending flags */ + FLASH_Flag_Status_Clear(FLASH_STS_CLRFLAG); + /* Wait for last operation to be completed */ + status_value = FLASH_Last_Operation_Wait(PROGRAM_TIMEOUT); + /* Get the actual read protection L2 Option Byte value */ + if (FLASH_Read_Out_Protection_L2_Status_Get() != RESET) + { + return FLASH_ERR_RDP2; + } + else + { + /*No process*/ + } + if (status_value == FLASH_EOP) + { + Option_Bytes_Unlock(); + /* Enables the Option Bytes Programming operation */ + FLASH->CTRL |= FLASH_CTRL_SET_OPTPG; + OBT->USER3_USER2 = (uint32_t)option_byte_user2 | (((uint32_t)(option_byte_LVR_cnt | option_byte_LVR | option_byte_LVR_filter | option_byte_LVR_reset)) << FLASH_USER2_USER3_OFFSET); + + /* Wait for last operation to be completed */ + status_value = FLASH_Last_Operation_Wait(PROGRAM_TIMEOUT); + if (status_value != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CTRL &= FLASH_CTRL_RESET_OPTPG; + } + else + { + /*No process*/ + } + } + else + { + /*No process*/ + } + /* Return the Option Byte Data Program status_value */ + return status_value; +} + + +/** +*\*\name FLASH_Option_Bytes_User4_RDP2_Program +*\*\fun Programs a half word at a specified Option Byte Data address. +*\*\note This function can be used for N32G003 devices. +*\*\param option_byte_rdp2: +*\*\ - FLASH_OB_RDP2_ENABLE +*\*\ - FLASH_OB_RDP2_DISABLE +*\*\param option_byte_user4: +*\*\ - 0x00 to 0xFF +*\*\return FLASH_STS: The returned value can be: +*\*\ - FLASH_BUSY +*\*\ - FLASH_ERR_PG +*\*\ - FLASH_ERR_WRP +*\*\ - FLASH_EOP +*\*\ - FLASH_ERR_RDP2 +*\*\ - FLASH_TIMEOUT +**/ +FLASH_STS FLASH_Option_Bytes_User4_RDP2_Program(uint8_t option_byte_rdp2,uint8_t option_byte_user4) +{ + FLASH_STS status_value = FLASH_EOP; + + /* Get the actual read protection L2 Option Byte value */ + if (FLASH_Read_Out_Protection_L2_Status_Get() != RESET) + { + return FLASH_ERR_RDP2; + } + else + { + /*No process*/ + } + + /* Clears the FLASH's pending flags */ + FLASH_Flag_Status_Clear(FLASH_STS_CLRFLAG); + /* Wait for last operation to be completed */ + status_value = FLASH_Last_Operation_Wait(PROGRAM_TIMEOUT); + + if (status_value == FLASH_EOP) + { + Option_Bytes_Unlock(); + /* Enables the Option Bytes Programming operation */ + FLASH->CTRL |= FLASH_CTRL_SET_OPTPG; + OBT->USER4_RDP2 = (((uint32_t)option_byte_user4) << FLASH_DATA0_DATA1_OFFSET) \ + | ((uint32_t)option_byte_rdp2); + /* Wait for last operation to be completed */ + status_value = FLASH_Last_Operation_Wait(PROGRAM_TIMEOUT); + if (status_value != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CTRL &= FLASH_CTRL_RESET_OPTPG; + } + else + { + /*No process*/ + } + } + else + { + /*No process*/ + } + /* Return the Option Byte Data Program status_value */ + return status_value; +} + + + +/** +*\*\name FLASH_Read_Out_Protection_L1_Enable +*\*\fun Enables the read out protection. +*\*\note If the user has already programmed the other option bytes before calling +*\*\ this function, he must re-program them since this function erases all option bytes. +*\*\ This function can be used for N32G003 devices. +*\*\param none +*\*\return FLASH_STS : +*\*\ - FLASH_BUSY +*\*\ - FLASH_ERR_PG +*\*\ - FLASH_ERR_WRP +*\*\ - FLASH_EOP +*\*\ - FLASH_ERR_RDP2 +*\*\ - FLASH_TIMEOUT +**/ +FLASH_STS FLASH_Read_Out_Protection_L1_Enable(void) +{ + uint32_t user_temp; + FLASH_STS status_value = FLASH_EOP; + + user_temp = ((FLASH_OB_USER_MSK & FLASH->OB) << FLASH_OB_TO_USER_OFFSET); + + /* Get the actual read protection L2 Option Byte value */ + if (FLASH_Read_Out_Protection_L2_Status_Get() != RESET) + { + return FLASH_ERR_RDP2; + } + else + { + /*No process*/ + } + + /* Clears the FLASH's pending flags */ + FLASH_Flag_Status_Clear(FLASH_STS_CLRFLAG); + /* Wait for last operation to be completed */ + status_value = FLASH_Last_Operation_Wait(ERASE_TIMEOUT); + + if (status_value == FLASH_EOP) + { + Option_Bytes_Unlock(); + FLASH->CTRL |= FLASH_CTRL_SET_OPTER; + FLASH->CTRL |= FLASH_CTRL_SET_START; + /* Wait for last operation to be completed */ + status_value = FLASH_Last_Operation_Wait(ERASE_TIMEOUT); + if (status_value == FLASH_EOP) + { + /* Clears the FLASH's pending flags */ + FLASH_Flag_Status_Clear(FLASH_STS_CLRFLAG); + + /* if the erase operation is completed, disable the OPTER Bit */ + FLASH->CTRL &= FLASH_CTRL_RESET_OPTER; + /* Enable the Option Bytes Programming operation */ + FLASH->CTRL |= FLASH_CTRL_SET_OPTPG; + /*enable new state of the ReadOut Protection*/ + OBT->USER_RDP = (FLASH_USER_MASK & user_temp); + /* Wait for last operation to be completed */ + status_value = FLASH_Last_Operation_Wait(ERASE_TIMEOUT); + + if (status_value != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CTRL &= FLASH_CTRL_RESET_OPTPG; + } + else + { + /*No process*/ + } + } + else + { + if (status_value != FLASH_TIMEOUT) + { + /* Disable the OPTER Bit */ + FLASH->CTRL &= FLASH_CTRL_RESET_OPTER; + } + else + { + /*No process*/ + } + } + } + else + { + /*No process*/ + } + /* Return the protection operation status_value */ + return status_value; +} + + +/** +*\*\name FLASH_Read_Out_Protection_L1_Disable +*\*\fun Disables the read out protection. +*\*\note If the user has already programmed the other option bytes before calling +*\*\ this function, he must re-program them since this function erases all option bytes. +*\*\ This function can be used for N32G003 devices. +*\*\param none +*\*\return FLASH_STS : +*\*\ - FLASH_BUSY +*\*\ - FLASH_ERR_PG +*\*\ - FLASH_ERR_WRP +*\*\ - FLASH_EOP +*\*\ - FLASH_ERR_RDP2 +*\*\ - FLASH_TIMEOUT +**/ +FLASH_STS FLASH_Read_Out_Protection_L1_Disable(void) +{ + uint32_t user_temp; + FLASH_STS status_value = FLASH_EOP; + + user_temp = ((FLASH_OB_USER_MSK & FLASH->OB) << FLASH_OB_TO_USER_OFFSET); + + /* Get the actual read protection L2 Option Byte value */ + if (FLASH_Read_Out_Protection_L2_Status_Get() != RESET) + { + return FLASH_ERR_RDP2; + } + else + { + /*No process*/ + } + + /* Clears the FLASH's pending flags */ + FLASH_Flag_Status_Clear(FLASH_STS_CLRFLAG); + /* Wait for last operation to be completed */ + status_value = FLASH_Last_Operation_Wait(ERASE_TIMEOUT); + + if (status_value == FLASH_EOP) + { + Option_Bytes_Unlock(); + FLASH->CTRL |= FLASH_CTRL_SET_OPTER; + FLASH->CTRL |= FLASH_CTRL_SET_START; + /* Wait for last operation to be completed */ + status_value = FLASH_Last_Operation_Wait(ERASE_TIMEOUT); + if (status_value == FLASH_EOP) + { + /* Clears the FLASH's pending flags */ + FLASH_Flag_Status_Clear(FLASH_STS_CLRFLAG); + + /* if the erase operation is completed, disable the OPTER Bit */ + FLASH->CTRL &= FLASH_CTRL_RESET_OPTER; + /* Enable the Option Bytes Programming operation */ + FLASH->CTRL |= FLASH_CTRL_SET_OPTPG; + /* Disables the read out protection */ + OBT->USER_RDP = ((FLASH_L1_RDP_KEY & FLASH_RDP1_MASK) | user_temp); + /* Wait for last operation to be completed */ + status_value = FLASH_Last_Operation_Wait(ERASE_TIMEOUT); + + if (status_value != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CTRL &= FLASH_CTRL_RESET_OPTPG; + } + else + { + /*No process*/ + } + } + else + { + if (status_value != FLASH_TIMEOUT) + { + /* Disable the OPTER Bit */ + FLASH->CTRL &= FLASH_CTRL_RESET_OPTER; + } + else + { + /*No process*/ + } + } + } + else + { + /*No process*/ + } + /* Return the protection operation status_value */ + return status_value; +} + + +/** +*\*\name FLASH_Read_Out_Protection_L2_Enable +*\*\fun Enables or disables the read out protection L2. +*\*\note If the user has already programmed the other option bytes before calling +*\*\ this function, he must re-program them since this function erases all option bytes. +*\*\ This function can be used for N32G003 devices. +*\*\param none +*\*\return FLASH_STS : +*\*\ - FLASH_BUSY +*\*\ - FLASH_ERR_PG +*\*\ - FLASH_ERR_WRP +*\*\ - FLASH_EOP +*\*\ - FLASH_ERR_RDP2 +*\*\ - FLASH_TIMEOUT +**/ +FLASH_STS FLASH_Read_Out_Protection_L2_Enable(void) +{ + uint32_t user_temp; + FLASH_STS status_value = FLASH_EOP; + + user_temp = ((FLASH_OB_USER_MSK & FLASH->OB) << FLASH_OB_TO_USER_OFFSET); + + /* Get the actual read protection L1 Option Byte value */ + if (FLASH_Read_Out_Protection_Status_Get() == RESET) + { + user_temp |= (FLASH_L1_RDP_KEY & FLASH_RDP1_MASK); + } + else + { + /*No process*/ + } + /* Get the actual read protection L2 Option Byte value */ + if (FLASH_Read_Out_Protection_L2_Status_Get() != RESET) + { + return FLASH_ERR_RDP2; + } + else + { + /*No process*/ + } + + /* Clears the FLASH's pending flags */ + FLASH_Flag_Status_Clear(FLASH_STS_CLRFLAG); + /* Wait for last operation to be completed */ + status_value = FLASH_Last_Operation_Wait(ERASE_TIMEOUT); + + if (status_value == FLASH_EOP) + { + Option_Bytes_Unlock(); + FLASH->CTRL |= FLASH_CTRL_SET_OPTER; + FLASH->CTRL |= FLASH_CTRL_SET_START; + /* Wait for last operation to be completed */ + status_value = FLASH_Last_Operation_Wait(ERASE_TIMEOUT); + if (status_value == FLASH_EOP) + { + /* Clears the FLASH's pending flags */ + FLASH_Flag_Status_Clear(FLASH_STS_CLRFLAG); + + /* if the erase operation is completed, disable the OPTER Bit */ + FLASH->CTRL &= FLASH_CTRL_RESET_OPTER; + /* Enable the Option Bytes Programming operation */ + FLASH->CTRL |= FLASH_CTRL_SET_OPTPG; + + OBT->USER_RDP = user_temp; + /* Wait for last operation to be completed */ + status_value = FLASH_Last_Operation_Wait(ERASE_TIMEOUT); + + if (status_value == FLASH_EOP) + { + /* Clears the FLASH's pending flags */ + FLASH_Flag_Status_Clear(FLASH_STS_CLRFLAG); + + /* Enables the read out protection L2 */ + OBT->USER4_RDP2 = FLASH_L2_RDP_KEY; + + /* Wait for last operation to be completed */ + status_value = FLASH_Last_Operation_Wait(ERASE_TIMEOUT); + } + else + { + /*No process*/ + } + + if (status_value != FLASH_TIMEOUT) + { + /* if the program operation is completed, disable the OPTPG Bit */ + FLASH->CTRL &= FLASH_CTRL_RESET_OPTPG; + } + else + { + /*No process*/ + } + } + else + { + if (status_value != FLASH_TIMEOUT) + { + /* Disable the OPTER Bit */ + FLASH->CTRL &= FLASH_CTRL_RESET_OPTER; + } + else + { + /*No process*/ + } + } + } + else + { + /*No process*/ + } + /* Return the protection operation status_value */ + return status_value; +} + + +/** +*\*\name FLASH_Option_Bytes_User_Get +*\*\fun Returns the FLASH User Option Bytes values. +*\*\note This function can be used for N32G003 devices. +*\*\param option_byte_bit +*\*\ - FLASH_OB_IWDG_SW +*\*\ - FLASH_OB_STOP_NORST +*\*\ - FLASH_OB_PD_NORST +*\*\ - FLASH_OB_NOLOCK_BOOT +*\*\ - FLASH_OB_PA0_NRST +*\*\return FlagStatus : +*\*\ - SET +*\*\ - RESET +**/ +FlagStatus FLASH_Option_Bytes_User_Get(uint32_t option_byte_bit) +{ + if(((FLASH->OB >> FLASH_OB_OFFSET) & option_byte_bit) != (uint32_t)RESET) + { + return SET; + } + else + { + return RESET; + } +} + + +/** +*\*\name FLASH_Option_Bytes_User2_Get +*\*\fun Returns the FLASH Option Bytes LVRCNT values. +*\*\note This function can be used for N32G003 devices. +*\*\param none +*\*\return LVRCNT: +*\*\ - 0x00 to 0xFF. +**/ +uint32_t FLASH_Option_Bytes_User2_Get(void) +{ + /* Return the User Option Byte2 */ + return (uint32_t)(FLASH->USER & FLASH_USER_LVRCNT_MSK); +} + + +/** +*\*\name FLASH_User_LVRLS_Get +*\*\fun Returns the FLASH Option Bytes LVRLS values. +*\*\note This function can be used for N32G003 devices. +*\*\param none +*\*\return LVRLS: +*\*\ - 0x00 to 0x0F. +**/ +uint32_t FLASH_User_LVRLS_Get(void) +{ + /* Return the Option Byte User3 LVRLS */ + return (uint32_t)((FLASH->USER & FLASH_USER_LVRLS_MSK) >> FLASH_USER3_OFFSET); +} + + +/** +*\*\name FLASH_Option_Bytes_User3_Get +*\*\fun Returns the FLASH Option Bytes User3 values. +*\*\note This function can be used for N32G003 devices. +*\*\param option_byte_bit +*\*\ - FLASH_OB_USER_LVR_DISABLE +*\*\ - FLASH_OB_USER_LVRFIL_DISABLE +*\*\ - FLASH_OB_USER_LVRRST_DISABLE +*\*\return FlagStatus : +*\*\ - SET +*\*\ - RESET +**/ +FlagStatus FLASH_Option_Bytes_User3_Get(uint32_t option_byte_bit) +{ + if(((FLASH->USER >> FLASH_USER3_OFFSET) & option_byte_bit) != (uint32_t)RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/** +*\*\name FLASH_Option_Bytes_User4_Get +*\*\fun Returns the FLASH Option Bytes LVRCNT values. +*\*\note This function can be used for N32G003 devices. +*\*\param none +*\*\return LVRCNT: +*\*\ - 0x00 to 0xFF. +**/ +uint32_t FLASH_Option_Bytes_User4_Get(void) +{ + /* Return the Option Byte User4 */ + return (uint32_t)((FLASH->USER & FLASH_USER_POR_DELAY_MSK) >> FLASH_USER4_OFFSET); +} + + +/** +*\*\name FLASH_Read_Out_Protection_Status_Get +*\*\fun Checks whether the FLASH Read Out Protection status_value is set or not. +*\*\note This function can be used for N32G003 devices. +*\*\param none +*\*\return FlagStatus : +*\*\ - SET +*\*\ - RESET +**/ +FlagStatus FLASH_Read_Out_Protection_Status_Get(void) +{ + if ((FLASH->OB & FLASH_RDPRTL1_MSK) != (uint32_t)RESET) + { + return SET; + } + else + { + return RESET; + } +} + + +/** +*\*\name FLASH_Read_Out_Protection_L2_Status_Get +*\*\fun Checks whether the FLASH Read Out Protection L2 status_value is set or not. +*\*\note This function can be used for N32G003 devices. +*\*\param none +*\*\return FlagStatus : +*\*\ - SET +*\*\ - RESET +**/ +FlagStatus FLASH_Read_Out_Protection_L2_Status_Get(void) +{ + if ((FLASH->OB & FLASH_RDPRTL2_MSK) != (uint32_t)RESET) + { + return SET; + } + else + { + return RESET; + } +} + + + + + +/** +*\*\name FLASH_Prefetch_Buffer_Status_Get +*\*\fun Checks whether the FLASH Prefetch Buffer status_value is set or not. +*\*\note This function can be used for N32G003 devices. +*\*\param none +*\*\return FlagStatus : +*\*\ - SET +*\*\ - RESET +**/ +FlagStatus FLASH_Prefetch_Buffer_Status_Get(void) +{ + if ((FLASH->AC & FLASH_PRFTBS_MSK) != (uint32_t)RESET) + { + return SET; + } + else + { + return RESET; + } +} + + + +/** +*\*\name FLASH_Interrupt_Enable +*\*\fun Enables the specified FLASH interrupts. +*\*\note This function can be used for N32G003 devices. +*\*\param flash_interrupts : +*\*\ - FLASH_INT_ERROR FLASH Error Interrupt +*\*\ - FLASH_INT_EOP FLASH end of operation Interrupt +*\*\return none +**/ +void FLASH_Interrupt_Enable(uint32_t flash_interrupts) +{ + + /* Enable the interrupt sources */ + FLASH->CTRL |= flash_interrupts; +} + + +/** +*\*\name FLASH_Interrupt_Disable +*\*\fun Disables the specified FLASH interrupts. +*\*\note This function can be used for N32G003 devices. +*\*\param flash_interrupts : +*\*\ - FLASH_INT_ERROR FLASH Error Interrupt +*\*\ - FLASH_INT_EOP FLASH end of operation Interrupt +*\*\return none +**/ +void FLASH_Interrupt_Disable(uint32_t flash_interrupts) +{ + /* Disable the interrupt sources */ + FLASH->CTRL &= ~(uint32_t)flash_interrupts; +} + + + + +/** +*\*\name FLASH_Flag_Status_Get +*\*\fun Checks whether the specified FLASH flag is set or not. +*\*\note This function can be used for N32G003 devices. +*\*\param flash_flag : +*\*\ - FLASH_FLAG_BUSY FLASH Busy flag +*\*\ - FLASH_FLAG_PGERR FLASH Program error flag +*\*\ - FLASH_FLAG_WRPERR FLASH Write protected error flag +*\*\ - FLASH_FLAG_EOP FLASH End of Operation flag +*\*\return FlagStatus : +*\*\ - SET +*\*\ - RESET +**/ +FlagStatus FLASH_Flag_Status_Get(uint32_t flash_flag) +{ + if ((FLASH->STS & flash_flag) != (uint32_t)RESET) + { + return SET; + } + else + { + return RESET; + } +} + + +/** +*\*\name FLASH_Option_Bytes_Flag_Get +*\*\fun Checks whether the specified FLASH flag is set or not. +*\*\note This function can be used for N32G003 devices. +*\*\param flash_flag : +*\*\ - FLASH_FLAG_OBERR FLASH Option Byte error flag +*\*\return FlagStatus : +*\*\ - SET +*\*\ - RESET +**/ +FlagStatus FLASH_Option_Bytes_Flag_Get(uint32_t flash_flag) +{ + if ((FLASH->OB & flash_flag) != (uint32_t)RESET) + { + return SET; + } + else + { + return RESET; + } +} + + +/** +*\*\name FLASH_Flag_Status_Clear +*\*\fun Clears the FLASH's status flags. +*\*\note This function can be used for N32G003 devices. +*\*\param flash_flag : +*\*\ - FLASH_FLAG_PGERR FLASH Program error flag +*\*\ - FLASH_FLAG_WRPERR FLASH Write protected error flag +*\*\ - FLASH_FLAG_EOP FLASH End of Operation flag +*\*\return none +**/ +void FLASH_Flag_Status_Clear(uint32_t flash_flag) +{ + /* Clear the flags */ + FLASH->STS |= flash_flag; +} + + + +/** +*\*\name FLASH_Status_Get +*\*\fun Returns the FLASH_STS. +*\*\note This function can be used for N32G003 devices. +*\*\param none +*\*\return FLASH_STS : +*\*\ - FLASH_BUSY +*\*\ - FLASH_ERR_PG +*\*\ - FLASH_ERR_WRP +*\*\ - FLASH_EOP +**/ +FLASH_STS FLASH_Status_Get(void) +{ + FLASH_STS status_value = FLASH_EOP; + + if ((FLASH->STS & FLASH_FLAG_BUSY) == FLASH_FLAG_BUSY) + { + status_value = FLASH_BUSY; + } + else + { + if ((FLASH->STS & FLASH_FLAG_PGERR) != RESET) + { + status_value = FLASH_ERR_PG; + } + else + { + if ((FLASH->STS & FLASH_FLAG_WRPERR) != RESET) + { + status_value = FLASH_ERR_WRP; + } + else + { + status_value = FLASH_EOP; + } + } + } + + /* Return the FLASH_STS */ + return status_value; +} + + +/** +*\*\name FLASH_Last_Operation_Wait +*\*\fun Waits for a Flash operation to complete or a timeout to occur. +*\*\note This function can be used for N32G003 devices. +*\*\param timeout : +*\*\ - ERASE_TIMEOUT +*\*\ - PROGRAM_TIMEOUT +*\*\return FLASH_STS: The returned value can be: +*\*\ - FLASH_BUSY +*\*\ - FLASH_ERR_PG +*\*\ - FLASH_ERR_WRP +*\*\ - FLASH_EOP +*\*\ - FLASH_TIMEOUT +**/ +FLASH_STS FLASH_Last_Operation_Wait(uint32_t timeout) +{ + FLASH_STS status_value = FLASH_EOP; + + /* Check for the Flash status_value */ + status_value = FLASH_Status_Get(); + /* Wait for a Flash operation to complete or a timeout to occur */ + while ((status_value == FLASH_BUSY) && (timeout != 0x00)) + { + status_value = FLASH_Status_Get(); + timeout--; + } + if (timeout == 0x00) + { + status_value = FLASH_TIMEOUT; + } + /* Return the operation status_value */ + return status_value; +} + + +/** +*\*\name FLASH_VTOR_Address_Set +*\*\fun Set interrupt vector offset address. +*\*\note This function can be used for N32G003 devices. +*\*\param VTOR_address : +*\*\ - 0x00000000~0x7FFFFFFF +*\*\param VTOR_cmd : +*\*\ - FLASH_VTOR_ENABLE +*\*\ - FLASH_VTOR_DISABLE +*\*\return none +**/ +void FLASH_VTOR_Address_Set(uint32_t VTOR_address,uint32_t VTOR_cmd) +{ + /* Set VTOR address */ + FLASH->VTOR = (VTOR_cmd | VTOR_address); +} + + + diff --git a/firmware/n32g003_std_periph_driver/src/n32g003_gpio.c b/firmware/n32g003_std_periph_driver/src/n32g003_gpio.c new file mode 100644 index 0000000..68337ce --- /dev/null +++ b/firmware/n32g003_std_periph_driver/src/n32g003_gpio.c @@ -0,0 +1,989 @@ +/** +* Copyright (c) 2022, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** +*\*\file n32g003_gpio.c +*\*\author Nations +*\*\version v1.0.0 +*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. +**/ + +#include "n32g003_gpio.h" + + +/** + *\*\name GPIO_Reset. + *\*\fun Reset the GPIOx peripheral registers to their default reset values. + *\*\param GPIOx : + *\*\ - GPIOA + *\*\ - GPIOB + *\*\return none + */ +void GPIO_Reset(GPIO_Module* GPIOx) +{ + if (GPIOx == GPIOA) + { + RCC_Peripheral_Reset(RCC_RST_GPIOARST); + } + else if (GPIOx == GPIOB) + { + RCC_Peripheral_Reset(RCC_RST_GPIOBRST); + } + else + { + return; + } +} + +/** + *\*\name GPIO_Alternate_Function_Reset. + *\*\fun Reset the Alternate Function registers to their default reset values. + *\*\param none + *\*\return none + */ +void GPIO_Alternate_Function_Reset(void) +{ + RCC_Peripheral_Reset(RCC_RST_AFIORST); +} + + +/** + *\*\name GPIOA_Pin_Reset. + *\*\fun Reset the GPIOA peripheral registers to it's default reset values. + *\*\param pin : + *\*\ - GPIO_PIN_0 + *\*\ - GPIO_PIN_1 + *\*\ - GPIO_PIN_2 + *\*\ - GPIO_PIN_3 + *\*\ - GPIO_PIN_4 + *\*\ - GPIO_PIN_5 + *\*\ - GPIO_PIN_6 + *\*\ - GPIO_PIN_7 + *\*\ - GPIO_PIN_8 + *\*\ - GPIO_PIN_9 + *\*\ - GPIO_PIN_10 + *\*\ - GPIO_PIN_11 + *\*\ - GPIO_PIN_12 + *\*\ - GPIO_PIN_13 + *\*\ - GPIO_PIN_14 + *\*\ - GPIO_PIN_15 + *\*\ - GPIO_PIN_ALL + *\*\return none + */ +void GPIOA_Pin_Reset(uint16_t pin) +{ + uint32_t position = 0x00U; + uint32_t current_pin = 0x00U; + + while((pin >> position) != 0) + { + /* Get the IO position */ + current_pin = (pin) & (IO_POSITION_MASK << position); + + if(current_pin) + { + if(position == GPIOA_POSITION1 || position == GPIOA_POSITION2) + { + /* Configure IO Direction in alternate Mode */ + GPIOA->PMODE |= (GPIO_AF_MODE << (position * MULTIPLIER_FACTOR_2)); + } + else + { + /* Configure IO Direction in analog Mode */ + GPIOA->PMODE |= (GPIO_ANALOG_MODE << (position * MULTIPLIER_FACTOR_2)); + } + + /* Configure the default Alternate Function in current IO */ + if(position & AF_SELECTION_MASK) + { + if(position == GPIOA_POSITION1 || position == GPIOA_POSITION2) + { + GPIOA->AFH &= ~(GPIO_AF_MASK << ((position & (uint32_t)AF_WRITE_POSITION_MASK) * MULTIPLIER_FACTOR_4)); + } + else + { + GPIOA->AFH |= (GPIO_AF_MASK << ((position & (uint32_t)AF_WRITE_POSITION_MASK) * MULTIPLIER_FACTOR_4)); + } + } + else + { + GPIOA->AFL |= (GPIO_AF_MASK << ((position & (uint32_t)AF_WRITE_POSITION_MASK) * MULTIPLIER_FACTOR_4)); + } + + /* Reset GPIO output type to push-pull output */ + GPIOA->POTYPE &= ~(GPIO_POTYPE_MASK << position); + + + if(position == GPIOA_POSITION1) + { + /* Reset the GPIO pull mode to pull-up */ + GPIOA->PUPD |= (GPIO_PU_MODE << (position * MULTIPLIER_FACTOR_2)); + } + else if(position == GPIOA_POSITION2) + { + /* Reset the GPIO pull mode to pull-down */ + GPIOA->PUPD |= (GPIO_PD_MODE << (position * MULTIPLIER_FACTOR_2)); + } + else + { + /* Reset the GPIO pull mode to no-pull */ + GPIOA->PUPD &= ~(GPIO_PUPD_MASK << (position * MULTIPLIER_FACTOR_2)); + } + + /* Reset the GPIO slew rate to slow */ + GPIOA->SR |= (GPIO_SR_SLOW << position); + + /* Reset the GPIO high driver capacity */ + GPIOA->DS &= ~(GPIO_LOW_DRIVER << position); + } + position++; + } +} + +/** + *\*\name GPIOB_Pin_Reset. + *\*\fun Reset the GPIOB peripheral registers to it's default reset values. + *\*\param pin : + *\*\ - GPIO_PIN_0 + *\*\ - GPIO_PIN_1 + *\*\return none + */ +void GPIOB_Pin_Reset(uint16_t pin) +{ + uint32_t position = 0x00U; + uint32_t current_pin = 0x00U; + + while((pin >> position) != 0) + { + /* Get the IO position */ + current_pin = (pin) & (IO_POSITION_MASK << position); + + if(current_pin) + { + /** Reset GPIO pin mode **/ + + /* Configure IO Direction in analog Mode */ + GPIOB->PMODE |= (GPIO_ANALOG_MODE << (position * MULTIPLIER_FACTOR_2)); + + /** Configure the default Alternate Function in current IO **/ + GPIOB->AFL |= (GPIO_AF_MASK << ((position & (uint32_t)AF_WRITE_POSITION_MASK) * MULTIPLIER_FACTOR_4)); + + /* Reset GPIO output type to push-pull output */ + GPIOB->POTYPE &= ~(GPIO_POTYPE_MASK << position); + + /* Reset the GPIO pull mode to no-pull */ + GPIOB->PUPD &= ~(GPIO_PUPD_MASK << (position * MULTIPLIER_FACTOR_2)); + + /* Reset the GPIO slew rate to slow */ + GPIOB->SR |= (GPIO_SR_SLOW << position); + + /* Reset the GPIO high driver capacity */ + GPIOB->DS &= ~(GPIO_LOW_DRIVER << position); + } + position++; + } +} + + +/** + *\*\name GPIO_Alternate_Set. + *\*\fun Configure GPIO alternate function. + *\*\param GPIOx : + *\*\ - GPIOA + *\*\ - GPIOB + *\*\ Note: When selects the GPIOB, Only GPIO_PIN_0 and GPIO_PIN_1 are valid + *\*\param alternate + *\*\ - Refer to the "alternate_function" parameter + *\*\ list of the GPIO_Pin_Remap_Set() function + *\*\param position + *\*\ - 0x00 ~ 0x0F 0x00 represents GPIO_PIN_0, + *\*\ 0x01 represents GPIO_PIN_1 + *\*\ ... + *\*\ 0x0F represents GPIO_PIN_15 + *\*\return none + */ +void GPIO_Alternate_Set(GPIO_Module* GPIOx, uint32_t alternate, uint32_t position) +{ + uint32_t temp_value = 0x00U; + + /* Configure Alternate function mapped with the current IO */ + if(position & AF_SELECTION_MASK) + { + temp_value = GPIOx->AFH; + temp_value &= ~(GPIO_AF_MASK << ((uint32_t)(position & (uint32_t)AF_WRITE_POSITION_MASK) * MULTIPLIER_FACTOR_4)); + temp_value |= ((uint32_t)alternate << ((uint32_t)(position & (uint32_t)AF_WRITE_POSITION_MASK) * MULTIPLIER_FACTOR_4)); + GPIOx->AFH = temp_value; + } + else + { + temp_value = GPIOx->AFL; + temp_value &= ~(GPIO_AF_MASK << ((uint32_t)(position & (uint32_t)AF_WRITE_POSITION_MASK) * MULTIPLIER_FACTOR_4)); + temp_value |= ((uint32_t)alternate << ((uint32_t)(position & (uint32_t)AF_WRITE_POSITION_MASK) * MULTIPLIER_FACTOR_4)); + GPIOx->AFL = temp_value; + } +} + + +/** + *\*\name GPIO_Mode_Set. + *\*\fun Configure GPIO mode. + *\*\param GPIOx : + *\*\ - GPIOA + *\*\ - GPIOB + *\*\ Note: When selects the GPIOB, Only GPIO_PIN_0 and GPIO_PIN_1 are valid + *\*\param mode + *\*\ - GPIO_MODE_INPUT + *\*\ - GPIO_MODE_OUT_PP + *\*\ - GPIO_MODE_OUT_OD + *\*\ - GPIO_MODE_AF_PP + *\*\ - GPIO_MODE_AF_OD + *\*\ - GPIO_MODE_ANALOG + *\*\param position + *\*\ - 0x00 ~ 0x0F 0x00 represents GPIO_PIN_0, + *\*\ 0x01 represents GPIO_PIN_1 + *\*\ ... + *\*\ 0x0F represents GPIO_PIN_15 + *\*\return none + */ +void GPIO_Mode_Set(GPIO_Module* GPIOx, uint32_t mode, uint32_t position) +{ + uint32_t temp_value = 0x00U; + uint32_t temp = 0x00U; + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp_value = GPIOx->PMODE; + temp = (mode & GPIO_SET_PMODE_MASK); + temp_value &= ~(GPIO_PMODE_MASK << (position * MULTIPLIER_FACTOR_2)); + temp_value |= (temp << (position * MULTIPLIER_FACTOR_2)); + GPIOx->PMODE = temp_value; + + /* In case of Output or Alternate function mode selection */ + if((mode == GPIO_MODE_OUT_PP) || (mode == GPIO_MODE_OUT_OD) || + (mode == GPIO_MODE_AF_PP) || (mode == GPIO_MODE_AF_OD)) + { + /* Configure the IO Output Type */ + temp_value = GPIOx->POTYPE; + temp_value &= ~(GPIO_POTYPE_MASK << position); + temp_value |= (((mode & GPIO_OUTPUT_TYPE_MASK) >> SHIFT_POTYPE) << position); + GPIOx->POTYPE = temp_value; + } +} + + +/** + *\*\name GPIO_Pull_Set. + *\*\fun Configure pull mode. + *\*\param GPIOx : + *\*\ - GPIOA + *\*\ - GPIOB + *\*\ Note: When selects the GPIOB, Only GPIO_PIN_0 and GPIO_PIN_1 are valid + *\*\param pull + *\*\ - GPIO_NO_PULL + *\*\ - GPIO_PULL_UP + *\*\ - GPIO_PULL_DOWN + *\*\param position + *\*\ - 0x00 ~ 0x0F 0x00 represents GPIO_PIN_0, + *\*\ 0x01 represents GPIO_PIN_1 + *\*\ ... + *\*\ 0x0F represents GPIO_PIN_15 + *\*\return none + */ +void GPIO_Pull_Set(GPIO_Module* GPIOx, uint32_t pull, uint32_t position) +{ + uint32_t temp_value = 0x00U; + + /* Configure pull-down mode */ + temp_value = GPIOx->PUPD; + temp_value &= ~(GPIO_PUPD_MASK << (position * MULTIPLIER_FACTOR_2)); + temp_value |= (pull << (position * MULTIPLIER_FACTOR_2)); + GPIOx->PUPD = temp_value; +} + + +/** + *\*\name GPIO_SlewRate_Set. + *\*\fun GPIO slew rate configuration. + *\*\param GPIOx : + *\*\ - GPIOA + *\*\ - GPIOB + *\*\ Note: When selects the GPIOB, Only GPIO_PIN_0 and GPIO_PIN_1 are valid + *\*\param slew_rate + *\*\ - GPIO_SLEW_RATE_FAST + *\*\ - GPIO_SLEW_RATE_SLOW + *\*\param position + *\*\ - 0x00 ~ 0x0F 0x00 represents GPIO_PIN_0, + *\*\ 0x01 represents GPIO_PIN_1 + *\*\ ... + *\*\ 0x0F represents GPIO_PIN_15 + *\*\return none + */ +void GPIO_SlewRate_Set(GPIO_Module* GPIOx, uint32_t slew_rate, uint32_t position) +{ + uint32_t temp_value = 0x00U; + + /* Configure slew rate */ + temp_value = GPIOx->SR; + temp_value &= ~(GPIO_SR_MASK << position); + temp_value |= (slew_rate << position); + GPIOx->SR = temp_value; +} + + +/** + *\*\name GPIO_Driver_Set. + *\*\fun GPIO driver configuration. + *\*\param GPIOx : + *\*\ - GPIOA + *\*\ - GPIOB + *\*\ Note: When selects the GPIOB, Only GPIO_PIN_0 and GPIO_PIN_1 are valid + *\*\param current + *\*\ - GPIO_HIGH_DREIVE + *\*\ - GPIO_LOW_DREIVE + *\*\param position + *\*\ - 0x00 ~ 0x0F 0x00 represents GPIO_PIN_0, + *\*\ 0x01 represents GPIO_PIN_1 + *\*\ ... + *\*\ 0x0F represents GPIO_PIN_15 + *\*\return none + */ +void GPIO_Driver_Set(GPIO_Module* GPIOx, uint32_t current, uint32_t position) +{ + uint32_t temp_value = 0x00U; + + temp_value = GPIOx->DS; + temp_value &= ~(GPIO_DS_MASK << position); + temp_value |= (current << position); + GPIOx->DS = temp_value; +} + + +/** + *\*\name GPIO_Peripheral_Initialization. + *\*\fun Initialize the GPIOx peripheral with the value of the GPIO_InitStruct structure. + *\*\param GPIOx : + *\*\ - GPIOA + *\*\ - GPIOB + *\*\param GPIO_InitStructure : + *\*\ pointer to GPIO_InitType structure. + *\*\return none + */ +void GPIO_Peripheral_Initialize(GPIO_Module* GPIOx, GPIO_InitType* GPIO_InitStructure) +{ + uint32_t position = 0x00U; + uint32_t current_pin = 0x00U; + + while(((GPIO_InitStructure->Pin) >> position) != 0) + { + /* Get the IO position */ + current_pin = (GPIO_InitStructure->Pin) & (IO_POSITION_MASK << position); + if(current_pin) + { + /* Configure GPIO alternate function */ + GPIO_Alternate_Set(GPIOx, GPIO_InitStructure->GPIO_Alternate, position); + + /* Configure GPIO mode */ + GPIO_Mode_Set(GPIOx, GPIO_InitStructure->GPIO_Mode, position); + + /* Configure pull-down or pull-up mode */ + GPIO_Pull_Set(GPIOx, GPIO_InitStructure->GPIO_Pull, position); + + /* Configure slew rate */ + GPIO_SlewRate_Set(GPIOx, GPIO_InitStructure->GPIO_Slew_Rate, position); + + /* Configuration drive capability */ + GPIO_Driver_Set(GPIOx, GPIO_InitStructure->GPIO_Current, position); + } + position++; + } +} + + +/** + *\*\name GPIO_Struct_Initialization. + *\*\fun Assign default values to each GPIO_InitStruct member. + *\*\param GPIO_InitStructure : + *\*\ pointer to GPIO_InitType structure. + *\*\return none + */ +void GPIO_Structure_Initialize(GPIO_InitType* GPIO_InitStruct) +{ + /* Reset GPIO structure member */ + GPIO_InitStruct->Pin = GPIO_PIN_ALL; + GPIO_InitStruct->GPIO_Slew_Rate = GPIO_SLEW_RATE_FAST; + GPIO_InitStruct->GPIO_Mode = GPIO_MODE_INPUT; + GPIO_InitStruct->GPIO_Alternate = GPIO_NO_AF; + GPIO_InitStruct->GPIO_Pull = GPIO_NO_PULL; + GPIO_InitStruct->GPIO_Current = GPIO_HIGH_DREIVE; +} + + +/** + *\*\name GPIO_Input_Pin_Data_Get. + *\*\fun Get the pin status on the specified input port. + *\*\param GPIOx : + *\*\ - GPIOA + *\*\ - GPIOB + *\*\ Note: When selects the GPIOB, Only GPIO_PIN_0 and GPIO_PIN_1 are valid + *\*\param pin : + *\*\ - GPIO_PIN_0 + *\*\ - GPIO_PIN_1 + *\*\ - GPIO_PIN_2 + *\*\ - GPIO_PIN_3 + *\*\ - GPIO_PIN_4 + *\*\ - GPIO_PIN_5 + *\*\ - GPIO_PIN_6 + *\*\ - GPIO_PIN_7 + *\*\ - GPIO_PIN_8 + *\*\ - GPIO_PIN_9 + *\*\ - GPIO_PIN_10 + *\*\ - GPIO_PIN_11 + *\*\ - GPIO_PIN_12 + *\*\ - GPIO_PIN_13 + *\*\ - GPIO_PIN_14 + *\*\ - GPIO_PIN_15 + *\*\return the pin state on the input port. + */ +uint8_t GPIO_Input_Pin_Data_Get(GPIO_Module* GPIOx, uint16_t pin) +{ + if ((GPIOx->PID & pin) != (uint32_t)PIN_RESET) + { + return (uint8_t)PIN_SET; + } + else + { + return (uint8_t)PIN_RESET; + } +} + + +/** + *\*\name GPIO_Input_Data_Get. + *\*\fun Get the input data on the designated GPIO port. + *\*\param GPIOx : + *\*\ - GPIOA + *\*\ - GPIOB + *\*\ Note: When selects the GPIOB, Only bit0 and bit1 are valid + *\*\return the data value on the GPIO input port. + */ +uint16_t GPIO_Input_Data_Get(GPIO_Module* GPIOx) +{ + return ((uint16_t)GPIOx->PID); +} + + +/** + *\*\name GPIO_Output_Pin_Data_Get. + *\*\fun Get the pin status on the specified output port. + *\*\param GPIOx : + *\*\ - GPIOA + *\*\ - GPIOB + *\*\ Note: When selects the GPIOB, Only GPIO_PIN_0 and GPIO_PIN_1 are valid + *\*\param pin : + *\*\ - GPIO_PIN_0 + *\*\ - GPIO_PIN_1 + *\*\ - GPIO_PIN_2 + *\*\ - GPIO_PIN_3 + *\*\ - GPIO_PIN_4 + *\*\ - GPIO_PIN_5 + *\*\ - GPIO_PIN_6 + *\*\ - GPIO_PIN_7 + *\*\ - GPIO_PIN_8 + *\*\ - GPIO_PIN_9 + *\*\ - GPIO_PIN_10 + *\*\ - GPIO_PIN_11 + *\*\ - GPIO_PIN_12 + *\*\ - GPIO_PIN_13 + *\*\ - GPIO_PIN_14 + *\*\ - GPIO_PIN_15 + *\*\return the pin state on the output port. + */ +uint8_t GPIO_Output_Pin_Data_Get(GPIO_Module* GPIOx, uint16_t pin) +{ + if ((GPIOx->POD & pin) != (uint32_t)PIN_RESET) + { + return (uint8_t)PIN_SET; + } + else + { + return (uint8_t)PIN_RESET; + } +} + + +/** + *\*\name GPIO_Output_Data_Get. + *\*\fun Get the output data on the designated GPIO port. + *\*\param GPIOx : + *\*\ - GPIOA + *\*\ - GPIOB + *\*\ Note: When selects the GPIOB, Only bit0 and bit1 are valid + *\*\return the data value on the GPIO output port. + */ +uint16_t GPIO_Output_Data_Get(GPIO_Module* GPIOx) +{ + return ((uint16_t)GPIOx->POD); +} + + +/** + *\*\name GPIO_Pins_Set. + *\*\fun Sets the selected data port bits. + *\*\param GPIOx : + *\*\ - GPIOA + *\*\ - GPIOB + *\*\ Note: When selects the GPIOB, Only GPIO_PIN_0 and GPIO_PIN_1 are valid + *\*\param pin : + *\*\ - GPIO_PIN_0 + *\*\ - GPIO_PIN_1 + *\*\ - GPIO_PIN_2 + *\*\ - GPIO_PIN_3 + *\*\ - GPIO_PIN_4 + *\*\ - GPIO_PIN_5 + *\*\ - GPIO_PIN_6 + *\*\ - GPIO_PIN_7 + *\*\ - GPIO_PIN_8 + *\*\ - GPIO_PIN_9 + *\*\ - GPIO_PIN_10 + *\*\ - GPIO_PIN_11 + *\*\ - GPIO_PIN_12 + *\*\ - GPIO_PIN_13 + *\*\ - GPIO_PIN_14 + *\*\ - GPIO_PIN_15 + *\*\return none + */ +void GPIO_Pins_Set(GPIO_Module* GPIOx, uint16_t pin) +{ + GPIOx->PBSC = pin; +} + +/** + *\*\name GPIO_Pins_Reset. + *\*\fun Reset the selected data port bits. + *\*\param GPIOx : + *\*\ - GPIOA + *\*\ - GPIOB + *\*\ Note: When selects the GPIOB, Only GPIO_PIN_0 and GPIO_PIN_1 are valid + *\*\param pin : + *\*\ - GPIO_PIN_0 + *\*\ - GPIO_PIN_1 + *\*\ - GPIO_PIN_2 + *\*\ - GPIO_PIN_3 + *\*\ - GPIO_PIN_4 + *\*\ - GPIO_PIN_5 + *\*\ - GPIO_PIN_6 + *\*\ - GPIO_PIN_7 + *\*\ - GPIO_PIN_8 + *\*\ - GPIO_PIN_9 + *\*\ - GPIO_PIN_10 + *\*\ - GPIO_PIN_11 + *\*\ - GPIO_PIN_12 + *\*\ - GPIO_PIN_13 + *\*\ - GPIO_PIN_14 + *\*\ - GPIO_PIN_15 + *\*\return none + */ +void GPIO_Pins_Reset(GPIO_Module* GPIOx, uint16_t pin) +{ + GPIOx->PBC = pin; +} + +/** + *\*\name GPIO_PBSC_Pins_Reset. + *\*\fun Sets the selected data port bits. + *\*\param GPIOx : + *\*\ - GPIOA + *\*\ - GPIOB + *\*\ Note: When selects the GPIOB, Only GPIO_PIN_0 and GPIO_PIN_1 are valid + *\*\param pin : + *\*\ - GPIO_PIN_0 + *\*\ - GPIO_PIN_1 + *\*\ - GPIO_PIN_2 + *\*\ - GPIO_PIN_3 + *\*\ - GPIO_PIN_4 + *\*\ - GPIO_PIN_5 + *\*\ - GPIO_PIN_6 + *\*\ - GPIO_PIN_7 + *\*\ - GPIO_PIN_8 + *\*\ - GPIO_PIN_9 + *\*\ - GPIO_PIN_10 + *\*\ - GPIO_PIN_11 + *\*\ - GPIO_PIN_12 + *\*\ - GPIO_PIN_13 + *\*\ - GPIO_PIN_14 + *\*\ - GPIO_PIN_15 + *\*\return none + */ +void GPIO_PBSC_Pins_Reset(GPIO_Module* GPIOx, uint16_t pin) +{ + GPIOx->PBSC = ((uint32_t)pin << SHIFT_PBSC_HIGH16); +} + + +/** + *\*\name GPIO_PBC_Pins_Reset. + *\*\fun Reset the selected data port bits. + *\*\param GPIOx : + *\*\ - GPIOA + *\*\ - GPIOB + *\*\ Note: When selects the GPIOB, Only GPIO_PIN_0 and GPIO_PIN_1 are valid + *\*\param pin : + *\*\ - GPIO_PIN_0 + *\*\ - GPIO_PIN_1 + *\*\ - GPIO_PIN_2 + *\*\ - GPIO_PIN_3 + *\*\ - GPIO_PIN_4 + *\*\ - GPIO_PIN_5 + *\*\ - GPIO_PIN_6 + *\*\ - GPIO_PIN_7 + *\*\ - GPIO_PIN_8 + *\*\ - GPIO_PIN_9 + *\*\ - GPIO_PIN_10 + *\*\ - GPIO_PIN_11 + *\*\ - GPIO_PIN_12 + *\*\ - GPIO_PIN_13 + *\*\ - GPIO_PIN_14 + *\*\ - GPIO_PIN_15 + *\*\return none + */ +void GPIO_PBC_Pins_Reset(GPIO_Module* GPIOx, uint16_t pin) +{ + GPIOx->PBC = pin; +} + + +/** + *\*\name GPIO_Write_Data. + *\*\fun Write data on the designated GPIO data port. + *\*\param GPIOx : + *\*\ - GPIOA + *\*\ - GPIOB + *\*\ Note: When selects the GPIOB, Only bit0 and bit1 are valid + *\*\param data_value : + *\*\ the value to be written to the port output data register. + *\*\return none + */ +void GPIO_Write(GPIO_Module* GPIOx, uint16_t data_value) +{ + GPIOx->POD = data_value; +} + + +/** + *\*\name GPIO_Pin_Toggle. + *\*\fun Toggle the specified port pin level. + *\*\param GPIOx : + *\*\ - GPIOA + *\*\ - GPIOB + *\*\ Note: When selects the GPIOB, Only GPIO_PIN_0 and GPIO_PIN_1 are valid + *\*\param pin : + *\*\ - GPIO_PIN_0 + *\*\ - GPIO_PIN_1 + *\*\ - GPIO_PIN_2 + *\*\ - GPIO_PIN_3 + *\*\ - GPIO_PIN_4 + *\*\ - GPIO_PIN_5 + *\*\ - GPIO_PIN_6 + *\*\ - GPIO_PIN_7 + *\*\ - GPIO_PIN_8 + *\*\ - GPIO_PIN_9 + *\*\ - GPIO_PIN_10 + *\*\ - GPIO_PIN_11 + *\*\ - GPIO_PIN_12 + *\*\ - GPIO_PIN_13 + *\*\ - GPIO_PIN_14 + *\*\ - GPIO_PIN_15 + *\*\return none + */ +void GPIO_Pin_Toggle(GPIO_Module* GPIOx, uint16_t pin) +{ + GPIOx->POD ^= pin; +} + + +/** + *\*\name GPIO_Pin_Lock_Set. + *\*\fun GPIO port lock register configuration. + *\*\param GPIOx : + *\*\ - GPIOA + *\*\ - GPIOB + *\*\ Note: When selects the GPIOB, Only GPIO_PIN_0 and GPIO_PIN_1 are valid + *\*\param pin : + *\*\ - GPIO_PIN_0 + *\*\ - GPIO_PIN_1 + *\*\ - GPIO_PIN_2 + *\*\ - GPIO_PIN_3 + *\*\ - GPIO_PIN_4 + *\*\ - GPIO_PIN_5 + *\*\ - GPIO_PIN_6 + *\*\ - GPIO_PIN_7 + *\*\ - GPIO_PIN_8 + *\*\ - GPIO_PIN_9 + *\*\ - GPIO_PIN_10 + *\*\ - GPIO_PIN_11 + *\*\ - GPIO_PIN_12 + *\*\ - GPIO_PIN_13 + *\*\ - GPIO_PIN_14 + *\*\ - GPIO_PIN_15 + *\*\return none + */ +void GPIO_Pin_Lock_Set(GPIO_Module* GPIOx, uint16_t pin) +{ + uint32_t temp_value = 0x00U; + + temp_value = (GPIO_PLOCKK_MASK | pin); + + /* PLOCKK and PLOCKx write 1 */ + GPIOx->PLOCK = temp_value; + + /* PLOCKK write 0 */ + GPIOx->PLOCK = pin; + + /* PLOCKK and PLOCKx write 1 */ + GPIOx->PLOCK = temp_value; + + /* PLOCKK read 0 */ + temp_value = GPIOx->PLOCK; + + /* PLOCKK read 1 */ + temp_value = GPIOx->PLOCK; +} + + +/** + *\*\name GPIO_Pin_Remap_Set. + *\*\fun Pin remapping configuration. + *\*\param port_source : + *\*\ - GPIOA_PORT_SOURCE + *\*\ - GPIOB_PORT_SOURCE + *\*\ Note: When selects the GPIOB, Only GPIO_PIN_SOURCE0 and GPIO_PIN_SOURCE1 are valid + *\*\param pin_source : + *\*\ - GPIO_PIN_SOURCE0 + *\*\ - GPIO_PIN_SOURCE1 + *\*\ - GPIO_PIN_SOURCE2 + *\*\ - GPIO_PIN_SOURCE3 + *\*\ - GPIO_PIN_SOURCE4 + *\*\ - GPIO_PIN_SOURCE5 + *\*\ - GPIO_PIN_SOURCE6 + *\*\ - GPIO_PIN_SOURCE7 + *\*\ - GPIO_PIN_SOURCE8 + *\*\ - GPIO_PIN_SOURCE9 + *\*\ - GPIO_PIN_SOURCE10 + *\*\ - GPIO_PIN_SOURCE11 + *\*\ - GPIO_PIN_SOURCE12 + *\*\ - GPIO_PIN_SOURCE13 + *\*\ - GPIO_PIN_SOURCE14 + *\*\ - GPIO_PIN_SOURCE15 + *\*\param alternate_function : + *\*\ - GPIO_AF0_SWDIO SWDIO Alternate Function mapping + *\*\ - GPIO_AF0_SWCLK SWCLK Alternate Function mapping + *\*\ - GPIO_AF0_TIM1 TIM1 Alternate Function mapping + *\*\ - GPIO_AF0_TIM3 TIM3 Alternate Function mapping + *\*\ - GPIO_AF0_SPI SPI Alternate Function mapping + *\*\ + *\*\ - GPIO_AF1_UART2 UART2 Alternate Function mapping + *\*\ - GPIO_AF1_TIM3 TIM3 Alternate Function mapping + *\*\ + *\*\ - GPIO_AF2_UART1 UART1 Alternate Function mapping + *\*\ - GPIO_AF2_TIM1 TIM1 Alternate Function mapping + *\*\ - GPIO_AF2_TIM3 TIM3 Alternate Function mapping + *\*\ + *\*\ - GPIO_AF3_TIM1 TIM1 Alternate Function mapping + *\*\ - GPIO_AF3_COMP COMP Alternate Function mapping + *\*\ - GPIO_AF3_EVENTOUT EVENTOUT Alternate Function mapping + *\*\ + *\*\ - GPIO_AF4_TIM1 TIM1 Alternate Function mapping + *\*\ + *\*\ - GPIO_AF5_UART1 UART1 Alternate Function mapping + *\*\ - GPIO_AF5_TIM1 TIM1 Alternate Function mapping + *\*\ - GPIO_AF5_SPI SPI Alternate Function mapping + *\*\ + *\*\ - GPIO_AF6_SPI SPI Alternate Function mapping + *\*\ - GPIO_AF6_I2C I2C Alternate Function mapping + *\*\ - GPIO_AF6_TIM3 TIM3 Alternate Function mapping + *\*\ - GPIO_AF6_UART2 UART2 Alternate Function mapping + *\*\ - GPIO_AF6_MCO MCO Alternate Function mapping + *\*\ + *\*\ - GPIO_AF7_BEEPER BEEPER Alternate Function mapping + *\*\return none + */ +void GPIO_Pin_Remap_Set(uint8_t port_source, uint8_t pin_source, uint32_t alternate_function) +{ + uint32_t position = 0x00, temp_value = 0x00; + GPIO_Module *GPIOx; + + /* Get Peripheral index */ + GPIOx = GPIO_GET_PERIPH(port_source); + + if(pin_source & (uint8_t)AF_SELECTION_MASK) + { + position = (uint32_t)(pin_source & (uint8_t)AF_WRITE_POSITION_MASK); + + /* Read GPIO_AFH register */ + temp_value = GPIOx->AFH; + + /* Reset corresponding bits */ + temp_value &= ~(GPIO_AF_MASK << (position * MULTIPLIER_FACTOR_4)); + + /* Set corresponding bits */ + temp_value |= (alternate_function << (position * MULTIPLIER_FACTOR_4)); + + /* Write to the GPIO_AFH register */ + GPIOx->AFH = temp_value; + } + else + { + position = (uint32_t)(pin_source & (uint8_t)AF_WRITE_POSITION_MASK); + + /* Read GPIO_AFL register */ + temp_value = GPIOx->AFL; + + /* Reset corresponding bits */ + temp_value &= ~(GPIO_AF_MASK << (position * MULTIPLIER_FACTOR_4)); + + /* Set corresponding bits */ + temp_value |= (alternate_function << (position * MULTIPLIER_FACTOR_4)); + + /* Write to the GPIO_AFL register */ + GPIOx->AFL = temp_value; + } +} + +/** + *\*\name AFIO_ADC_External_Trigger_Set + *\*\fun Selects the GPIO pin used as EXTI Line. + *\*\param line_source: + *\*\ - AFIO_ADC_TRIG_PA0 + *\*\ - AFIO_ADC_TRIG_PA1 + *\*\ - AFIO_ADC_TRIG_PA2 + *\*\ - AFIO_ADC_TRIG_PA3 + *\*\ - AFIO_ADC_TRIG_PA4 + *\*\ - AFIO_ADC_TRIG_PA5 + *\*\ - AFIO_ADC_TRIG_PA6 + *\*\ - AFIO_ADC_TRIG_PA7 + *\*\ - AFIO_ADC_TRIG_PA8 + *\*\ - AFIO_ADC_TRIG_PA9 + *\*\ - AFIO_ADC_TRIG_PA10 + *\*\ - AFIO_ADC_TRIG_PA11 + *\*\ - AFIO_ADC_TRIG_PA12 + *\*\ - AFIO_ADC_TRIG_PA13 + *\*\ - AFIO_ADC_TRIG_PA14 + *\*\ - AFIO_ADC_TRIG_PA15 + *\*\ - AFIO_ADC_TRIG_PB0 + *\*\ - AFIO_ADC_TRIG_PB1 + *\*\ Note: Each EXTI line corresponds to a separate pin in this series. + *\*\return none + */ +void AFIO_ADC_External_Trigger_Set(uint8_t ADC_trigger) +{ + uint32_t temp_value = 0x00; + + temp_value = AFIO->CFG; + temp_value &= ~AFIO_CFG_MASK; + temp_value |= ADC_trigger; + AFIO->CFG = temp_value; +} + + +/** + *\*\name AFIO_SPI_NSS_Mode_Set. + *\*\fun Selects NSS mode of SPI when idle. + *\*\param SPI_nss_mode : + *\*\ specifies the SPI_NSS mode to be configured. + *\*\ - AFIO_SPI_NSS_HIGH_IMPEDANCE + *\*\ - AFIO_SPI_NSS_High_LEVEL + *\*\return none + */ +void AFIO_SPI_NSS_Mode_Set(uint32_t SPI_NSS_mode) +{ + uint32_t temp_value = 0x00U; + + temp_value = (AFIO->CFG & (~AFIO_CFG_SPI_NSS)); + + if(SPI_NSS_mode != AFIO_SPI_NSS_HIGH_IMPEDANCE) + { + temp_value |= AFIO_SPI_NSS; + } + else + { + temp_value &= ~AFIO_SPI_NSS; + } + + AFIO->CFG = temp_value; +} + + +/** + *\*\name AFIO_TIM3CH2_Remap. + *\*\fun Controls the TIM3_CH2 internal mapping. + *\*\param TIM3CH2_remap : + *\*\ specifies the TIM3_CH2 internal mapping. + *\*\ - TIM3CH2_TO_PORT + *\*\ - TIM3CH2_TO_LSI + *\*\return none + */ +void AFIO_TIM3CH2_Remap(uint32_t TIM3CH2_remap) +{ + uint32_t temp_value = 0x00U; + + temp_value = (AFIO->CFG & (~AFIO_CFG_TIM3CH2_MAP)); + + if(TIM3CH2_remap != TIM3CH2_TO_PORT) + { + temp_value |= AFIO_TIM3CH2_MAP; + } + else + { + temp_value &= ~AFIO_TIM3CH2_MAP; + } + + AFIO->CFG = temp_value; +} + + + + + diff --git a/firmware/n32g003_std_periph_driver/src/n32g003_i2c.c b/firmware/n32g003_std_periph_driver/src/n32g003_i2c.c new file mode 100644 index 0000000..c45499e --- /dev/null +++ b/firmware/n32g003_std_periph_driver/src/n32g003_i2c.c @@ -0,0 +1,1398 @@ +/** +* Copyright (c) 2022, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** +*\*\file n32g003_i2c.c +*\*\author Nations +*\*\version v1.0.0 +*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. +**/ +#include "n32g003_rcc.h" +#include "n32g003_i2c.h" + + +/** +*\*\name I2C_Reset. +*\*\fun Reset the I2Cx registers. +*\*\param I2Cx : +*\*\ - I2C +*\*\return none +**/ +void I2C_Reset(I2C_Module* I2Cx) +{ + /* I2C Reset */ + RCC_Peripheral_Reset(RCC_RST_I2CRST); +} + +/** +*\*\name I2C_Initializes. +*\*\fun Initializes the I2Cx peripheral according to the specified +*\*\ parameters in the I2C_InitParam +*\*\param I2Cx : +*\*\ - I2C +*\*\param I2C_InitParam : +*\*\ - ClkSpeed(common speed:100000(100KHz) - 400000(400KHz) - 1000000(1MHz)): +*\*\ - between 1 to 1000000 +*\*\ - DutyCycle(If the ClkSpeed does not exceed 100KHz,duty is fixed at 1:1, +*\*\ otherwise it can be configured as 2:1 or 16:9): +*\*\ - I2C_SMDUTYCYCLE_1 +*\*\ - I2C_FMDUTYCYCLE_16_9 +*\*\ - I2C_FMDUTYCYCLE_2 +*\*\ - OwnAddr1: +*\*\ - between 0 to 0x3FF +*\*\ - AckEnable: +*\*\ - I2C_ACKEN +*\*\ - I2C_ACKDIS +*\*\ - AddrMode: +*\*\ - I2C_ADDR_MODE_7BIT +*\*\ - I2C_ADDR_MODE_10BIT +*\*\return none +**/ +void I2C_Initializes(I2C_Module* I2Cx, I2C_InitType* I2C_InitParam) +{ + I2C_Clock_Speed_Config(I2Cx, I2C_InitParam->ClkSpeed, I2C_InitParam->DutyCycle); + I2C_Acknowledgement_Config(I2Cx, I2C_InitParam->AckEnable); + I2C_Addressing_Mode_Config(I2Cx, I2C_InitParam->AddrMode); + I2C_Own_Addr1_Config(I2Cx, I2C_InitParam->OwnAddr1); +} + +/** +*\*\name I2C_Clock_Speed_Config. +*\*\fun Initializes the clock speed. +*\*\param I2Cx : +*\*\ - I2C +*\*\param clk_speed +*\*\ - between 1 to 1000000 +*\*\param duty_cycle: +*\*\ - I2C_SMDUTYCYCLE_1 +*\*\ - I2C_FMDUTYCYCLE_16_9 +*\*\ - I2C_FMDUTYCYCLE_2 +*\*\return none +**/ +void I2C_Clock_Speed_Config(I2C_Module* I2Cx, uint32_t clk_speed, uint16_t duty_cycle) +{ + uint16_t temp_value = 0, freq_value = 0, speed_value = 0x04; + uint32_t pclk_value = 8000000, trise_value = 0; + RCC_ClocksType rcc_clocks; + + /* Get pclk frequency value */ + RCC_Clocks_Frequencies_Value_Get( &rcc_clocks ); + /* Get the I2Cx CTRL2 value */ + temp_value = I2Cx->CTRL2; + /* Clear frequency FREQ[5:0] bits */ + temp_value &= I2C_CLKFREQ_RESET; + /* Get APB1 frequency value */ + pclk_value = rcc_clocks.PclkFreq; + /* Set frequency bits depending on pclk_value value */ + freq_value = ( uint16_t )( pclk_value / 1000000 ); + if (freq_value > APB_FREQ_MAX_VALUE) + { + freq_value = APB_FREQ_MAX_VALUE; + } + temp_value |= freq_value; + /* Write to I2Cx CTRL2 */ + I2Cx->CTRL2 = temp_value; + + /** I2Cx CLKCTRL config **/ + /* Disable the selected I2C peripheral to configure TMRISE */ + I2Cx->CTRL1 &= I2C_EN_RESET; + /* Get the I2Cx TMRISE value */ + trise_value = I2Cx->TMRISE; + /* Clear TMRISE[5:0] bits */ + trise_value &= (~I2C_TMRISE_MASK); + /* Reset temp_value */ + /* Clear CLKCTRL:FSMODE, DUTY and CLKCTRL[11:0] bits */ + temp_value = 0; + + /*If the ClkSpeed does not exceed 100KHz, mode(FSMODE[bit15]) is standard, duty is fixed at 1:1,ignore + DUTY[bit14] */ + /* Configure speed in standard mode */ + + if ( clk_speed <= CLK_SPEED_100K ) + { + /* Standard mode speed calculate */ + speed_value = ( uint16_t )( pclk_value / (clk_speed * 2)); + /* Test if CLKCTRL value is under 0x4*/ + + if ( speed_value < SM_CLKCTRL_LOW_LIMIT ) + { + /* Set minimum allowed value */ + speed_value = SM_CLKCTRL_LOW_LIMIT; + } + + /* Set speed value for standard mode */ + temp_value |= speed_value; + + /* Set Maximum Rise Time for standard mode */ + trise_value |= ((freq_value + 1) & I2C_TMRISE_MASK); + } + /*If ClkSpeed exceeds 100KHz, mode(FSMODE[bit15]) is fast, duty(DUTY[bit14]) can be + configured as 2:1 or 16:9 */ + /* Configure speed in fast mode */ + else if ( clk_speed <= CLK_SPEED_1M ) + { + if ( duty_cycle != I2C_FMDUTYCYCLE_16_9 ) + { + /* Fast mode speed calculate: Tlow/Thigh = 2 */ + speed_value = ( uint16_t )( pclk_value / ( clk_speed * 3 ) ); + } + else /*I2C_InitStruct->DutyCycle == DutyCycle_16_9*/ + { + /* Fast mode speed calculate: Tlow/Thigh = 16/9 */ + speed_value = ( uint16_t )( pclk_value / ( clk_speed * 25 ) ); + /* Set DUTY bit */ + speed_value |= I2C_FMDUTYCYCLE_16_9; + } + + /* Test if CLKCTRL value is under 0x1*/ + if (( speed_value & I2C_CLKCTRL_SET ) < FM_CLKCTRL_LOW_LIMIT ) + { + /* Set minimum allowed value */ + speed_value |= ( uint16_t )FM_CLKCTRL_LOW_LIMIT; + } + + /* Set speed value and set F/S bit for fast mode */ + temp_value |= ( uint16_t )( speed_value | I2C_FSMODE_SET ); + + /* Set Maximum Rise Time for fast mode */ + /* if APB frequency is 48MHz,period = 1/48*1000ns,so trise_value = period/TRISE+1=48*TRISE/1000+1,See the manual for details*/ + if(clk_speed <= CLK_SPEED_400K) /* 100KHz~400KHz */ + { + trise_value |= (((uint16_t)(((freq_value * (uint16_t)FM_TRISE_400K) / (uint16_t)1000) + (uint16_t)1)) & I2C_TMRISE_MASK); + } + else /* 400KHz~1MHz */ + { + trise_value |= (((uint16_t)(((freq_value * (uint16_t)FM_TRISE_1M) / (uint16_t)1000) + (uint16_t)1)) & I2C_TMRISE_MASK); + } + } + /* Write to I2Cx TMRISE */ + I2Cx->TMRISE = trise_value; + + /* Write to I2Cx CLKCTRL */ + I2Cx->CLKCTRL = temp_value; + + /* Enable the selected I2C peripheral */ + I2Cx->CTRL1 |= I2C_EN_SET; + +} + +/** +*\*\name I2C_Acknowledgement_Config. +*\*\fun Initializes the acknowledgement. +*\*\param I2Cx : +*\*\ - I2C +*\*\param ack +*\*\ - I2C_ACKEN +*\*\ - I2C_ACKDIS +*\*\return none +**/ +void I2C_Acknowledgement_Config(I2C_Module* I2Cx, uint16_t ack) +{ + uint16_t temp_value = 0; + + /* Get the I2Cx CTRL1 value */ + temp_value = I2Cx->CTRL1; + /* Clear ACKEN bits */ + temp_value &= I2C_ACKEN_CLR_MASK; + /* Set ACKEN bits according to ack value */ + temp_value |= (uint16_t)((uint32_t)ack); + /* Set I2Cx CTRL1 */ + I2Cx->CTRL1 = temp_value; +} + +/** +*\*\name I2C_Addressing_Mode_Config. +*\*\fun Initializes addressing mode. +*\*\param I2Cx : +*\*\ - I2C +*\*\param mode +*\*\ - I2C_ADDR_MODE_7BIT +*\*\ - I2C_ADDR_MODE_10BIT +*\*\return none +**/ +void I2C_Addressing_Mode_Config(I2C_Module* I2Cx, uint16_t mode) +{ + uint16_t temp_value = 0; + + /* Get the I2Cx OADDR1 value */ + temp_value = I2Cx->OADDR1; + /* Clear ADDRMODE bits */ + temp_value &= I2C_ADDRMODE_CLR_MASK; + /* Set ACKEN bits according to mode value */ + temp_value |= mode; + /* Set I2Cx OADDR1 */ + I2Cx->OADDR1 = temp_value; +} + +/** +*\*\name I2C_Own_Addr1_Config. +*\*\fun Initializes the own address. +*\*\param I2Cx : +*\*\ - I2C +*\*\param addr1 between 0 to 0x3FF +*\*\return none +**/ +void I2C_Own_Addr1_Config(I2C_Module* I2Cx, uint16_t addr1) +{ + uint16_t temp_value = 0; + + /* Get the I2Cx OADDR1 value */ + temp_value = I2Cx->OADDR1; + /* Clear ADDRMODE bits */ + temp_value &= I2C_OADDR_CLR_MASK; + /* Set ACKEN bits according to mode value */ + temp_value |= addr1; + /* Set I2Cx OADDR1 */ + I2Cx->OADDR1 = temp_value; + +} + +/** +*\*\name I2C_Initializes_Structure. +*\*\fun Fills each I2C_InitStruct member with its default value. +*\*\param I2C_InitStruct : +*\*\ - ClkSpeed +*\*\ - BusMode -none +*\*\ - DutyCycle +*\*\ - OwnAddr1 +*\*\ - AckEnable +*\*\ - AddrMode +*\*\return none +**/ +void I2C_Initializes_Structure(I2C_InitType* I2C_InitStruct) +{ + /*---------------- Reset I2C init structure parameters values ----------------*/ + /* initialize the ClkSpeed member */ + I2C_InitStruct->ClkSpeed = 5000; + /* Initialize the DutyCycle member */ + I2C_InitStruct->DutyCycle = I2C_FMDUTYCYCLE_2; + /* Initialize the OwnAddr1 member */ + I2C_InitStruct->OwnAddr1 = 0; + /* Initialize the AckEnable member */ + I2C_InitStruct->AckEnable = I2C_ACKDIS; + /* Initialize the AddrMode member */ + I2C_InitStruct->AddrMode = I2C_ADDR_MODE_7BIT; +} + +/** +*\*\name I2C_ON. +*\*\fun I2Cx turn ON. +*\*\param I2Cx : +*\*\ - I2C +*\*\return none +**/ +void I2C_ON(I2C_Module* I2Cx) +{ + /* Enable the selected I2C peripheral */ + I2Cx->CTRL1 |= I2C_EN_SET; +} + +/** +*\*\name I2C_OFF. +*\*\fun I2Cx turn OFF. +*\*\param I2Cx : +*\*\ - I2C +*\*\return none +**/ +void I2C_OFF(I2C_Module* I2Cx) +{ + /* Disable the selected I2C peripheral */ + I2Cx->CTRL1 &= I2C_EN_RESET; +} + +/** +*\*\name I2C_Generate_Start_Enable. +*\*\fun Enable Generate a START condition. +*\*\param I2Cx : +*\*\ - I2C +*\*\return none +**/ +void I2C_Generate_Start_Enable(I2C_Module* I2Cx) +{ + /* Generate a START condition */ + I2Cx->CTRL1 |= I2C_START_SET; +} + +/** +*\*\name I2C_Generate_Start_Disable. +*\*\fun Disable the START condition generation. +*\*\param I2Cx : +*\*\ - I2C +*\*\return none +**/ +void I2C_Generate_Start_Disable(I2C_Module* I2Cx) +{ + /* Disable the START condition generation */ + I2Cx->CTRL1 &= I2C_START_RESET; +} + +/** +*\*\name I2C_Generate_Stop_Enable. +*\*\fun Enable Generate a STOP condition. +*\*\param I2Cx : +*\*\ - I2C +*\*\return none +**/ +void I2C_Generate_Stop_Enable(I2C_Module* I2Cx) +{ + /* Generate a STOP condition */ + I2Cx->CTRL1 |= I2C_STOP_SET; +} + +/** +*\*\name I2C_Generate_Stop_Disable. +*\*\fun Disable the STOP condition generation. +*\*\param I2Cx : +*\*\ - I2C +*\*\return none +**/ +void I2C_Generate_Stop_Disable(I2C_Module* I2Cx) +{ + /* Disable the STOP condition generation */ + I2Cx->CTRL1 &= I2C_STOP_RESET; +} + +/** +*\*\name I2C_Acknowledg_Enable. +*\*\fun Enable the acknowledgement. +*\*\param I2Cx : +*\*\ - I2C +*\*\return none +**/ +void I2C_Acknowledg_Enable(I2C_Module* I2Cx) +{ + /* Enable the acknowledgement */ + I2Cx->CTRL1 |= I2C_ACK_SET; +} + +/** +*\*\name I2C_Acknowledg_Disable. +*\*\fun Disable the acknowledgement. +*\*\param I2Cx : +*\*\ - I2C +*\*\return none +**/ +void I2C_Acknowledg_Disable(I2C_Module* I2Cx) +{ + /* Disable the acknowledgement */ + I2Cx->CTRL1 &= I2C_ACK_RESET; +} + +/** +*\*\name I2C_Own_Addr2_Set. +*\*\fun Set the specified I2C own address2. +*\*\param I2Cx : +*\*\ - I2C +*\*\param address +*\*\ - 7bit I2C own address2 +*\*\return none +**/ +void I2C_Own_Addr2_Set(I2C_Module* I2Cx, uint8_t address) +{ + uint16_t temp_value = 0; + + /* Get the old register value */ + temp_value = I2Cx->OADDR2; + + /* Reset I2Cx Own address2 bit [7:1] */ + temp_value &= I2C_ADDR2_RESET; + + /* Set I2Cx Own address2 */ + temp_value |= (uint16_t)((uint16_t)address & I2C_ADDR2_SET); + + /* Store the new register value */ + I2Cx->OADDR2 = temp_value; +} + +/** +*\*\name I2C_Dual_Addr_Enable. +*\*\fun Enables the specified I2C dual addressing mode. +*\*\param I2Cx : +*\*\ - I2C +*\*\return none +**/ +void I2C_Dual_Addr_Enable(I2C_Module* I2Cx) +{ + /* Enable dual addressing mode */ + I2Cx->OADDR2 |= I2C_DUALEN_SET; +} + +/** +*\*\name I2C_Dual_Addr_Disable. +*\*\fun Disable the specified I2C dual addressing mode. +*\*\param I2Cx : +*\*\ - I2C +*\*\return none +**/ +void I2C_Dual_Addr_Disable(I2C_Module* I2Cx) +{ + /* Disable dual addressing mode */ + I2Cx->OADDR2 &= I2C_DUALEN_RESET; +} + +/** +*\*\name I2C_General_Call_Enable. +*\*\fun Enables the specified I2C general call feature. +*\*\param I2Cx : +*\*\ - I2C +*\*\return none +**/ +void I2C_General_Call_Enable(I2C_Module* I2Cx) +{ + /* Enable generall call */ + I2Cx->CTRL1 |= I2C_GCEN_SET; +} + +/** +*\*\name I2C_General_Call_Disable. +*\*\fun Disable the specified I2C general call feature. +*\*\param I2Cx : +*\*\ - I2C +*\*\return none +**/ +void I2C_General_Call_Disable(I2C_Module* I2Cx) +{ + /* Disable generall call */ + I2Cx->CTRL1 &= I2C_GCEN_RESET; +} + +/** +*\*\name I2C_Interrupts_Enable. +*\*\fun Enables the specified I2C interrupts. +*\*\param I2Cx : +*\*\ - I2C +*\*\param I2C_IT : +*\*\ - I2C_INT_BUF Buffer interrupt mask +*\*\ - I2C_INT_EVENT Event interrupt mask +*\*\ - I2C_INT_ERR Error interrupt mask +*\*\return none +**/ +void I2C_Interrupts_Enable(I2C_Module* I2Cx, uint16_t I2C_IT) +{ + /* Enable the selected I2C interrupts */ + I2Cx->CTRL2 |= I2C_IT; +} + +/** +*\*\name I2C_Interrupts_Disable. +*\*\fun Disables the specified I2C interrupts. +*\*\param I2Cx : +*\*\ - I2C +*\*\param I2C_IT : +*\*\ - I2C_INT_BUF Buffer interrupt mask +*\*\ - I2C_INT_EVENT Event interrupt mask +*\*\ - I2C_INT_ERR Error interrupt mask +*\*\return none +**/ +void I2C_Interrupts_Disable(I2C_Module* I2Cx, uint16_t I2C_IT) +{ + /* Disable the selected I2C interrupts */ + I2Cx->CTRL2 &= (uint16_t)~I2C_IT; +} + +/** +*\*\name I2C_Data_Send. +*\*\fun Sends a data byte through the I2Cx peripheral. +*\*\param I2Cx : +*\*\ - I2C +*\*\param data +*\*\return none +**/ +void I2C_Data_Send(I2C_Module* I2Cx, uint8_t data) +{ + /* Write in the DAT register the data to be sent */ + I2Cx->DAT = data; +} + +/** +*\*\name I2C_Data_Recv. +*\*\fun Returns the most recent received data by the I2Cx peripheral. +*\*\param I2Cx : +*\*\ - I2C +*\*\return The value of the received data +**/ +uint8_t I2C_Data_Recv(I2C_Module* I2Cx) +{ + /* Return the data in the DAT register */ + return (uint8_t)I2Cx->DAT; +} + +/** +*\*\name I2C_7bit_Addr_Send. +*\*\fun Transmits the address byte to select the slave device. +*\*\param I2Cx : +*\*\ - I2C +*\*\param address +*\*\param mode : +*\*\ - I2C_DIRECTION_SEND Transmitter mode +*\*\ - I2C_DIRECTION_RECV Receiver mode +*\*\return none +**/ +void I2C_7bit_Addr_Send(I2C_Module* I2Cx, uint8_t address, uint8_t mode) +{ + /* Test on the direction to set/reset the read/write bit */ + if (mode == I2C_DIRECTION_RECV) + { + /* Set the address bit0 for read */ + address |= I2C_ADDR0_SET; + } + else + { + /* Reset the address bit0 for write */ + address &= I2C_ADDR0_RESET; + } + /* Send the address */ + I2Cx->DAT = address; +} + +/** +*\*\name I2C_Register_Value_Get. +*\*\fun Reads the specified I2C register and returns its value. +*\*\param I2Cx : +*\*\ - I2C +*\*\param I2C_Register : +*\*\ - I2C_REG_CTRL1 CTRL1 register +*\*\ - I2C_REG_CTRL2 CTRL2 register +*\*\ - I2C_REG_OADDR1 OADDR1 register +*\*\ - I2C_REG_OADDR2 OADDR2 register +*\*\ - I2C_REG_DAT DAT register +*\*\ - I2C_REG_STS1 STS1 register +*\*\ - I2C_REG_STS2 STS2 register +*\*\ - I2C_REG_CLKCTRL CLKCTRL register +*\*\ - I2C_REG_TMRISE TMRISE register +*\*\ - I2C_REG_GFLTRCTRL GFLTRCTRL register +*\*\ - I2C_REG_BYTENUM BYTENUM register +*\*\return none +**/ +uint16_t I2C_Register_Value_Get(I2C_Module* I2Cx, uint8_t I2C_Register) +{ + __IO uint32_t temp_value = 0; + temp_value = (uint32_t)I2Cx; + temp_value += I2C_Register; + + /* Return the selected register value */ + return (*(__IO uint16_t*)temp_value); +} + +/** +*\*\name I2C_Software_Reset_Enable. +*\*\fun Enables the specified I2C software reset. +*\*\param I2Cx : +*\*\ - I2C +*\*\return none +**/ +void I2C_Software_Reset_Enable(I2C_Module* I2Cx) +{ + /* Peripheral under reset */ + I2Cx->CTRL1 |= I2C_SWRESET_SET; +} + +/** +*\*\name I2C_Software_Reset_Disable. +*\*\fun Disables the specified I2C software reset. +*\*\param I2Cx : +*\*\ - I2C +*\*\return none +**/ +void I2C_Software_Reset_Disable(I2C_Module* I2Cx) +{ + /* Peripheral not under reset */ + I2Cx->CTRL1 &= I2C_SWRESET_RESET; +} + +/** +*\*\name I2C_NACK_Position_Set. +*\*\fun Selects the specified I2C NACK position in master receiver mode. +*\*\ This function is useful in I2C Master Receiver mode when the number +*\*\ of data to be received is equal to 2. In this case, this function +*\*\ should be called (with parameter I2C_NACK_POS_NEXT) before data +*\*\ reception starts,as described in the 2-byte reception procedure +*\*\ recommended in Reference Manual in Section: Master receiver. +*\*\param I2Cx : +*\*\ - I2C +*\*\param position : +*\*\ - I2C_NACK_POS_NEXT Indicates that the next byte will be the last received byte. +*\*\ - I2C_NACK_POS_CURRENT Indicates that current byte is the last received byte. +*\*\note This function configures the same bit (POS) as I2C_PEC_Position_Set() +*\*\ but is intended to be used in I2C mode while I2C_PEC_Position_Set() +*\*\ is intended to used in SMBUS mode. +*\*\return none +**/ +void I2C_NACK_Position_Set(I2C_Module* I2Cx, uint16_t position) +{ + if (position == I2C_NACK_POS_NEXT) + { + /* Next byte in shift register is the last received byte */ + I2Cx->CTRL1 |= I2C_NACK_POS_NEXT; + } + else + { + /* Current byte in shift register is the last received byte */ + I2Cx->CTRL1 &= I2C_NACK_POS_CURRENT; + } +} + +/** +*\*\name I2C_PEC_Send_Enable. +*\*\fun Enables the specified I2C PEC transfer. +*\*\param I2Cx : +*\*\ - I2C +*\*\return none +**/ +void I2C_PEC_Send_Enable(I2C_Module* I2Cx) +{ + /* Enable the selected I2C PEC transmission */ + I2Cx->CTRL1 |= I2C_PEC_SET; +} + +/** +*\*\name I2C_PEC_Send_Disable. +*\*\fun Disables the specified I2C PEC transfer. +*\*\param I2Cx : +*\*\ - I2C +*\*\return none +**/ +void I2C_PEC_Send_Disable(I2C_Module* I2Cx) +{ + /* Disable the selected I2C PEC transmission */ + I2Cx->CTRL1 &= I2C_PEC_RESET; +} + +/** +*\*\name I2C_NACK_Position_Set. +*\*\fun Selects the specified I2C PEC position. +*\*\param I2Cx : +*\*\ - I2C +*\*\param position : +*\*\ - I2C_PEC_POS_NEXT Indicates that the next byte is PEC +*\*\ - I2C_PEC_POS_CURRENT Indicates that current byte is PEC +*\*\note This function configures the same bit (POS) as I2C_NACK_Position_Set() +*\*\ but is intended to be used in SMBUS mode while I2C_NACK_Position_Set() +*\*\ is intended to used in I2C mode. +*\*\return none +**/ +void I2C_PEC_Position_Set(I2C_Module* I2Cx, uint16_t position) +{ + if (position == I2C_PEC_POS_NEXT) + { + /* Next byte in shift register is PEC */ + I2Cx->CTRL1 |= I2C_PEC_POS_NEXT; + } + else + { + /* Current byte in shift register is PEC */ + I2Cx->CTRL1 &= I2C_PEC_POS_CURRENT; + } +} + +/** +*\*\name I2C_PEC_Compute_Enable. +*\*\fun Enables PEC value compute. +*\*\param I2Cx : +*\*\ - I2C +*\*\return none +**/ +void I2C_PEC_Compute_Enable(I2C_Module* I2Cx) +{ + /* Enable the selected I2C PEC calculation */ + I2Cx->CTRL1 |= I2C_PECEN_SET; +} + +/** +*\*\name I2C_PEC_Compute_Disable. +*\*\fun Disables PEC value compute. +*\*\param I2Cx : +*\*\ - I2C +*\*\return none +**/ +void I2C_PEC_Compute_Disable(I2C_Module* I2Cx) +{ + /* Disable the selected I2C PEC calculation */ + I2Cx->CTRL1 &= I2C_PECEN_RESET; +} + +/** +*\*\name I2C_PEC_Get. +*\*\fun Get the PEC value for the specified I2C. +*\*\param I2Cx : +*\*\ - I2C +*\*\return The PEC value +**/ +uint8_t I2C_PEC_Get(I2C_Module* I2Cx) +{ + /* Return the selected I2C PEC value */ + return ((I2Cx->STS2) >> 8); +} + +/** +*\*\name I2C_Extend_Clock_Enable. +*\*\fun Enables the specified I2C clock extending. +*\*\param I2Cx : +*\*\ - I2C +*\*\return none +**/ +void I2C_Extend_Clock_Enable(I2C_Module* I2Cx) +{ + /* Enable the selected I2C Clock extending */ + I2Cx->CTRL1 &= I2C_NOEXTEND_RESET; +} + +/** +*\*\name I2C_Extend_Clock_Disable. +*\*\fun Disables the specified I2C clock extending. +*\*\param I2Cx : +*\*\ - I2C +*\*\return none +**/ +void I2C_Extend_Clock_Disable(I2C_Module* I2Cx) +{ + /* Disable the selected I2C Clock extending */ + I2Cx->CTRL1 |= I2C_NOEXTEND_SET; +} + +/** +*\*\name I2C_Fast_Mode_Duty_Cycle_Set. +*\*\fun Set the specified I2C fast mode duty cycle. +*\*\param I2Cx : +*\*\ - I2C +*\*\param duty_cycle : +*\*\ - I2C_FMDUTYCYCLE_2 I2C fast mode Tlow/Thigh = 2 +*\*\ - I2C_FMDUTYCYCLE_16_9 I2C fast mode Tlow/Thigh = 16/9 +*\*\return none +**/ +void I2C_Fast_Mode_Duty_Cycle_Set(I2C_Module* I2Cx, uint16_t duty_cycle) +{ + if (duty_cycle == I2C_FMDUTYCYCLE_16_9) + { + /* I2C fast mode Tlow/Thigh=16/9 */ + I2Cx->CLKCTRL |= I2C_FMDUTYCYCLE_16_9; + } + else + { + /* I2C fast mode Tlow/Thigh=2 */ + I2Cx->CLKCTRL &= I2C_FMDUTYCYCLE_2; + } +} + +/** +*\*\name I2C_Digital_Filter_Width_Set. +*\*\fun SDA digital filter width selection. +*\*\param I2Cx : +*\*\ - I2C +*\*\param width : +*\*\ - 0x00 ~ 0x0F The numbers of pclk cycles(width is 0x00: Disable the digital filter). +*\*\return none +**/ +void I2C_SDA_Digital_Filter_Width_Set(I2C_Module* I2Cx, uint8_t width) +{ + uint16_t temp_value = 0; + + temp_value = I2Cx->GFLTRCTRL; + /* Clear SDADFW[3:0] bits */ + temp_value &= I2C_SDADFW_MASK; + /* Set SDADFW[3:0] bits according to width value */ + temp_value |= (uint16_t)width ; + /* Store the new value */ + I2Cx->GFLTRCTRL = temp_value; + +} + +/** +*\*\name I2C_SCL_Digital_Filter_Width_Set. +*\*\fun SCL digital filter width selection. +*\*\param I2Cx : +*\*\ - I2C +*\*\param width : +*\*\ - 0x00 Disable the digital filter. +*\*\ - 0x01 ~ 0x0F The numbers of pclk cycles. +*\*\return none +**/ +void I2C_SCL_Digital_Filter_Width_Set(I2C_Module* I2Cx, uint8_t width) +{ + uint16_t temp_value = 0; + + temp_value = I2Cx->GFLTRCTRL; + /* Clear SCLDFW[3:0] bits */ + temp_value &= I2C_SCLDFW_MASK; + /* Set SCLDFW[3:0] bits according to width value */ + temp_value |= ((uint16_t)width << 4); + /* Store the new value */ + I2Cx->GFLTRCTRL = temp_value; + +} + +/** +*\*\name I2C_SDA_Analog_Filter_Width_Set. +*\*\fun SDA analog filter width selection. +*\*\param I2Cx : +*\*\ - I2C +*\*\param width : +*\*\ - I2C_ANALOG_FILTER_WIDTH_5NS +*\*\ - I2C_ANALOG_FILTER_WIDTH_15NS +*\*\ - I2C_ANALOG_FILTER_WIDTH_25NS +*\*\ - I2C_ANALOG_FILTER_WIDTH_35NS +*\*\return none +**/ +void I2C_SDA_Analog_Filter_Width_Set(I2C_Module* I2Cx, uint16_t width) +{ + uint16_t temp_value = 0; + + temp_value = I2Cx->GFLTRCTRL; + /* Clear SDAAFW[1:0] bits */ + temp_value &= I2C_SDAAFW_MASK; + /* Set SDAAFW[1:0] bits according to width value */ + temp_value |= width; + /* Store the new value */ + I2Cx->GFLTRCTRL = temp_value; + +} + +/** +*\*\name I2C_SDA_Analog_Filter_Enable. +*\*\fun Enables the SDA analog filter. +*\*\param I2Cx : +*\*\ - I2C +*\*\return none +**/ +void I2C_SDA_Analog_Filter_Enable(I2C_Module* I2Cx) +{ + /* Enable the SDA analog filter */ + I2Cx->GFLTRCTRL &= I2C_SCLAFENN_RESET; +} + +/** +*\*\name I2C_SDA_Analog_Filter_Disable. +*\*\fun Disables the SDA analog filter. +*\*\param I2Cx : +*\*\ - I2C +*\*\return none +**/ +void I2C_SDA_Analog_Filter_Disable(I2C_Module* I2Cx) +{ + /* Disable the SDA analog filter */ + I2Cx->GFLTRCTRL |= I2C_SCLAFENN_SET; +} + +/** +*\*\name I2C_SCL_Analog_Filter_Width_Set. +*\*\fun SCL analog filter width selection. +*\*\param I2Cx : +*\*\ - I2C +*\*\param width : +*\*\ - I2C_ANALOG_FILTER_WIDTH_5NS +*\*\ - I2C_ANALOG_FILTER_WIDTH_15NS +*\*\ - I2C_ANALOG_FILTER_WIDTH_25NS +*\*\ - I2C_ANALOG_FILTER_WIDTH_35NS +*\*\return none +**/ +void I2C_SCL_Analog_Filter_Width_Set(I2C_Module* I2Cx, uint16_t width) +{ + uint16_t temp_value = 0; + + temp_value = I2Cx->GFLTRCTRL; + /* Clear SCLAFW[1:0] bits */ + temp_value &= I2C_SCLAFW_MASK; + /* Set SCLAFW[1:0] bits according to width value */ + temp_value |= (width << 3); + /* Store the new value */ + I2Cx->GFLTRCTRL = temp_value; + +} + +/** +*\*\name I2C_SCL_Analog_Filter_Enable. +*\*\fun Enables the SCL analog filter. +*\*\param I2Cx : +*\*\ - I2C +*\*\return none +**/ +void I2C_SCL_Analog_Filter_Enable(I2C_Module* I2Cx) +{ + /* Enable the SCL analog filter */ + I2Cx->GFLTRCTRL &= I2C_SCLAFENN_RESET; +} + +/** +*\*\name I2C_SCL_Analog_Filter_Disable. +*\*\fun Disables the SCL analog filter. +*\*\param I2Cx : +*\*\ - I2C +*\*\return none +**/ + +void I2C_SCL_Analog_Filter_Disable(I2C_Module* I2Cx) +{ + /* Disable the SCL analog filter */ + I2Cx->GFLTRCTRL |= I2C_SCLAFENN_SET; +} + +/** +*\*\brief I2C State Monitoring Functions +*\*\ This I2C driver provides three different ways for I2C state monitoring +*\*\ depending on the application requirements and constraints: +*\*\ +*\*\ +*\*\ 1) Basic state monitoring: +*\*\ Using I2C_Event_Check() function: +*\*\ It compares the status registers (STS1 and STS2) content to a given event +*\*\ (can be the combination of one or more flags). +*\*\ It returns SUCCESS if the current status includes the given flags +*\*\ and returns ERROR if one or more flags are missing in the current status. +*\*\ - When to use: +*\*\ - This function is suitable for most applications as well as for startup +*\*\ activity since the events are fully described in the product reference manual. +*\*\ - It is also suitable for users who need to define their own events. +*\*\ - Limitations: +*\*\ - If an error occurs (ie. error flags are set besides to the monitored flags), +*\*\ the I2C_Event_Check() function may return SUCCESS despite the communication +*\*\ hold or corrupted real state. +*\*\ In this case, it is advised to use error interrupts to monitor the error +*\*\ events and handle them in the interrupt IRQ handler. +*\*\ +*\*\note +*\*\ For error management, it is advised to use the following functions: +*\*\ - I2C_ConfigInt() to configure and enable the error interrupts (I2C_INT_ERR). +*\*\ - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs. +*\*\ Where x is the peripheral instance (I2C, I2C2 ...) +*\*\ - I2C_Flag_Status_Get() or I2C_GetIntStatus() to be called into I2Cx_ER_IRQHandler() +*\*\ in order to determine which error occured. +*\*\ - I2C_Flag_Status_Clear() or I2C_ClrIntPendingBit() and/or I2C_EnableSoftwareReset() +*\*\ and/or I2C_Generate_Stop_Enable() in order to clear the error flag and source, +*\*\ and return to correct communication status. +*\*\ +*\*\ +*\*\ 2) Advanced state monitoring: +*\*\ Using the function I2C_Last_Event_Get() which returns the image of both status +*\*\ registers in a single word (uint32_t) (Status Register 2 value is shifted left +*\*\ by 16 bits and concatenated to Status Register 1). +*\*\ - When to use: +*\*\ - This function is suitable for the same applications above but it allows to +*\*\ overcome the mentioned limitation of I2C_Flag_Status_Get() function. +*\*\ The returned value could be compared to events already defined in the +*\*\ library (n32g003_i2c.h) or to custom values defined by user. +*\*\ - This function is suitable when multiple flags are monitored at the same time. +*\*\ - At the opposite of I2C_Event_Check() function, this function allows user to +*\*\ choose when an event is accepted (when all events flags are set and no +*\*\ other flags are set or just when the needed flags are set like +*\*\ I2C_Event_Check() function). +*\*\ - Limitations: +*\*\ - User may need to define his own events. +*\*\ - Same remark concerning the error management is applicable for this +*\*\ function if user decides to check only regular communication flags (and +*\*\ ignores error flags). +*\*\ +*\*\ +*\*\ 3) Flag-based state monitoring: +*\*\ Using the function I2C_Flag_Status_Get() which simply returns the status of +*\*\ one single flag (ie. I2C_FLAG_RXDATNE ...). +*\*\ - When to use: +*\*\ - This function could be used for specific applications or in debug phase. +*\*\ - It is suitable when only one flag checking is needed (most I2C events +*\*\ are monitored through multiple flags). +*\*\ - Limitations: +*\*\ - When calling this function, the Status register is accessed. Some flags are +*\*\ cleared when the status register is accessed. So checking the status +*\*\ of one Flag, may clear other ones. +*\*\ - Function may need to be called twice or more in order to monitor one +*\*\ single event. +*\*\ +*\*\ For detailed description of Events, please refer to section I2C_Events in +*\*\ n32g003_i2c.h file. +*\*\ +**/ + + +/** +*\*\name I2C_Event_Check. +*\*\fun Checks whether the last I2Cx Event is equal to the one passed as parameter. +*\*\param I2Cx : +*\*\ - I2C +*\*\param I2C_event : +*\*\ - I2C_EVT_SLAVE_SEND_ADDR_MATCHED EV1 +*\*\ - I2C_EVT_SLAVE_RECV_ADDR_MATCHED EV1 +*\*\ - I2C_EVT_SLAVE_SEND_ADDR2_MATCHED EV1 +*\*\ - I2C_EVT_SLAVE_RECV_ADDR2_MATCHED EV1 +*\*\ - I2C_EVT_SLAVE_GCALLADDR_MATCHED EV1 +*\*\ - I2C_EVT_SLAVE_DATA_RECVD EV2 +*\*\ - (I2C_EVT_SLAVE_DATA_RECVD | I2C_FLAG_DUALFLAG) EV2 +*\*\ - (I2C_EVT_SLAVE_DATA_RECVD | I2C_FLAG_GCALLADDR) EV2 +*\*\ - I2C_EVT_SLAVE_DATA_SENDED EV3 +*\*\ - (I2C_EVT_SLAVE_DATA_SENDED | I2C_FLAG_DUALFLAG) EV3 +*\*\ - (I2C_EVT_SLAVE_DATA_SENDED | I2C_FLAG_GCALLADDR)EV3 +*\*\ - I2C_EVT_SLAVE_ACK_MISS EV3_2 +*\*\ - I2C_EVT_SLAVE_STOP_RECVD EV4 +*\*\ - I2C_EVT_MASTER_MODE_FLAG EV5 +*\*\ - I2C_EVT_MASTER_TXMODE_FLAG EV6 +*\*\ - I2C_EVT_MASTER_RXMODE_FLAG EV6 +*\*\ - I2C_EVT_MASTER_DATA_RECVD_FLAG EV7 +*\*\ - I2C_EVT_MASTER_DATA_SENDING EV8 +*\*\ - I2C_EVT_MASTER_DATA_SENDED EV8_2 +*\*\ - I2C_EVT_MASTER_MODE_ADDRESS10_FLAG EV9 +*\*\note For detailed description of Events, please refer to section +*\*\ I2C_Events in n32g003_i2c.h file. +*\*\return SUCCESS or ERROR +**/ + +ErrorStatus I2C_Event_Check( I2C_Module* I2Cx, uint32_t I2C_event ) +{ + uint32_t le_value = 0; + uint32_t flag1 = 0, flag2 = 0; + + /* Read the I2Cx status register */ + flag1 = I2Cx->STS1; + flag2 = I2Cx->STS2; + flag2 = flag2 << RCC_FLAG_STS2_OFFSET; + + /* Get the last event value from I2C status register */ + le_value = (flag1 | flag2) & I2C_FLAG_Mask; + + /* Check whether the last event contains the I2C_event */ + if ((le_value & I2C_event) == I2C_event) + { + /* Return SUCCESS: last event is equal to I2C_event */ + return SUCCESS; + } + else + { + /* Return ERROR: last event is different from I2C_event */ + return ERROR; + } +} + +/** +*\*\name I2C_Last_Event_Get. +*\*\fun Returns the last I2Cx Event. +*\*\param I2Cx : +*\*\ - I2C +*\*\note For detailed description of Events, please refer to section +*\*\ I2C_Events in n32g003_i2c.h file. +*\*\return The last event +**/ + +uint32_t I2C_Last_Event_Get( I2C_Module* I2Cx ) +{ + uint32_t flag1 = 0, flag2 = 0; + + /* Read the I2Cx status register */ + flag1 = I2Cx->STS1; + flag2 = I2Cx->STS2; + flag2 = flag2 << RCC_FLAG_STS2_OFFSET; + + /* Return the last event value from I2C status register */ + return (flag1 | flag2) & I2C_FLAG_Mask; +} + +/** +*\*\name I2C_Flag_Status_Get. +*\*\fun Checks whether the specified I2C flag is set or not. +*\*\param I2Cx : +*\*\ - I2C +*\*\param I2C_flag : +*\*\ - I2C_FLAG_DUALFLAG Dual flag (Slave mode) +*\*\ - I2C_FLAG_GCALLADDR General call header flag (Slave mode) +*\*\ - I2C_FLAG_TRF Transmitter/Receiver flag +*\*\ - I2C_FLAG_BUSY Bus busy flag +*\*\ - I2C_FLAG_MSMODE Master/Slave flag +*\*\ - I2C_FLAG_PECERR PEC error in reception flag +*\*\ - I2C_FLAG_OVERRUN Overrun/Underrun flag (Slave mode) +*\*\ - I2C_FLAG_ACKFAIL Acknowledge failure flag +*\*\ - I2C_FLAG_ARLOST Arbitration lost flag (Master mode) +*\*\ - I2C_FLAG_BUSERR Bus error flag +*\*\ - I2C_FLAG_TXDATE Data register empty flag (Transmitter) +*\*\ - I2C_FLAG_RXDATNE Data register not empty (Receiver) flag +*\*\ - I2C_FLAG_STOPF Stop detection flag (Slave mode) +*\*\ - I2C_FLAG_ADDR10F 10-bit header sent flag (Master mode) +*\*\ - I2C_FLAG_BYTEF Byte transfer finished flag +*\*\ - I2C_FLAG_ADDRF Address sent flag (Master mode) +*\*\ Address matched flag (Slave mode) +*\*\ - I2C_FLAG_STARTBF Start bit flag (Master mode) +*\*\return SET or RESET +**/ + +FlagStatus I2C_Flag_Status_Get( I2C_Module* I2Cx, uint32_t I2C_flag ) +{ + __IO uint32_t temp_value0 = 0, temp_value1 = 0; + + /* Get the I2Cx peripheral base address */ + temp_value0 = (uint32_t)I2Cx; + + /* Read flag register index */ + temp_value1 = I2C_flag >> RCC_FLAG_GET_OFFSET; + + /* Get bit[23:0] of the flag */ + I2C_flag &= I2C_FLAG_Mask; + + if (temp_value1 == 0) + { + /* Flag in I2Cx STS2 Register */ + I2C_flag = (uint32_t)(I2C_flag >> RCC_FLAG_STS2_OFFSET); + /* Get the I2Cx STS2 register address */ + temp_value0 += 0x18; + } + else + { + /* Get the I2Cx STS1 register address */ + temp_value0 += 0x14; + } + + if (((*(__IO uint32_t*)temp_value0) & I2C_flag) == (uint32_t)RESET) + { + /* I2C_flag is reset */ + return RESET; + } + else + { + /* I2C_flag is set */ + return SET; + } +} + +/** +*\*\name I2C_Flag_Status_Clear. +*\*\fun Clears the I2Cx's flags. +*\*\param I2Cx : +*\*\ - I2C +*\*\param I2C_flag : +*\*\ - I2C_FLAG_PECERR PEC error in reception flag +*\*\ - I2C_FLAG_OVERRUN Overrun/Underrun flag (Slave mode) +*\*\ - I2C_FLAG_ACKFAIL Acknowledge failure flag +*\*\ - I2C_FLAG_ARLOST Arbitration lost flag (Master mode) +*\*\ - I2C_FLAG_BUSERR Bus error flag +*\*\note - STOPF (STOP detection) is cleared by software sequence: a read operation +*\*\ to I2C_STS1 register (I2C_Flag_Get()) followed by a write operation +*\*\ to I2C_CTRL1 register (I2C_ON() to re-enable the I2C peripheral). +*\*\ - ADD10 (10-bit header sent) is cleared by software sequence: a read +*\*\ operation to I2C_STS1 (I2C_Flag_Get()) followed by writing the +*\*\ second byte of the address in DAT register. +*\*\ - BTF (Byte Transfer Finished) is cleared by software sequence: a read +*\*\ operation to I2C_STS1 register (I2C_Flag_Get()) followed by a +*\*\ read/write to I2C_DAT register (I2C_Data_Send()). +*\*\ - ADDR (Address sent) is cleared by software sequence: a read operation to +*\*\ I2C_STS1 register (I2C_Flag_Get()) followed by a read operation to +*\*\ I2C_STS2 register ((void)(I2Cx->STS2)). +*\*\ - SB (Start Bit) is cleared software sequence: a read operation to I2C_STS1 +*\*\ register (I2C_Flag_Get()) followed by a write operation to I2C_DAT +*\*\ register (I2C_Data_Send()). +*\*\return none +**/ + + +void I2C_Flag_Status_Clear( I2C_Module* I2Cx, uint32_t I2C_flag ) +{ + uint32_t temp_value = 0; + + /* Get the I2C flag position */ + temp_value = I2C_flag & I2C_FLAG_Mask; + /* Clear the selected I2C flag */ + I2Cx->STS1 = (uint16_t)~temp_value; +} + +/** +*\*\name I2C_Interrupt_Status_Get. +*\*\fun Checks whether the specified I2C interrupt has occurred or not. +*\*\param I2Cx : +*\*\ - I2C +*\*\param Interrupt : +*\*\ - I2C_INT_PECERR PEC error in reception flag +*\*\ - I2C_INT_OVERRUN Overrun/Underrun flag (Slave mode) +*\*\ - I2C_INT_ACKFAIL Acknowledge failure flag +*\*\ - I2C_INT_ARLOST Arbitration lost flag (Master mode) +*\*\ - I2C_INT_BUSERR Bus error flag +*\*\ - I2C_INT_TXDATE Data register empty flag (Transmitter) +*\*\ - I2C_INT_RXDATNE Data register not empty (Receiver) flag +*\*\ - I2C_INT_STOPF Stop detection flag (Slave mode) +*\*\ - I2C_INT_ADDR10F 10-bit header sent flag (Master mode) +*\*\ - I2C_INT_BYTEF Byte transfer finished flag +*\*\ - I2C_INT_ADDRF Address sent flag (Master mode) +*\*\ Address matched flag (Slave mode) +*\*\ - I2C_INT_STARTBF Start bit flag (Master mode) +*\*\return SET or RESET +**/ + +ITStatus I2C_Interrupt_Status_Get( I2C_Module* I2Cx, uint32_t Interrupt ) +{ + uint32_t temp_value = 0; + + /* Check if the interrupt source is enabled or not */ + temp_value = (uint32_t)(((Interrupt & I2C_INTEN_MASK) >> 16) & (I2Cx->CTRL2)); + + /* Get bit[23:0] of the flag */ + Interrupt &= I2C_FLAG_Mask; + + /* Check the status of the specified I2C flag */ + if (((I2Cx->STS1 & Interrupt) != (uint32_t)RESET) && temp_value) + { + /* Interrupt is set */ + return SET; + } + else + { + /* Interrupt is reset */ + return RESET; + } +} + + +/** +*\*\name I2C_Interrupt_Statu_Clear. +*\*\fun Clears the I2Cx's interrupt statu bits. +*\*\param I2Cx : +*\*\ - I2C +*\*\param Interrupt : +*\*\ - I2C_INT_PECERR PEC error in reception flag +*\*\ - I2C_INT_OVERRUN Overrun/Underrun flag (Slave mode) +*\*\ - I2C_INT_ACKFAIL Acknowledge failure flag +*\*\ - I2C_INT_ARLOST Arbitration lost flag (Master mode) +*\*\ - I2C_INT_BUSERR Bus error flag +*\*\note - STOPF (STOP detection) is cleared by software sequence: a read operation +*\*\ to I2C_STS1 register (I2C_Flag_Get()) followed by a write operation +*\*\ to I2C_CTRL1 register (I2C_ON() to re-enable the I2C peripheral). +*\*\ - ADD10 (10-bit header sent) is cleared by software sequence: a read +*\*\ operation to I2C_STS1 (I2C_Flag_Get()) followed by writing the +*\*\ second byte of the address in DAT register. +*\*\ - BTF (Byte Transfer Finished) is cleared by software sequence: a read +*\*\ operation to I2C_STS1 register (I2C_Flag_Get()) followed by a +*\*\ read/write to I2C_DAT register (I2C_Data_Send()). +*\*\ - ADDR (Address sent) is cleared by software sequence: a read operation to +*\*\ I2C_STS1 register (I2C_Flag_Get()) followed by a read operation to +*\*\ I2C_STS2 register ((void)(I2Cx->STS2)). +*\*\ - SB (Start Bit) is cleared software sequence: a read operation to I2C_STS1 +*\*\ register (I2C_Flag_Get()) followed by a write operation to I2C_DAT +*\*\ register (I2C_Data_Send()). +*\*\return none +**/ +void I2C_Interrupt_Statu_Clear(I2C_Module* I2Cx, uint32_t Interrupt) +{ + uint32_t temp_value = 0; + + /* Get the I2C flag position */ + temp_value = Interrupt & I2C_FLAG_Mask; + /* Clear the selected I2C flag */ + I2Cx->STS1 = (uint16_t)~temp_value; +} + +/** +*\*\name I2C_ByteNum_Enable. +*\*\fun Enables the specified I2C peripheral ByteNum function. +*\*\param I2Cx : +*\*\ - I2C +*\*\return none +**/ + +void I2C_ByteNum_enable(I2C_Module* I2Cx) +{ + /* Enable the selected I2C peripheral ByteNum function*/ + I2Cx->BYTENUM |= I2C_BYTENUMEN_SET; +} + +/** +*\*\name I2C_ByteNum_Disable. +*\*\fun disables the specified I2C peripheral ByteNum function. +*\*\param I2Cx : +*\*\ - I2C +*\*\return none +**/ + +void I2C_ByteNum_Disable(I2C_Module* I2Cx) +{ + /* Disable the selected I2C peripheral ByteNum function*/ + I2Cx->BYTENUM &= I2C_BYTENUMEN_RESET; +} + + +/** +*\*\name I2C_Master_Received_DataBytesNum_Set. +*\*\fun Set the number of data bytes that will be received by master receiver of I2C peripheral. +*\*\param I2Cx : +*\*\ - I2C +*\*\param Number_Of_bytes(the number of data bytes) : +*\*\ - 0x0~0x3FFF +*\*\return none +**/ + + +void I2C_Master_Received_DataBytesNum_Set(I2C_Module* I2Cx, uint16_t Number_Of_bytes) +{ + uint16_t temp_value = 0; + + temp_value = I2Cx->BYTENUM; + /* Clear BYTENUM[13:0] bits */ + temp_value &= I2C_BYTENUM_MASK; + /* Set BYTENUM[13:0] bits according to Number_Of_bytes value */ + temp_value |= Number_Of_bytes; + /* Store the new value */ + I2Cx->BYTENUM = temp_value; +} + +/** +*\*\name I2C_ByteNum_Last_StartStop_Set. +*\*\fun Configure the last status after master have finished sending the required data bytes. +*\*\param I2Cx : +*\*\ - I2C +*\*\param LastStatus : +*\*\ - I2C_BYTENUM_LAST_STOP +*\*\ - I2C_BYTENUM_LAST_START +*\*\return none +**/ + +void I2C_ByteNum_Last_StartStop_Set(I2C_Module* I2Cx, uint16_t LastStatus) +{ + if (LastStatus == I2C_BYTENUM_LAST_START) + { + /* Next byte in shift register is PEC */ + I2Cx->BYTENUM |= I2C_BYTENUM_LAST_START; + } + else + { + /* Current byte in shift register is PEC */ + I2Cx->BYTENUM &= I2C_BYTENUM_LAST_STOP; + } +} + + + + diff --git a/firmware/n32g003_std_periph_driver/src/n32g003_iwdg.c b/firmware/n32g003_std_periph_driver/src/n32g003_iwdg.c new file mode 100644 index 0000000..134dd18 --- /dev/null +++ b/firmware/n32g003_std_periph_driver/src/n32g003_iwdg.c @@ -0,0 +1,195 @@ +/** +* Copyright (c) 2022, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** +*\*\file n32g003_iwdg.c +*\*\author Nations +*\*\version v1.0.0 +*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. +**/ +#include "n32g003_iwdg.h" + + +/** +*\*\name IWDG_Write_Protection_Disable. +*\*\fun Disable write protection to IWDG_PREDIV and IWDG_RELV registers. +*\*\param none +*\*\return none +**/ +void IWDG_Write_Protection_Disable(void) +{ + IWDG->KEY = IWDG_WRITE_CONFIG_ENABLE; +} + +/** +*\*\name IWDG_Write_Protection_Enable. +*\*\fun Enable write protection to IWDG_PREDIV and IWDG_RELV registers. +*\*\param none +*\*\return none +**/ +void IWDG_Write_Protection_Enable(void) +{ + IWDG->KEY = IWDG_WRITE_CONFIG_DISABLE; +} + + +/** +*\*\name IWDG_Prescaler_Division_Set. +*\*\fun IWDG_Prescaler specifies the IWDG prescaler value. +*\*\param IWDG_prescaler : +*\*\ - IWDG_CONFIG_PRESCALER_DIV4 +*\*\ - IWDG_CONFIG_PRESCALER_DIV8 +*\*\ - IWDG_CONFIG_PRESCALER_DIV16 +*\*\ - IWDG_CONFIG_PRESCALER_DIV32 +*\*\ - IWDG_CONFIG_PRESCALER_DIV64 +*\*\ - IWDG_CONFIG_PRESCALER_DIV128 +*\*\ - IWDG_CONFIG_PRESCALER_DIV256 +*\*\return none +**/ +void IWDG_Prescaler_Division_Set(IWDG_CONFIG_PRESCALER IWDG_prescaler) +{ + IWDG->PREDIV = IWDG_prescaler; +} + + +/** +*\*\name IWDG_Counter_Reload. +*\*\fun Sets IWDG reload value. +*\*\param reload_value : +*\*\ -0x000 ~ 0xFFF +*\*\return none +**/ +void IWDG_Counter_Reload(uint16_t reload_value) +{ + IWDG->RELV= reload_value; +} + + +/** +*\*\name IWDG_Key_Reload. +*\*\fun Reload IWDG counter with value defined in IWDG_RELV register. +*\*\return none +**/ +void IWDG_Key_Reload(void) +{ + IWDG->KEY = KEY_RELOAD_COUNTER; +} + + +/** +*\*\name IWDG_Enable. +*\*\fun Start watch dog counter. +*\*\return none +**/ +void IWDG_Enable(void) +{ + IWDG->KEY = KEY_ENABLE_COUNTER; +} + +/** +*\*\name IWDG_Freeze_Enable. +*\*\fun Freeze and stop IWDG while IWDG is running. +*\*\return none +**/ +ErrorStatus IWDG_Freeze_Enable(void) +{ + IWDG->FREEZE = IWDG_FREEZE; + if((IWDG->FREEZE & IWDG_FREEZE_FLAG) != (uint32_t)RESET) + { + return SUCCESS; + } + else + { + return ERROR; + } + +} + + +/** +*\*\name IWDG_Restore_From_Freeze. +*\*\fun Restore from run time feeze. +*\*\return none +**/ +ErrorStatus IWDG_Restore_From_Freeze(void) +{ + IWDG->FREEZE = IWDG_UNFREEZE; + if((IWDG->FREEZE & IWDG_FREEZE_FLAG) == (uint32_t)RESET) + { + return SUCCESS; + } + else + { + return ERROR; + } +} + + +/** +*\*\name IWDG_Status_Get. +*\*\fun Checks whether the specified IWDG flag is set or not. +*\*\param IWDG_flag : +*\*\ - IWDG_PVU_FLAG +*\*\ - IWDG_CRVU_FLAG +*\*\return FlagStatus : +*\*\ - RESET +*\*\ - SET +**/ +FlagStatus IWDG_Status_Get(IWDG_STATUS_FLAG IWDG_flag) +{ + if((IWDG->STS & IWDG_flag) != (uint32_t)RESET) + { + return SET; + } + else + { + return RESET; + } +} + + + diff --git a/firmware/n32g003_std_periph_driver/src/n32g003_pwr.c b/firmware/n32g003_std_periph_driver/src/n32g003_pwr.c new file mode 100644 index 0000000..8f3600c --- /dev/null +++ b/firmware/n32g003_std_periph_driver/src/n32g003_pwr.c @@ -0,0 +1,575 @@ +/** +* Copyright (c) 2022, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** +*\*\file n32g003_pwr.c +*\*\author Nations +*\*\version v1.0.0 +*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32g003_pwr.h" +#include "n32g003_rcc.h" + +/** PWR Private Defines **/ + +/** PWR Driving Functions Declaration **/ + +/** +*\*\name PWR_Reset. +*\*\fun Deinitializes the PWR peripheral registers to their default reset values. +*\*\param none +*\*\return none +**/ +void PWR_Reset(void) +{ + RCC_Peripheral_Reset(RCC_RST_PWRRST); +} + +/** +*\*\name PWR_PVD_Enable. +*\*\fun Enables the Power Voltage Detector(PVD). +*\*\param none +*\*\return none +**/ +void PWR_PVD_Enable(void) +{ + PWR->CTRL |= PWR_PVD_ENABLE; +} + +/** +*\*\name PWR_PVD_Disable. +*\*\fun Disables the Power Voltage Detector(PVD). +*\*\param none +*\*\return none +**/ +void PWR_PVD_Disable(void) +{ + PWR->CTRL &= (~PWR_PVD_ENABLE); +} + +/** +*\*\name PWR_PVD_Interrupt_Enable. +*\*\fun Enables the Power Voltage Detector Interrupt. +*\*\param none +*\*\return none +**/ +void PWR_PVD_Interrupt_Enable(void) +{ + PWR->CTRL |= PWR_PVD_INT_ENABLE; +} + +/** +*\*\name PWR_PVD_Interrupt_Disable. +*\*\fun Disables the Power Voltage Detector Interrupt. +*\*\param none +*\*\return none +**/ +void PWR_PVD_Interrupt_Disable(void) +{ + PWR->CTRL &= (~PWR_PVD_INT_ENABLE); +} + +/** +*\*\name PWR_PVD_Filter_Enable. +*\*\fun Enables the Power Voltage Detector Filter. +*\*\param none +*\*\return none +**/ +void PWR_PVD_Filter_Enable(void) +{ + PWR->CTRL |= PWR_PVD_FIL_ENABLE; +} + +/** +*\*\name PWR_PVD_Filter_Disable. +*\*\fun Disables the Power Voltage Detector Filter. +*\*\param none +*\*\return none +**/ +void PWR_PVD_Filter_Disable(void) +{ + PWR->CTRL &= (~PWR_PVD_FIL_ENABLE); +} + +/** +*\*\name PWR_PVD_Level_Config. +*\*\fun Configures the voltage threshold detected by the Power Voltage Detector(PVD). +*\*\param level : +*\*\ - PWR_PVD_LEVEL_1V8 +*\*\ - PWR_PVD_LEVEL_2V0 +*\*\ - PWR_PVD_LEVEL_2V2 +*\*\ - PWR_PVD_LEVEL_2V4 +*\*\ - PWR_PVD_LEVEL_2V6 +*\*\ - PWR_PVD_LEVEL_2V8 +*\*\ - PWR_PVD_LEVEL_3V0 +*\*\ - PWR_PVD_LEVEL_3V2 +*\*\ - PWR_PVD_LEVEL_3V4 +*\*\ - PWR_PVD_LEVEL_3V6 +*\*\ - PWR_PVD_LEVEL_3V8 +*\*\ - PWR_PVD_LEVEL_4V0 +*\*\ - PWR_PVD_LEVEL_4V2 +*\*\ - PWR_PVD_LEVEL_4V4 +*\*\ - PWR_PVD_LEVEL_4V6 +*\*\ - PWR_PVD_LEVEL_4V8 +*\*\return none +**/ +void PWR_PVD_Level_Config(uint32_t level) +{ + uint32_t temp_value = 0; + temp_value = PWR->CTRL; + /* Clear PLS[8:5] bits bit */ + temp_value &= PWR_CTRL_PLS_MASK; + /* Set PLS[8:5] bits according to level value */ + temp_value |= level; + /* Store the new value */ + PWR->CTRL = temp_value; +} + +/** +*\*\name PWR_LVR_Enable. +*\*\fun Enables the Low Voltage Detector(LVR). +*\*\param none +*\*\return none +**/ +void PWR_LVR_Enable(void) +{ + PWR->CTRL2 |= PWR_LVR_ENABLE; +} + +/** +*\*\name PWR_LVR_Disable. +*\*\fun Disables the Low Voltage Detector(LVR). +*\*\param none +*\*\return none +**/ +void PWR_LVR_Disable(void) +{ + PWR->CTRL2 &= (~PWR_LVR_ENABLE); +} + +/** +*\*\name PWR_LVR_Reset_Enable. +*\*\fun Enables the Low Voltage Detector reset. +*\*\param none +*\*\return none +**/ +void PWR_LVR_Reset_Enable(void) +{ + PWR->CTRL2 |= PWR_LVR_RST_ENABLE; +} + +/** +*\*\name PWR_LVR_Reset_Disable. +*\*\fun Disables the Low Voltage Detector reset. +*\*\param none +*\*\return none +**/ +void PWR_LVR_Reset_Disable(void) +{ + PWR->CTRL2 &= (~PWR_LVR_RST_ENABLE); +} + +/** +*\*\name PWR_LVR_Filter_Enable. +*\*\fun Enables the Low Voltage Detector Filter. +*\*\param none +*\*\return none +**/ +void PWR_LVR_Filter_Enable(void) +{ + PWR->CTRL2 |= PWR_LVR_FIL_ENABLE; +} + +/** +*\*\name PWR_LVR_Filter_Disable. +*\*\fun Disables the Low Voltage Detector Filter. +*\*\param none +*\*\return none +**/ +void PWR_LVR_Filter_Disable(void) +{ + PWR->CTRL2 &= (~PWR_LVR_FIL_ENABLE); +} + +/** +*\*\name PWR_LVR_Level_Config. +*\*\fun Configures the voltage threshold detected by the Low Voltage Detector(LVR). +*\*\param level : +*\*\ - PWR_LVR_LEVEL_1V8 +*\*\ - PWR_LVR_LEVEL_2V0 +*\*\ - PWR_LVR_LEVEL_2V2 +*\*\ - PWR_LVR_LEVEL_2V4 +*\*\ - PWR_LVR_LEVEL_2V6 +*\*\ - PWR_LVR_LEVEL_2V8 +*\*\ - PWR_LVR_LEVEL_3V0 +*\*\ - PWR_LVR_LEVEL_3V2 +*\*\ - PWR_LVR_LEVEL_3V4 +*\*\ - PWR_LVR_LEVEL_3V6 +*\*\ - PWR_LVR_LEVEL_3V8 +*\*\ - PWR_LVR_LEVEL_4V0 +*\*\ - PWR_LVR_LEVEL_4V2 +*\*\ - PWR_LVR_LEVEL_4V4 +*\*\ - PWR_LVR_LEVEL_4V6 +*\*\ - PWR_LVR_LEVEL_4V8 +*\*\return none +**/ +void PWR_LVR_Level_Config(uint32_t level) +{ + uint32_t temp_value = 0; + temp_value = PWR->CTRL2; + /* Clear LVRS[14:11] bits*/ + temp_value &= PWR_CTRL2_LVRLS_MASK; + /* Set LVRS[14:11] bits according to level value */ + temp_value |= level; + /* Store the new value */ + PWR->CTRL2 = temp_value; +} + +/** +*\*\name PWR_Wakeup_Pin_Enable. +*\*\fun Enables the Wakeup Pin functionality. +*\*\param pin : +*\*\ - WAKEUP_PIN1 PA1 +*\*\ - WAKEUP_PIN2 PA2 +*\*\param polarity : +*\*\ - PWR_PIN_RISING +*\*\ - PWR_PIN_FALLING +*\*\return none +**/ +void PWR_Wakeup_Pin_Enable(WAKEUP_PINX pin, uint32_t polarity) +{ + uint32_t temp_value = 0; + temp_value = PWR->CTRLSTS; + /* Clear WKUPPOL bit*/ + temp_value &= (PWR_CTRLSTS_WKUPPOL_MASK); + /* Clear WKUP1EN or WKUP0EN bit*/ + temp_value &= (~(uint32_t)pin); + /* Set wakeup polarity value */ + temp_value |= (polarity << PWR_BIT_SHIFT_10); + /* Set wakeup value */ + temp_value |= pin; + /* Store the new value */ + PWR->CTRLSTS = temp_value; +} + +/** +*\*\name PWR_Wakeup_Pin_Disable. +*\*\fun Disables the WakeUp Pin functionality. +*\*\param pin : +*\*\ - WAKEUP_PIN1 PA1 +*\*\ - WAKEUP_PIN2 PA2 +*\*\return none +**/ +void PWR_Wakeup_Pin_Disable(WAKEUP_PINX pin) +{ + uint32_t temp_value = 0; + temp_value = PWR->CTRLSTS; + /* Set wakeup value */ + temp_value &= (~(uint32_t)pin); + /* Store the new value */ + PWR->CTRLSTS = temp_value; +} + +/** +*\*\name PWR_STOP_Mode_Enter. +*\*\fun Enters STOP mode. +*\*\param enter_mode : +*\*\ - PWR_STOP_ENTRY_WFI (enter STOP mode with WFI instruction) +*\*\ - PWR_STOP_ENTRY_WFE (enter STOP mode with WFE instruction) +*\*\return none +**/ +void PWR_STOP_Mode_Enter(uint8_t enter_mode) +{ + uint32_t temp_value = 0; + temp_value = PWR->CTRL; + /* Clear PDSTP bits */ + temp_value &= PWR_CTRL_PDSTP_MASK; + /* Store the new value */ + PWR->CTRL = temp_value; + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP; + + /* Select STOP mode entry */ + if (enter_mode == PWR_STOP_ENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP); +} + +/** +*\*\name PWR_PD_Mode_Enter. +*\*\fun Enters PD mode. +*\*\param enter_mode : +*\*\ - PWR_PD_ENTRY_WFI (enter PD mode with WFI instruction) +*\*\ - PWR_PD_ENTRY_WFE (enter PD mode with WFE instruction) +*\*\return none +**/ +void PWR_PD_Mode_Enter(uint8_t enter_mode) +{ + /* Clear Wake-up flag */ + PWR->CTRL |= PWR_CLEAR_WKUPF; + /* Clear PDS bits */ + PWR->CTRL &= PWR_CTRL_PDSTP_MASK; + /* Select PD mode */ + PWR->CTRL |= PWR_PD_MODE; + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SCB->SCR |= SCB_SCR_SLEEPDEEP; + /* This option is used to ensure that store operations are completed */ +#if defined(__CC_ARM) + __force_stores(); +#endif + /* Select PD mode entry */ + if (enter_mode == PWR_PD_ENTRY_WFI) + { + /* Request Wait For Interrupt */ + __WFI(); + } + else + { + /* Request Wait For Event */ + __SEV(); + __WFE(); + __WFE(); + } +} + +/** +*\*\name PWR_HSI_40M_Trim_Select. +*\*\fun PWR control selects the HSI frequency as 40M. +*\*\param none +*\*\return none +**/ +void PWR_HSI_40M_Trim_Select(void) +{ + /* Enable the HSI is controlled by the PWR */ + PWR->CTRL3 |= PWR_CONTROL_HSI; + /* Select the HSI frequency as 40M */ + PWR->CTRL3 |= PWR_HSI_TRIM_40M; +} + +/** +*\*\name PWR_PDR_Trigger_Level_Config. +*\*\fun VDDD PDR trigger level configuration in STOP mode. +*\*\param level : +*\*\ - PWR_PDR_LEVEL_0V8 +*\*\ - PWR_PDR_LEVEL_1V0 +*\*\ - PWR_PDR_LEVEL_1V2 +*\*\return none +**/ +void PWR_PDR_Trigger_Level_Config(uint32_t level) +{ + uint32_t temp_value = 0; + /* Enable PDR select signal is controlled by the PWR */ + PWR->CTRL3 |= PWR_CONTROL_PDR_SEL; + + temp_value = PWR->CTRL; + /* Clear PDRS[10:9] bits*/ + temp_value &= PWR_CTRL_PDRS_MASK; + /* Set PDRS[10:9] bits according to level value */ + temp_value |= level; + /* Store the new value */ + PWR->CTRL = temp_value; +} + +/** +*\*\name PWR_VDDD_Output_Config. +*\*\fun After the chip enters STOP mode, configure the output voltage of VDDD. +*\*\param voltage_output : +*\*\ - PWR_VDDD_OUTPUT_1V5 +*\*\ - PWR_VDDD_OUTPUT_1V0 +*\*\ - PWR_VDDD_OUTPUT_1V2 +*\*\return none +*\*\note When configuring PWR_VDDD_OUTPUT_1V0 and PWR_VDDD_OUTPUT_1V2, you must +*\*\ first call the PWR_PDR_Trigger_Level_Config() function with the +*\*\ parameter PWR_PDR_LEVEL_0V8. +**/ +void PWR_VDDD_Output_Config(uint32_t voltage_output) +{ + uint32_t temp_value = 0; + /* Enable VDDD output voltage select */ + PWR->CTRL6 |= PWR_VDDD_OUTPUT_SEL_EN; + + temp_value = PWR->CTRL5; + /* Clear STPMRSEL[3:2] bits*/ + temp_value &= PWR_CTRL5_STPMRSEL_MASK; + /* Set STPMRSEL[3:2] bits according to level value */ + temp_value |= voltage_output; + /* Store the new value */ + PWR->CTRL5 = temp_value; +} + + +/** +*\*\name PWR_CTRL2_write_Protection_Enable. +*\*\fun Enable the PWR_CTRL2 registers write protection. +*\*\param none +*\*\return none +**/ +void PWR_CTRL2_write_Protection_Enable(void) +{ + /* Enable the write protection for PWR_CTRL2 registers */ + PWR->CTRL2 = PWR_CTRL2_KEYS; +} + +/** +*\*\name PWR_CTRL4_write_Protection_Enable. +*\*\fun Enable the PWR_CTRL4 registers write protection. +*\*\param none +*\*\return none +**/ +void PWR_CTRL4_write_Protection_Enable(void) +{ + /* Enable the write protection for PWR_CTRL4 registers */ + PWR->CTRL4 = PWR_CTRL4_KEYS; +} + +/** +*\*\name PWR_Flag_Status_Get. +*\*\fun Checks whether the specified PWR flag is set or not. +*\*\param flag : +*\*\ - PWR_WKUP_FLAG +*\*\ - PWR_DBGPD_FLAG +*\*\ - PWR_PVD_OUTPUT_FLAG +*\*\ - PWR_LVR_OUTPUT_FLAG +*\*\return SET or RESET. +**/ +FlagStatus PWR_Flag_Status_Get(uint32_t flag) +{ + if (flag == PWR_LVR_OUTPUT_FLAG) + { + /* Check the status of the PWR flag */ + if ((PWR->CTRL2 & flag) == (uint32_t)RESET) + { + /* PWR Flag is reset */ + return RESET; + } + else + { + /* PWR Flag is set */ + return SET; + } + } + else + { + /* Check the status of the PWR flag */ + if ((PWR->CTRLSTS & flag) == (uint32_t)RESET) + { + /* PWR Flag is reset */ + return RESET; + } + else + { + /* PWR Flag is set */ + return SET; + } + } +} + +/** +*\*\name PWR_Flag_Status_Clear. +*\*\fun Clears the PWR's pending flags. +*\*\param flag : +*\*\ - PWR_WKUP_FLAG +*\*\ - PWR_DBGPD_FLAG +*\*\return none +**/ +void PWR_Flag_Status_Clear(uint32_t flag) +{ + if(flag == PWR_DBGPD_FLAG) + { + PWR->CTRL |= (flag << PWR_BIT_SHIFT_2); + } + else + { + PWR->CTRL |= (flag << PWR_BIT_SHIFT_2); + } +} + +/** +*\*\name DBG_Peripheral_ON. +*\*\fun Configures the specified peripheral run when the MCU under Debug mode. +*\*\param DBG_Periph : +*\*\ - PWR_DBG_STOP Keep debugger connection during STOP mode +*\*\ - PWR_DBG_PD Keep debugger connection during PD mode +*\*\ - PWR_DBG_IWDG IWDG stopped when Core is halted +*\*\ - PWR_DBG_TIM1 TIM1 counter stopped when Core is halted +*\*\ - PWR_DBG_TIM3 TIM3 counter stopped when Core is halted +*\*\ - PWR_DBG_TIM6 TIM6 counter stopped when Core is halted +*\*\return none +**/ +void DBG_Peripheral_ON(uint32_t DBG_Periph) +{ + PWR->DBG_CTRL |= DBG_Periph; +} + +/** +*\*\name DBG_Peripheral_OFF. +*\*\fun Configures the specified peripheral run or stop when the MCU under Debug mode. +*\*\param DBG_Periph : +*\*\ - PWR_DBG_STOP Keep debugger connection during STOP mode +*\*\ - PWR_DBG_PD Keep debugger connection during PD mode +*\*\ - PWR_DBG_IWDG IWDG stopped when Core is halted +*\*\ - PWR_DBG_TIM1 TIM1 counter stopped when Core is halted +*\*\ - PWR_DBG_TIM3 TIM3 counter stopped when Core is halted +*\*\ - PWR_DBG_TIM6 TIM6 counter stopped when Core is halted +*\*\return none +**/ +void DBG_Peripheral_OFF(uint32_t DBG_Periph) +{ + PWR->DBG_CTRL &= (~DBG_Periph); +} + diff --git a/firmware/n32g003_std_periph_driver/src/n32g003_rcc.c b/firmware/n32g003_std_periph_driver/src/n32g003_rcc.c new file mode 100644 index 0000000..89f1c93 --- /dev/null +++ b/firmware/n32g003_std_periph_driver/src/n32g003_rcc.c @@ -0,0 +1,708 @@ +/** +* Copyright (c) 2022, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** +*\*\file n32g003_rcc.c +*\*\author Nations +*\*\version v1.0.0 +*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. + */ +#include "n32g003_rcc.h" + + +/** RCC_Private_Defines **/ +static __I uint8_t AHBPresTable[16] = {1, 1, 1, 1, 1, 1, 1, 1, 2, 4, 8, 12, 16, 24, 24,24}; +static __I uint8_t APBPresTable[8] = {1, 1, 1, 1, 2, 4, 8, 16}; +static __I uint8_t ADCCLKPresTable[16] = {1, 2, 3, 4, 6, 8, 10, 12, 24, 32, 32, 32, 32, 32, 32, 32}; +static __I uint8_t ADC1MCLKPresTable[4] = {6, 12, 24, 48}; + + +/** RCC Driving Functions Declaration **/ + +/** +*\*\name RCC_Reset. +*\*\fun Reset the RCC registers. +*\*\param none +*\*\return none +**/ +void RCC_Reset(void) +{ + /* Set SYSPRES[1:0] bit */ + RCC->CFG |= (uint32_t)0x00003000; + + /* Reset MCO[1:0] APBPRES[2:0] AHBPRES[3:0] bit */ + RCC->CFG &= (uint32_t)0xF9FFF80F; + + /* Reset LSIDETEN bit */ + RCC->LSICTRL &= (uint32_t)0xFFFFFF7F; + + /* Reset TIM1CLKSEL TIM6CLKSEL ADCPRES[3:0]bit */ + RCC->CFG2 &= (uint32_t)0x3FFFFFF0; + + /* Set ADC1MPRES[1:0] ADCPRES[3:0]bit */ + RCC->CFG2 |= (uint32_t)0x00000C01; + +} + + +/** +*\*\name RCC_HSI_Calibration_Value_Set. +*\*\fun Adjusts the Internal High Speed oscillator (HSI) calibration value. +*\*\param calibration_value(the calibration trimming value): +*\*\ This parameter must be a number between 0 and 0x0F +*\*\return none +**/ +void RCC_HSI_Calibration_Value_Set(uint8_t calibration_value) +{ + uint32_t temp_value = 0; + + temp_value = RCC->HSICTRL; + /* Clear HSITRIM[3:0] bits */ + temp_value &= RCC_HSITRIM_MASK; + /* Set the HSITRIM[3:0] bits according to HSICalibrationValue value */ + temp_value |= (uint32_t)calibration_value << RCC_CTRL_HSITRIM_OFFSET; + /* Store the new value */ + RCC->HSICTRL = temp_value; +} + +/** +*\*\name RCC_LSI_Calibration_Value_Set. +*\*\fun Adjusts the Internal Low Speed oscillator (LSI) calibration value. +*\*\param calibration_value(the calibration trimming value): +*\*\ This parameter must be a number between 0 and 0x1F +*\*\return none +**/ +void RCC_LSI_Calibration_Value_Set(uint8_t calibration_value) +{ + uint32_t temp_value = 0; + + temp_value = RCC->LSICTRL; + /* Clear LSITRIM[4:0] bits */ + temp_value &= RCC_LSITRIM_MASK; + /* Set the LSITRIM[4:0] bits according to LSICalibrationValue value */ + temp_value |= (uint32_t)calibration_value << RCC_CTRL_LSITRIM_OFFSET; + /* Store the new value */ + RCC->LSICTRL = temp_value; +} + +/** +*\*\name RCC_Sysclk_Config. +*\*\fun Configures the system clock (SYSCLK). +*\*\When HSI is 48M: +*\*\param HSI_div(system clock is derived from the HSI clock): +*\*\ - RCC_HSICLK_DIV1 system clock = HSI clock +*\*\ - RCC_HSICLK_DIV2 system clock = HSI clock/2 +*\*\ - RCC_HSICLK_DIV6 system clock = HSI clock/6 +*\*\When HSI is 40M: +*\*\param HSI_div(system clock is derived from the HSI clock): +*\*\ - RCC_HSICLK_DIV1 system clock = HSI clock +*\*\ - RCC_HSICLK_DIV5 system clock = HSI clock/5 +*\*\return none +**/ +void RCC_Sysclk_Config(uint32_t HSI_div) +{ + uint32_t temp_value = 0; + temp_value = RCC->CFG; + /* Clear SYSPRES[1:0] bits */ + temp_value &= RCC_HSICLK_DIV_MASK; + /* Set SYSPRES[1:0] bits according to HSI_div value */ + temp_value |= HSI_div; + /* Store the new value */ + RCC->CFG = temp_value; +} + +/** +*\*\name RCC_Hclk_Config. +*\*\fun Configures the AHB clock (HCLK). +*\*\param sysclk_div(AHB clock is derived from the system clock (SYSCLK)): +*\*\ - RCC_SYSCLK_DIV1 AHB clock = SYSCLK +*\*\ - RCC_SYSCLK_DIV2 AHB clock = SYSCLK/2 +*\*\ - RCC_SYSCLK_DIV4 AHB clock = SYSCLK/4 +*\*\ - RCC_SYSCLK_DIV8 AHB clock = SYSCLK/8 +*\*\ - RCC_SYSCLK_DIV12 AHB clock = SYSCLK/12 +*\*\ - RCC_SYSCLK_DIV16 AHB clock = SYSCLK/16 +*\*\ - RCC_SYSCLK_DIV24 AHB clock = SYSCLK/24 +*\*\return none +**/ +void RCC_Hclk_Config(uint32_t sysclk_div) +{ + uint32_t temp_value = 0; + temp_value = RCC->CFG; + /* Clear AHBPRES[3:0] bits */ + temp_value &= RCC_SYSCLK_DIV_MASK; + /* Set AHBPRES[3:0] bits according to rcc_sysclk value */ + temp_value |= sysclk_div; + /* Store the new value */ + RCC->CFG = temp_value; +} + + +/** +*\*\name RCC_Pclk_Config. +*\*\fun Configures the Low Speed APB clock (PCLK1). +*\*\param hclk_div(APB1 clock is derived from the AHB clock (HCLK)): +*\*\ - RCC_HCLK_DIV1 APB1 clock = HCLK +*\*\ - RCC_HCLK_DIV2 APB1 clock = HCLK/2 +*\*\ - RCC_HCLK_DIV4 APB1 clock = HCLK/4 +*\*\ - RCC_HCLK_DIV8 APB1 clock = HCLK/8 +*\*\ - RCC_HCLK_DIV16 APB1 clock = HCLK/16 +*\*\return none +**/ +void RCC_Pclk_Config(uint32_t hclk_div) +{ + uint32_t temp_value = 0; + temp_value = RCC->CFG; + /* Clear APB1PRES[2:0] bits */ + temp_value &= RCC_APB_DIV_MASK; + /* Set APB1PRES[2:0] bits according to hclk_div value */ + temp_value |= hclk_div; + /* Store the new value */ + RCC->CFG = temp_value; +} + + +/** +*\*\name RCC_TIM1_Clock_Config. +*\*\fun Configures the TIM1 clock source(TIM1CLK). +*\*\param timer_clksrc(TIM1 clock source): +*\*\ - RCC_TIM1_CLKSRC_PCLK +*\*\ - RCC_TIM1_CLKSRC_SYSCLK +*\*\return none +**/ +void RCC_TIM1_Clock_Config(uint32_t timer_clksrc) +{ + uint32_t temp_value = 0; + + temp_value = RCC->CFG2; + /* Clear TIMCLK_SEL bits */ + temp_value &= RCC_TIM1_CLKSRC_MASK; + /* Set TIMCLK_SEL bits according to timer_clksrc value */ + temp_value |= timer_clksrc; + + /* Store the new value */ + RCC->CFG2 = temp_value; +} + + +/** +*\*\name RCC_ADC_1M_Clock_Config. +*\*\fun Configures the ADC 1M clock (ADC1MCLK). +*\*\param ADC1M_prescaler(ADC1M clock prescaler): +*\*\ - RCC_ADC1MCLK_DIV6 HSI Clock Divided By 6 +*\*\ - RCC_ADC1MCLK_DIV12 HSI Clock Divided By 12 +*\*\ - RCC_ADC1MCLK_DIV24 HSI Clock Divided By 24 +*\*\ - RCC_ADC1MCLK_DIV40 HSI Clock Divided By 40 +*\*\ - RCC_ADC1MCLK_DIV48 HSI Clock Divided By 48 +*\*\return none +*\*\note To ensure normal work of the ADC module, the HSI divide result must be 1Mhz. +**/ +void RCC_ADC_1M_Clock_Config(uint32_t ADC1M_prescaler) +{ + uint32_t temp_value = 0; + + temp_value = RCC->CFG2; + /* Clear ADC1MPRE[1:0] bits */ + temp_value &= RCC_ADC1MCLK_DIV_MASK; + + /* Set ADC1MPRE[1:0] bits according to ADC1M_prescaler value */ + temp_value |= ADC1M_prescaler; + + /* Store the new value */ + RCC->CFG2 = temp_value; +} + + +/** +*\*\name RCC_ADC_Clock_Config. +*\*\fun Configures the ADCHCLK prescaler. +*\*\param ADC_prescaler(ADCHCLK prescaler): +*\*\ - RCC_ADC_DIV1 HSI Clock Divided By 1 +*\*\ - RCC_ADC_DIV2 HSI Clock Divided By 2 +*\*\ - RCC_ADC_DIV3 HSI Clock Divided By 3 +*\*\ - RCC_ADC_DIV4 HSI Clock Divided By 4 +*\*\ - RCC_ADC_DIV6 HSI Clock Divided By 6 +*\*\ - RCC_ADC_DIV8 HSI Clock Divided By 8 +*\*\ - RCC_ADC_DIV10 HSI Clock Divided By 10 +*\*\ - RCC_ADC_DIV12 HSI Clock Divided By 12 +*\*\ - RCC_ADC_DIV24 HSI Clock Divided By 24 +*\*\ - RCC_ADC_DIV32 HSI Clock Divided By 32 +*\*\ - RCC_ADC_DIV_OTHERS HSI Clock Divided By 32 +*\*\return none +**/ +void RCC_ADC_Clock_Config(uint32_t ADC_prescaler) +{ + uint32_t temp_value = 0; + + temp_value = RCC->CFG2; + /* Clear ADCPRES[3:0] bits */ + temp_value &= RCC_ADC_DIV_MASK; + /* Set ADCPRES[3:0] bits according to ADC_prescaler value */ + temp_value |= ADC_prescaler; + + /* Store the new value */ + RCC->CFG2 = temp_value; +} + + +/** +*\*\name RCC_TIM6_Clock_Config. +*\*\fun Configures the TIM6 clock source(TIM6CLK). +*\*\param timer_clksrc(TIM6 clock source): +*\*\ - RCC_TIM6_CLKSRC_PCLK +*\*\ - RCC_TIM6_CLKSRC_LSI +*\*\return none +**/ +void RCC_TIM6_Clock_Config(uint32_t timer_clksrc) +{ + uint32_t temp_value = 0; + + temp_value = RCC->CFG2; + /* Clear TIM6CLK_SEL bits */ + temp_value &= RCC_TIM6_CLKSRC_MASK; + /* Set TIM6CLK_SEL bits according to timer_clksrc value */ + temp_value |= timer_clksrc; + + /* Store the new value */ + RCC->CFG2 = temp_value; +} + + +/** +*\*\name RCC_Clocks_Frequencies_Value_Get. +*\*\fun Returns the frequencies of different on chip clocks. +*\*\param RCC_clocks pointer to a RCC_ClocksType structure which will hold +*\*\ the clocks frequencies. +*\*\return none +*\*\note The result of this function could be not correct when using +*\*\ fractional value for HSI crystal. +**/ +void RCC_Clocks_Frequencies_Value_Get(RCC_ClocksType* RCC_clocks) +{ + uint32_t temp_value = 0; + uint32_t presc_value = 0; + + /* Get SYSCLK source + * -------------------------------------------------------*/ + temp_value = PWR->CTRL3 & PWR_CTRL3_HSISEL; + + switch (temp_value) + { + case PWR_CTRL3_HSISEL: /* HSI 40M used as system clock */ + if((RCC->CFG & RCC_CFG_SYSPRES) == RCC_HSICLK_DIV1) + { + RCC_clocks->SysclkFreq = SYSCLK_FREQ_40M; + } + else + { + RCC_clocks->SysclkFreq = SYSCLK_FREQ_8M; + } + + /* Get ADCCLK prescaler */ + presc_value = ADCCLKPresTable[(RCC->CFG & RCC_CFG2_ADCPRES)]; + /* ADCCLK clock frequency */ + RCC_clocks->AdcClkFreq = HSI_FREQ_40M/presc_value; + + /* Get ADC1MCLK prescaler */ + RCC_clocks->Adc1MClkFreq = HSI_FREQ_40M/40; + + break; + + default:/* HSI 48M used as system clock */ + if((RCC->CFG & RCC_CFG_SYSPRES) == RCC_HSICLK_DIV1) + { + RCC_clocks->SysclkFreq = SYSCLK_FREQ_48M; + } + else if((RCC->CFG & RCC_CFG_SYSPRES) == RCC_HSICLK_DIV2) + { + RCC_clocks->SysclkFreq = SYSCLK_FREQ_24M; + } + else + { + RCC_clocks->SysclkFreq = SYSCLK_FREQ_8M; + } + + /* Get ADCCLK prescaler */ + presc_value = ADCCLKPresTable[(RCC->CFG & RCC_CFG2_ADCPRES)]; + /* ADCCLK clock frequency */ + RCC_clocks->AdcClkFreq = HSI_FREQ_48M/presc_value; + + /* Get ADC1MCLK prescaler */ + presc_value = ADC1MCLKPresTable[((RCC->CFG & RCC_CFG2_ADC1MPRES) >> RCC_CFG2_ADC1MPRES_OFFSET)]; + /* ADCCLK clock frequency */ + RCC_clocks->Adc1MClkFreq = HSI_FREQ_48M/presc_value; + break; + } + + /* Get HCLK prescaler */ + presc_value = AHBPresTable[((RCC->CFG & RCC_CFG_AHBPRES) >> RCC_CFG_AHBPRES_OFFSET)]; + /* HCLK clock frequency */ + RCC_clocks->HclkFreq = RCC_clocks->SysclkFreq/presc_value; + + /* Get PCLK prescaler */ + presc_value = APBPresTable[((RCC->CFG & RCC_CFG_APBPRES) >> RCC_CFG_APBPRES_OFFSET)]; + /* PCLK clock frequency */ + RCC_clocks->PclkFreq = RCC_clocks->HclkFreq/presc_value; + + +} + + + +/** +*\*\name RCC_AHB_Peripheral_Clock_Enable. +*\*\fun Enables the AHB peripheral clock. +*\*\param AHB_periph (AHB peripheral to gates its clock): +*\*\ - RCC_AHB_PERIPH_CRC +*\*\ - RCC_AHB_PERIPH_ADC +*\*\return none +**/ +void RCC_AHB_Peripheral_Clock_Enable(uint32_t AHB_periph) +{ + RCC->AHBPCLKEN |= AHB_periph; +} + +/** +*\*\name RCC_AHB_Peripheral_Clock_Disable. +*\*\fun Disables the AHB peripheral clock. +*\*\param AHB_periph (AHB peripheral to gates its clock): +*\*\ - RCC_AHB_PERIPH_CRC +*\*\ - RCC_AHB_PERIPH_ADC +*\*\return none +**/ +void RCC_AHB_Peripheral_Clock_Disable(uint32_t AHB_periph) +{ + RCC->AHBPCLKEN &= ~AHB_periph; +} + + +/** +*\*\name RCC_APB_Peripheral_Clock_Enable. +*\*\fun Enables the High Speed APB (APB1) peripheral clock. +*\*\param APB_periph (APB1 peripheral to gates its clock): +*\*\ - RCC_APB_PERIPH_AFIO +*\*\ - RCC_APB_PERIPH_BEEPER +*\*\ - RCC_APB_PERIPH_IOPA +*\*\ - RCC_APB_PERIPH_IOPB +*\*\ - RCC_APB_PERIPH_COMP +*\*\ - RCC_APB_PERIPH_COMP_FILT +*\*\ - RCC_APB_PERIPH_UART1 +*\*\ - RCC_APB_PERIPH_UART2 +*\*\ - RCC_APB_PERIPH_I2C +*\*\ - RCC_APB_PERIPH_PWR +*\*\ - RCC_APB_PERIPH_SPI +*\*\ - RCC_APB_PERIPH_TIM1 +*\*\ - RCC_APB_PERIPH_TIM3 +*\*\ - RCC_APB_PERIPH_TIM6 +*\*\ - RCC_APB_PERIPH_IWDG +*\*\return none. +**/ +void RCC_APB_Peripheral_Clock_Enable(uint32_t APB_periph) +{ + RCC->APBPCLKEN |= APB_periph; +} + + +/** +*\*\name RCC_APB_Peripheral_Clock_Disable. +*\*\fun Disables the High Speed APB (APB1) peripheral clock. +*\*\param APB_periph (APB1 peripheral to gates its clock): +*\*\ - RCC_APB_PERIPH_AFIO +*\*\ - RCC_APB_PERIPH_BEEPER +*\*\ - RCC_APB_PERIPH_IOPA +*\*\ - RCC_APB_PERIPH_IOPB +*\*\ - RCC_APB_PERIPH_COMP +*\*\ - RCC_APB_PERIPH_COMP_FILT +*\*\ - RCC_APB_PERIPH_UART1 +*\*\ - RCC_APB_PERIPH_UART2 +*\*\ - RCC_APB_PERIPH_I2C +*\*\ - RCC_APB_PERIPH_PWR +*\*\ - RCC_APB_PERIPH_SPI +*\*\ - RCC_APB_PERIPH_TIM1 +*\*\ - RCC_APB_PERIPH_TIM3 +*\*\ - RCC_APB_PERIPH_TIM6 +*\*\ - RCC_APB_PERIPH_IWDG +*\*\return none. +**/ +void RCC_APB_Peripheral_Clock_Disable(uint32_t APB_periph) +{ + RCC->APBPCLKEN &= ~APB_periph; +} + + +/** +*\*\name RCC_Peripheral_Reset. +*\*\fun AHB and APB peripheral reset. +*\*\param Periph specifies the APB peripheral to reset. +*\*\ - RCC_RST_AFIORST +*\*\ - RCC_RST_BEEPRST +*\*\ - RCC_RST_GPIOARST +*\*\ - RCC_RST_GPIOBRST +*\*\ - RCC_RST_UART1RST +*\*\ - RCC_RST_UART2RST +*\*\ - RCC_RST_I2CRST +*\*\ - RCC_RST_PWRRST +*\*\ - RCC_RST_ADCRST +*\*\ - RCC_RST_SPIRST +*\*\ - RCC_RST_TIM1RST +*\*\ - RCC_RST_TIM3RST +*\*\ - RCC_RST_TIM6RST +*\*\ - RCC_RST_COMPRST +*\*\return none. +**/ +void RCC_Peripheral_Reset(uint32_t Periph) +{ + RCC->PRST |= Periph; + RCC->PRST &= ~Periph; +} + +/** +*\*\name RCC_MCO_Prescaler_Config. +*\*\fun Configures the MCO clock prescaler. +*\*\param MCO_prescaler(MCO clock prescaler): +*\*\ - RCC_MCO_CLK_DIV1 +*\*\ - RCC_MCO_CLK_DIV2 +*\*\ - RCC_MCO_CLK_DIV3 +*\*\ - RCC_MCO_CLK_DIV4 +*\*\ - RCC_MCO_CLK_DIV5 +*\*\ - RCC_MCO_CLK_DIV6 +*\*\ - RCC_MCO_CLK_DIV7 +*\*\ - RCC_MCO_CLK_DIV8 +*\*\ - RCC_MCO_CLK_DIV9 +*\*\ - RCC_MCO_CLK_DIV10 +*\*\ - RCC_MCO_CLK_DIV11 +*\*\ - RCC_MCO_CLK_DIV12 +*\*\ - RCC_MCO_CLK_DIV13 +*\*\ - RCC_MCO_CLK_DIV14 +*\*\ - RCC_MCO_CLK_DIV15 +*\*\ - RCC_MCO_CLK_DIV32 +*\*\return none. +*\*\note if MCO select LSI,the minimum MCO_prescaler is RCC_MCO_CLK_DIV1 +\*\ if MCO select HSI,the minimum MCO_prescaler is RCC_MCO_CLK_DIV2 +**/ +void RCC_MCO_Prescaler_Config(uint32_t MCO_prescaler) +{ + uint32_t temp_value = 0; + + temp_value = RCC->CFG; + /* Clear MCOPRE[3:0] bits */ + temp_value &= RCC_MCO_CLK_DIV_MASK; + /* Set MCOPRE[3:0] bits according to MCO_prescaler value */ + temp_value |= MCO_prescaler; + + /* Store the new value */ + RCC->CFG = temp_value; +} +/** +*\*\name RCC_MCO_Source_Config. +*\*\fun Selects the clock source to output on MCO pin. +*\*\param MCO_source(clock source to output): +*\*\ - RCC_MCO_NOCLK +*\*\ - RCC_MCO_HSI +*\*\ - RCC_MCO_LSI +*\*\return none. +**/ +void RCC_MCO_Source_Config(uint32_t MCO_source) +{ + uint32_t temp_value = 0; + + temp_value = RCC->CFG; + /* Clear MCO[1:0] bits */ + temp_value &= RCC_MCO_MASK; + /* Set MCO[1:0] bits according to MCO_source value */ + temp_value |= MCO_source; + + /* Store the new value */ + RCC->CFG = temp_value; +} + + + + +/** +*\*\name RCC_Flag_Status_Get. +*\*\fun Checks whether the specified RCC flag is set or not. +*\*\param RCC_flag: +*\*\ - RCC_FLAG_HSI40MRDF HSI 40M oscillator clock ready +*\*\ - RCC_FLAG_HSI48MRDF HSI 48M oscillator clock ready +*\*\ - RCC_FLAG_LSIRDF LSI 32k oscillator clock ready +*\*\ - RCC_FLAG_LSIDETFF LSI 32k detect finish +*\*\ - RCC_FLAG_PINRST Pin reset +*\*\ - RCC_FLAG_PORRST POR/PDR reset +*\*\ - RCC_FLAG_SFTRST Software reset +*\*\ - RCC_FLAG_IWDGRST Independent Watchdog reset +*\*\ - RCC_FLAG_LVRRST LVR reset +*\*\ - RCC_FLAG_LPWRRST Low Power reset +*\*\ - RCC_FLAG_EMCCLAMPF EMC Power reset +*\*\return FlagStatus: +*\*\ - SET +*\*\ - RESET +**/ +FlagStatus RCC_Flag_Status_Get(uint8_t RCC_flag) +{ + uint32_t temp_value = 0; + uint32_t reg_value = 0; + + /* Get the RCC register index */ + temp_value = RCC_flag >> RCC_FLAG_OFFSET; + switch(temp_value) + { + case 1: /* The flag to check is in HSICTRL register */ + reg_value = RCC->HSICTRL; + break; + case 2: /* The flag to check is in LSICTRL register */ + reg_value = RCC->LSICTRL; + break; + default:/* The flag to check is in CTRLSTS register */ + reg_value = RCC->CTRLSTS; + break; + } + + /* Get the flag position */ + temp_value = RCC_flag & FLAG_Mask; + if ((reg_value & ((uint32_t)1 << temp_value)) != (uint32_t)RESET) + { + return SET; + } + else + { + return RESET; + } +} + + +/** +*\*\name RCC_Reset_Flag_Clear. +*\*\fun Clears the RCC reset flags. +*\*\param none +*\*\return none +**/ +void RCC_Reset_Flag_Clear(void) +{ + /* Set RMRSTF bit to clear the reset flags */ + RCC->CTRLSTS |= RCC_REMOVE_RESET_FLAG; + /* RMRSTF bit should be reset */ + RCC->CTRLSTS &= (~RCC_REMOVE_RESET_FLAG); +} + + +/** +*\*\name RCC_EMC_Reset_Disable. +*\*\fun Disable the RCC's EMC Clamp reset bits. +*\*\param none +*\*\return none +**/ +void RCC_EMC_Reset_Disable(void) +{ + RCC->EMCCTRL &= (~RCC_EMCCTRL_EMCRSTEN); +} + +/** +*\*\name RCC_EMC_Reset_Enable. +*\*\fun Enable the RCC's EMC Clamp reset bits. +*\*\param none +*\*\return none +**/ +void RCC_EMC_Reset_Enable(void) +{ + RCC->EMCCTRL |= RCC_EMCCTRL_EMCRSTEN; +} + +/** +*\*\name RCC_EMC_Detect_Disable. +*\*\fun Disable the RCC's EMC Clamp detect bits. +*\*\param none +*\*\return none +**/ +void RCC_EMC_Detect_Disable(void) +{ + RCC->EMCCTRL &= (~RCC_EMCCTRL_EMCDETEN); +} + +/** +*\*\name RCC_EMC_Detect_Enable. +*\*\fun Enable the RCC's EMC Clamp detect bits. +*\*\param none +*\*\return none +**/ +void RCC_EMC_Detect_Enable(void) +{ + RCC->EMCCTRL |= RCC_EMCCTRL_EMCDETEN; +} + +/** +*\*\name RCC_LSI_Detect_Disable. +*\*\fun Disable the LSI detect. +*\*\param none +*\*\return none +**/ +void RCC_LSI_Detect_Disable(void) +{ + RCC->LSICTRL &= (~RCC_LSICTRL_LSIDETEN); +} + +/** +*\*\name RCC_LSI_Detect_Enable. +*\*\fun Enable the LSI detect. +*\*\param none +*\*\return none +**/ +void RCC_LSI_Detect_Enable(void) +{ + RCC->LSICTRL |= RCC_LSICTRL_LSIDETEN; +} + +/** +*\*\name RCC_LSI_Clocks_Frequencies_Get. +*\*\fun Get the LSI Frequencies. +*\*\param none +*\*\return LSIFREQ[15:0] (LSI Frequencies LSICLK(kHz)= 8*HSICLK/LSIFREQ[15:0] (HSICLK is 48000kHz or 40000kHz)) +**/ +uint16_t RCC_LSI_Clocks_Frequencies_Get(void) +{ + return (uint16_t)((RCC->LSICTRL & RCC_LSICTRL_LSIFREQ) >> 8); +} +/******************* (C) COPYRIGHT 2018 NATIONZ *****END OF FILE****/ diff --git a/firmware/n32g003_std_periph_driver/src/n32g003_spi.c b/firmware/n32g003_std_periph_driver/src/n32g003_spi.c new file mode 100644 index 0000000..7fdcdb8 --- /dev/null +++ b/firmware/n32g003_std_periph_driver/src/n32g003_spi.c @@ -0,0 +1,518 @@ +/** +* Copyright (c) 2022, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** +*\*\file n32g003_spi.c +*\*\author Nations +*\*\version v1.0.0 +*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. +**/ + +#include "n32g003_spi.h" +#include "n32g003_rcc.h" + +/* SPI Driving Functions Declaration */ + +/** +*\*\name SPI_Reset. +*\*\fun Reset the SPI registers. +*\*\param none +*\*\return none +**/ +void SPI_Reset(void) +{ + /* SPI Reset */ + RCC_Peripheral_Reset(RCC_RST_SPIRST); +} + + +/** +*\*\name SPI_ON. +*\*\fun SPI turn ON. +*\*\param none +*\*\return none +**/ +void SPI_ON(void) +{ + /* Enable SPI */ + SPI->CTRL1 |= SPI_TURN_ON; +} + + +/** +*\*\name SPI_OFF. +*\*\fun SPI turn OFF. +*\*\param none +*\*\return none +**/ +void SPI_OFF(void) +{ + /* Disable SPI */ + SPI->CTRL1 &= SPI_TURN_OFF; +} + + +/** +*\*\name SPI_Initializes_Structure. +*\*\fun Fills each SPI_InitStruct member with its default value. +*\*\param SPI_InitStruct : +*\*\ - DataDirection +*\*\ - SpiMode +*\*\ - DataLen +*\*\ - CLKPOL +*\*\ - CLKPHA +*\*\ - NSS +*\*\ - BaudRatePres +*\*\ - FirstBit +*\*\return none +**/ +void SPI_Initializes_Structure(SPI_InitType* SPI_InitStruct) +{ + /* Initialize the DataDirection member */ + SPI_InitStruct->DataDirection = SPI_DIR_DOUBLELINE_FULLDUPLEX; + /* initialize the SpiMode member */ + SPI_InitStruct->SpiMode = SPI_MODE_SLAVE; + /* initialize the DataLen member */ + SPI_InitStruct->DataLen = SPI_DATA_SIZE_8BITS; + /* Initialize the CLKPOL member */ + SPI_InitStruct->CLKPOL = SPI_CLKPOL_LOW; + /* Initialize the CLKPHA member */ + SPI_InitStruct->CLKPHA = SPI_CLKPHA_FIRST_EDGE; + /* Initialize the NSS member */ + SPI_InitStruct->NSS = SPI_NSS_HARD; + /* Initialize the BaudRatePres member */ + SPI_InitStruct->BaudRatePres = SPI_BR_PRESCALER_2; + /* Initialize the FirstBit member */ + SPI_InitStruct->FirstBit = SPI_FB_MSB; +} + + +/** +*\*\name SPI_DataDirection_Config. +*\*\fun Config the SPI DataDirection. +*\*\param DataDirection : +*\*\ - SPI_DIR_DOUBLELINE_FULLDUPLEX +*\*\ - SPI_DIR_DOUBLELINE_RONLY_TX +*\*\ - SPI_DIR_DOUBLELINE_RONLY_RX +*\*\ - SPI_DIR_SINGLELINE_RX +*\*\ - SPI_DIR_SINGLELINE_TX +*\*\return none +**/ +void SPI_DataDirection_Config(uint16_t DataDirection) +{ + /* Clear SPI_CTRL1[15:14] and [10] bits */ + SPI->CTRL1 &= SPI_DATADIRECTION_MASK; + /* Set SPI_CTRL1[15:14] and [10] bits */ + SPI->CTRL1 |= DataDirection; +} + + +/** +*\*\name SPI_SpiMode_Config. +*\*\fun Config the SPI mode. +*\*\param SpiMode : +*\*\ - SPI_MODE_MASTER +*\*\ - SPI_MODE_SLAVE +*\*\return none +**/ +void SPI_SpiMode_Config(uint16_t SpiMode) +{ + /* Clear SPI_CTRL1 MSEL bits */ + SPI->CTRL1 &= SPI_MODE_MASK; + /* Set SPI_CTRL1 MSEL bits */ + SPI->CTRL1 |= SpiMode; +} + + +/** +*\*\name SPI_DataLen_Config. +*\*\fun Config the SPI DataLen. +*\*\param DataLen : +*\*\ - SPI_DATA_SIZE_16BITS +*\*\ - SPI_DATA_SIZE_8BITS +*\*\return none +*\*\note Must be used with SPI OFF. +**/ +void SPI_DataLen_Config(uint16_t DataLen) +{ + /* Clear SPI_CTRL1 DATFF bits */ + SPI->CTRL1 &= SPI_DATALEN_MASK; + /* Set SPI_CTRL1 DATFF bits */ + SPI->CTRL1 |= DataLen; +} + + +/** +*\*\name SPI_CLKPOL_Config. +*\*\fun Config the SPI CLKPOL. +*\*\param CLKPOL : +*\*\ - SPI_CLKPOL_LOW +*\*\ - SPI_CLKPOL_HIGH +*\*\return none +**/ +void SPI_CLKPOL_Config(uint16_t CLKPOL) +{ + /* Clear SPI_CTRL1 CLKPOL bits */ + SPI->CTRL1 &= SPI_CLKPOL_MASK; + /* Set SPI_CTRL1 CLKPOL bits */ + SPI->CTRL1 |= CLKPOL; +} + + +/** +*\*\name SPI_CLKPHA_Config. +*\*\fun Config the SPI CLKPHA. +*\*\param CLKPHA : +*\*\ - SPI_CLKPHA_FIRST_EDGE +*\*\ - SPI_CLKPHA_SECOND_EDGE +*\*\return none +**/ +void SPI_CLKPHA_Config(uint16_t CLKPHA) +{ + /* Clear SPI_CTRL1 CLKPHA bits */ + SPI->CTRL1 &= SPI_CLKPHA_MASK; + /* Set SPI_CTRL1 CLKPHA bits */ + SPI->CTRL1 |= CLKPHA; +} + + +/** +*\*\name SPI_NSS_Config. +*\*\fun Config the SPI NSS. +*\*\param NSS : +*\*\ - SPI_NSS_SOFT +*\*\ - SPI_NSS_HARD +*\*\return none +**/ +void SPI_NSS_Config(uint16_t NSS) +{ + /* Clear SPI_CTRL1 SSMEN bits */ + SPI->CTRL1 &= SPI_NSS_MASK; + /* Set SPI_CTRL1 SSMEN bits */ + SPI->CTRL1 |= NSS; +} + + +/** +*\*\name SPI_BaudRatePres_Config. +*\*\fun Config the SPI BaudRatePres. +*\*\param BaudRatePres : +*\*\ - SPI_BR_PRESCALER_2 +*\*\ - SPI_BR_PRESCALER_4 +*\*\ - SPI_BR_PRESCALER_8 +*\*\ - SPI_BR_PRESCALER_16 +*\*\ - SPI_BR_PRESCALER_32 +*\*\ - SPI_BR_PRESCALER_64 +*\*\ - SPI_BR_PRESCALER_128 +*\*\ - SPI_BR_PRESCALER_256 +*\*\return none +**/ +void SPI_BaudRatePres_Config(uint16_t BaudRatePres) +{ + /* Clear SPI_CTRL1 BR[2:0] bits */ + SPI->CTRL1 &= SPI_BAUDRATEPRES_MASK; + /* Set SPI_CTRL1 BR[2:0] bits */ + SPI->CTRL1 |= BaudRatePres; +} + + +/** +*\*\name SPI_FirstBit_Config. +*\*\fun Config the SPI FirstBit. +*\*\param FirstBit : +*\*\ - SPI_FB_MSB +*\*\ - SPI_FB_LSB +*\*\return none +**/ +void SPI_FirstBit_Config(uint16_t FirstBit) +{ + /* Clear SPI_CTRL1 LSBFF bits */ + SPI->CTRL1 &= SPI_FIRSTBIT_MASK; + /* Set SPI_CTRL1 LSBFF bits */ + SPI->CTRL1 |= FirstBit; +} + + +/** +*\*\name SPI_Initializes. +*\*\fun Initializes the SPI according to SPI_InitStruct. +*\*\param SPI_InitStruct : +*\*\ - DataDirection +*\*\ - SPI_DIR_DOUBLELINE_FULLDUPLEX +*\*\ - SPI_DIR_DOUBLELINE_RONLY_TX +*\*\ - SPI_DIR_DOUBLELINE_RONLY_RX +*\*\ - SPI_DIR_SINGLELINE_RX +*\*\ - SPI_DIR_SINGLELINE_TX +*\*\ - SpiMode +*\*\ - SPI_MODE_MASTER +*\*\ - SPI_MODE_SLAVE +*\*\ - DataLen +*\*\ - SPI_DATA_SIZE_16BITS +*\*\ - SPI_DATA_SIZE_8BITS +*\*\ - CLKPOL +*\*\ - SPI_CLKPOL_LOW +*\*\ - SPI_CLKPOL_HIGH +*\*\ - CLKPHA +*\*\ - SPI_CLKPHA_FIRST_EDGE +*\*\ - SPI_CLKPHA_SECOND_EDGE +*\*\ - NSS +*\*\ - SPI_NSS_SOFT +*\*\ - SPI_NSS_HARD +*\*\ - BaudRatePres +*\*\ - SPI_BR_PRESCALER_2 +*\*\ - SPI_BR_PRESCALER_4 +*\*\ - SPI_BR_PRESCALER_8 +*\*\ - SPI_BR_PRESCALER_16 +*\*\ - SPI_BR_PRESCALER_32 +*\*\ - SPI_BR_PRESCALER_64 +*\*\ - SPI_BR_PRESCALER_128 +*\*\ - SPI_BR_PRESCALER_256 +*\*\ - FirstBit +*\*\ - SPI_FB_MSB +*\*\ - SPI_FB_LSB +*\*\return none +**/ +void SPI_Initializes(SPI_InitType* SPI_InitStruct) +{ + SPI_DataDirection_Config(SPI_InitStruct->DataDirection); + SPI_SpiMode_Config(SPI_InitStruct->SpiMode); + SPI_DataLen_Config(SPI_InitStruct->DataLen); + SPI_CLKPHA_Config(SPI_InitStruct->CLKPHA); + SPI_CLKPOL_Config(SPI_InitStruct->CLKPOL); + SPI_NSS_Config(SPI_InitStruct->NSS); + SPI_BaudRatePres_Config(SPI_InitStruct->BaudRatePres); + SPI_FirstBit_Config(SPI_InitStruct->FirstBit); +} + + +/** +*\*\name SPI_Set_Nss_Level. +*\*\fun Configures internally by software the NSS pin for the selected SPI. +*\*\param SPI_NSS_Internal_Soft : +*\*\ - SPI_NSS_HIGH +*\*\ - SPI_NSS_LOW +*\*\return none +**/ +void SPI_Set_Nss_Level(uint16_t SPI_NSS_Internal_Soft) +{ + if(SPI_NSS_Internal_Soft == SPI_NSS_HIGH) + { + /* Set NSS pin internally by software */ + SPI->CTRL1 |= SPI_NSS_HIGH; + } + else + { + /* Reset NSS pin internally by software */ + SPI->CTRL1 &= SPI_NSS_LOW; + } +} + +/** +*\*\name SPI_NSS_Output_Enable. +*\*\fun Enables the NSS output for the selected SPI. +*\*\return none +**/ +void SPI_NSS_Output_Enable(void) +{ + /* Set the SPI_CTRL2 SSOEN bit to enable NSS output */ + SPI->CTRL2 |= SPI_NSS_OUTPUT_ENABLE; +} + +/** +*\*\name SPI_NSS_Output_Disable. +*\*\fun Disable the NSS output for the selected SPI. +*\*\return none +**/ +void SPI_NSS_Output_Disable(void) +{ + /* Clean the SPI_CTRL2 SSOEN bit to disable SS output */ + SPI->CTRL2 &= SPI_NSS_OUTPUT_DISABLE; +} + + +/** +*\*\name SPI_Interrupts_Enable. +*\*\fun Enable SPI interrupts. +*\*\param spi_interrupt : +*\*\ - SPI_INT_TE SPI_CTRL2 +*\*\ - SPI_INT_RNE SPI_CTRL2 +*\*\ - SPI_INT_ERR SPI_CTRL2 +*\*\return none +**/ +void SPI_Interrupts_Enable(uint8_t spi_interrupt) +{ + /* Set the SPI_CTRL2 TEINTEN/RNEINTEN/ERRINTEN bit to enable SPI interrupts */ + SPI->CTRL2 |= spi_interrupt; +} + +/** +*\*\name SPI_Interrupts_Disable. +*\*\fun Disable SPI interrupts. +*\*\param spi_interrupt : +*\*\ - SPI_INT_TE SPI_CTRL2 +*\*\ - SPI_INT_RNE SPI_CTRL2 +*\*\ - SPI_INT_ERR SPI_CTRL2 +*\*\return none +**/ +void SPI_Interrupts_Disable(uint8_t spi_interrupt) +{ + /* Clean the SPI_CTRL2 TEINTEN/RNEINTEN/ERRINTEN bit to disable SPI interrupts */ + SPI->CTRL2 &= (~spi_interrupt); +} + + +/** +*\*\name SPI_Data_Transmit. +*\*\fun Transmits a Data through the SPI peripheral. +*\*\param Data: data to be transmitted +*\*\return none +**/ +void SPI_Data_Transmit(uint16_t Data) +{ + /* Write in the SPI_DAT register the data to be sent */ + SPI->DAT = Data; +} + + +/** +*\*\name SPI_Data_Get. +*\*\fun Get SPI data from SPI_DAT register. +*\*\return The data in the SPI_DAT register +**/ +uint16_t SPI_Data_Get(void) +{ + /* Return the data in the SPI_DAT register */ + return SPI->DAT; +} + + +/** +*\*\name SPI_Flag_Status_Get. +*\*\fun Get SPI flag status. +*\*\param spi_flag : +*\*\ - SPI_FLAG_TE +*\*\ - SPI_FLAG_RNE +*\*\ - SPI_FLAG_BUSY +*\*\ - SPI_FLAG_OVER +*\*\ - SPI_FLAG_MODERR +*\*\return SET or RESET +**/ +FlagStatus SPI_Flag_Status_Get(uint8_t spi_flag) +{ + return (((SPI->STS & spi_flag) == spi_flag) ? SET : RESET); +} + +/** +*\*\name SPI_Interrupt_Flag_Status_Get. +*\*\fun Get SPI interrupt flag status. +*\*\param spi_flag : +*\*\ - SPI_INT_FLAG_RNE +*\*\ - SPI_INT_FLAG_TE +*\*\ - SPI_INT_FLAG_MODERR +*\*\ - SPI_INT_FLAG_OVER +*\*\ - SPI_INT_FLAG_ERR +*\*\return SET or RESET +**/ +FlagStatus SPI_Interrupt_Flag_Status_Get(uint16_t spi_flag) +{ + /* Interrupt flag */ + switch (spi_flag) + { + case SPI_INT_FLAG_TE: + if((SPI->CTRL2 & SPI_INT_TE) == SPI_INT_TE && (SPI->STS & SPI_INT_FLAG_TE) == SPI_INT_FLAG_TE) + { + return SET; + } + else + { + return RESET; + } + + case SPI_INT_FLAG_RNE: + if((SPI->CTRL2 & SPI_INT_RNE) && (SPI->STS & SPI_INT_FLAG_RNE)) + { + return SET; + } + else + { + return RESET; + } + + case SPI_INT_FLAG_ERR: + case SPI_INT_FLAG_MODERR: + case SPI_INT_FLAG_OVER: + if((SPI->CTRL2 & SPI_INT_ERR) && (SPI->STS & spi_flag)) + { + return SET; + } + else + { + return RESET; + } + + default: + return RESET; + } +} + + +/** +*\*\name SPI_Clear_Flag_Status. +*\*\fun Get SPI flag status. +*\*\param none +*\*\return none +**/ +void SPI_OVER_Flag_Clear(void) +{ + volatile u8 temp_vlue; + + /* read SPI_DAT and SPI_STS to Clear the Flag*/ + temp_vlue = SPI->DAT; + temp_vlue = SPI->STS; +} + + diff --git a/firmware/n32g003_std_periph_driver/src/n32g003_tim.c b/firmware/n32g003_std_periph_driver/src/n32g003_tim.c new file mode 100644 index 0000000..78ef4f7 --- /dev/null +++ b/firmware/n32g003_std_periph_driver/src/n32g003_tim.c @@ -0,0 +1,2850 @@ +/** +* Copyright (c) 2022, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + +/** +*\*\file n32g003_tim.c +*\*\author Nations +*\*\version v1.0.0 +*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. +**/ +#include "n32g003_tim.h" +#include "n32g003_rcc.h" + +/** +*\*\name TIM_Reset. +*\*\fun Reset the TIM registers. +*\*\param TIMx : +*\*\ - TIM1 +*\*\ - TIM3 +*\*\ - TIM6 +*\*\return none +**/ +void TIM_Reset(TIM_Module* TIMx) +{ + + if (TIMx == TIM1) + { + RCC_Peripheral_Reset(RCC_RST_TIM1RST); + } + else if (TIMx == TIM3) + { + RCC_Peripheral_Reset(RCC_RST_TIM3RST); + } + else if (TIMx == TIM6) + { + RCC_Peripheral_Reset(RCC_RST_TIM6RST); + } +} + +/** +*\*\name TIM_Base_Count_Mode_Set. +*\*\fun Initializes the TIM cnt mode in up mode or down mode. +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\param cnt_mode +*\*\ - TIM_CNT_MODE_UP +*\*\ - TIM_CNT_MODE_DOWN +*\*\ - TIM_CNT_MODE_CENTER_ALIGN1 TIM Center Aligned Mode1 +*\*\ - TIM_CNT_MODE_CENTER_ALIGN2 TIM Center Aligned Mode2 +*\*\ - TIM_CNT_MODE_CENTER_ALIGN3 TIM Center Aligned Mode3 +*\*\return none +*\*\note The counting direction of TIM6 is fixed upward counting +**/ +void TIM_Base_Count_Mode_Set(TIM_Module* TIMx, uint32_t cnt_mode) +{ + uint32_t temp_value = 0; + + temp_value = TIMx->CTRL1; + /* Reset the CMS and DIR Bits */ + temp_value &= (uint32_t)(~((uint32_t)(TIM_CTRL1_DIR | TIM_CTRL1_CAMSEL))); + /* Set the Counter Mode */ + temp_value |= cnt_mode; + /* Write to TIMx CTRL1 register */ + TIMx->CTRL1 = temp_value; +} + + +/** +*\*\name TIM_Base_Auto_Reload_Set. +*\*\fun Initializes the TIM AR value +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\ - TIM6 +*\*\param auto_reload： + - [1, 0xffff] +*\*\return none +**/ +void TIM_Base_Auto_Reload_Set(TIM_Module* TIMx, uint16_t auto_reload) +{ + TIMx->AR = auto_reload; +} + +/** +*\*\name TIM_Base_Prescaler_Set. +*\*\fun Initializes the TIM PSC value +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\ - TIM6 +*\*\param prescaler +*\*\return none +**/ +void TIM_Base_Prescaler_Set(TIM_Module* TIMx, uint16_t prescaler) +{ + TIMx->PSC = prescaler; +} + +/** +*\*\name TIM_Base_Reload_Mode_Set. +*\*\fun Initializes the TIM reload mode +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\ - TIM6 +*\*\param prescaler_reload_mode: +**\ - TIM_PSC_RELOAD_MODE_IMMEDIATE +**\ - TIM_PSC_RELOAD_MODE_UPDATE +*\*\return none +**/ +void TIM_Base_Reload_Mode_Set(TIM_Module* TIMx, uint16_t prescaler_reload_mode) +{ + TIMx->EVTGEN = prescaler_reload_mode; +} + +/** +*\*\name TIM_Base_Repeat_Count_Set. +*\*\fun Initializes the TIM repeat cnt +*\*\param TIMx: +*\*\ - TIM1 +*\*\param repeat_cnt +*\*\ - [0,255] +*\*\return none +**/ +void TIM_Base_Repeat_Count_Set(TIM_Module* TIMx, uint8_t repeat_cnt) +{ + TIMx->REPCNT = repeat_cnt; +} + +/** +*\*\name TIM_Base_Channel1. +*\*\param TIMx: +*\*\ - TIM1 +*\*\param channel_selection: +**\ - 1 +**\ CH1 is from COMP +**\ - 0 +**\ CH1 is from IO +*\*\return none +*\*\note not for TIM6 +**/ +void TIM_Base_Channel1(TIM_Module* TIMx, bool channel_selection) +{ + if(channel_selection) + { + TIMx->CTRL1 |= TIM_CH1_SEL; + } + else + { + TIMx->CTRL1 &= (uint32_t)(~TIM_CH1_SEL); + } +} + + +/** +*\*\name TIM_Base_OCrefClear. +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\param OCrefClear_selection: +**\ - 1 +**\ OCrefClear is from ETR +**\ - 0 +**\ OCrefClear is from COMP +*\*\return none +*\*\note Not for TIM6 +**/ +void TIM_Base_OCrefClear(TIM_Module* TIMx, bool OCrefClear_selection) +{ + if (OCrefClear_selection) + { + TIMx->CTRL1 |= TIM_OCREF_CLEAR_SEL; + } + else + { + TIMx->CTRL1 &= (uint32_t)(~TIM_OCREF_CLEAR_SEL); + } +} + +/** +*\*\name TIM_Base_Init. +*\*\fun Initializes the TIMx Time Base Unit peripheral according to +*\*\ the specified parameters in the TIM_TimeBaseInitStruct. +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\ - TIM6 +*\*\param TIM_TimeBaseInitStruct: +*\*\ - refer to the definition of TIM_TimeBaseInitType +*\*\return none +**/ +void TIM_Base_Initialize(TIM_Module* TIMx, TIM_TimeBaseInitType* TIM_TimeBaseInitStruct) +{ + if (TIMx != TIM6) + { + TIM_Base_Count_Mode_Set(TIMx, TIM_TimeBaseInitStruct->CntMode); + TIM_Clock_Division_Set(TIMx, TIM_TimeBaseInitStruct->ClkDiv); + } + else + { + /* none */ + } + + TIM_Base_Auto_Reload_Set(TIMx, TIM_TimeBaseInitStruct->Period); + + TIM_Base_Prescaler_Set(TIMx, TIM_TimeBaseInitStruct->Prescaler); + + if (TIMx == TIM1) + { + TIM_Base_Repeat_Count_Set(TIMx,TIM_TimeBaseInitStruct->RepetCnt); + } + else + { + /* none */ + } + + TIM_Base_Reload_Mode_Set(TIMx, TIM_PSC_RELOAD_MODE_IMMEDIATE); + + if ((TIMx != TIM6)) + { + TIM_Base_Channel1(TIMx, TIM_TimeBaseInitStruct->CapCh1Sel); + } + else + { + /* none */ + } + + if ((TIMx == TIM1) || (TIMx == TIM3)) + { + TIM_Base_OCrefClear(TIMx, TIM_TimeBaseInitStruct->CapEtrClrFromCompEn); + } + else + { + /* none */ + } + +} + +void TIM_Base_Struct_Initialize(TIM_TimeBaseInitType* TIM_TimeBaseInitStruct) +{ + /* Set the default configuration */ + TIM_TimeBaseInitStruct->Period = 0xFFFF; + TIM_TimeBaseInitStruct->Prescaler = 0x0000; + TIM_TimeBaseInitStruct->ClkDiv = TIM_CLK_DIV1; + TIM_TimeBaseInitStruct->CntMode = TIM_CNT_MODE_UP; + TIM_TimeBaseInitStruct->RepetCnt = 0x0000; + + TIM_TimeBaseInitStruct->CapCh1Sel = false; + TIM_TimeBaseInitStruct->CapEtrClrFromCompEn = false; +} +/** +*\*\name TIM_Base_Count_Set. +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\ - TIM6 +*\*\param count: +*\*\return none +**/ +void TIM_Base_Count_Set(TIM_Module* TIMx, uint16_t count) +{ + TIMx->CNT= count; +} +/** +*\*\name TIM_Base_Count_Get. +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\ - TIM6 +*\*\return the value of count register +**/ +uint16_t TIM_Base_Count_Get(TIM_Module* TIMx) +{ + /* Get the value of count register */ + return TIMx->CNT; +} + +/** +*\*\name TIM_Auto_Reload_Get. +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\ - TIM6 +*\*\return the value of auto reload register +**/ +uint16_t TIM_Auto_Reload_Get(TIM_Module* TIMx) +{ + /* Get the value of auto reload register */ + return TIMx->AR; +} + +/** +*\*\name TIM_Base_Prescaler_Get. +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\ - TIM6 +*\*\return the value of prescaler register +**/ +uint16_t TIM_Base_Prescaler_Get(TIM_Module* TIMx) +{ + /* Get the value of prescaler register */ + return TIMx->PSC; +} + + +/** +*\*\name TIM_On. +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\ - TIM6 +*\*\return none +**/ +void TIM_On(TIM_Module* TIMx) +{ + TIMx->CTRL1 |= TIM_ON; +} + +/** +*\*\name TIM_Off. +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\ - TIM6 +*\*\return none +**/ +void TIM_Off(TIM_Module* TIMx) +{ + TIMx->CTRL1 &= (uint32_t)(~((uint32_t)TIM_ON)); +} + +/** +*\*\name TIM_Output_Channel1_Preload_Set +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\param TIM_output_channel_preload +*\*\ - TIM_OC_PRELOAD_ENABLE +*\*\ - TIM_OC_PRELOAD_DISABLE +*\*\return none +**/ +void TIM_Output_Channel1_Preload_Set(TIM_Module* TIMx, uint16_t TIM_output_channel_preload) +{ + uint16_t temp_value = 0; + + temp_value = TIMx->CCMOD1; + /* Reset the OC1PE Bit */ + temp_value &= (uint16_t) ~((uint16_t)TIM_OC1_PRELOAD_MASK); + /* Enable or Disable the Output Compare Preload feat_value |= (uint16_t)TIM_output_channel_preload;*/ + temp_value |= TIM_output_channel_preload; + /* Write to TIMx CCMOD1 register */ + TIMx->CCMOD1 = temp_value; +} + +/** +*\*\name TIM_Output_Channel2_Preload_Set +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\param TIM_output_channel_preload +*\*\ - TIM_OC_PRELOAD_ENABLE +*\*\ - TIM_OC_PRELOAD_DISABLE +*\*\return none +**/ +void TIM_Output_Channel2_Preload_Set(TIM_Module* TIMx, uint16_t TIM_output_channel_preload) +{ + uint16_t temp_value = 0; + + temp_value = TIMx->CCMOD1; + /* Reset the OC1PE Bit */ + temp_value &= (uint16_t) ~((uint16_t)TIM_OC2_PRELOAD_MASK); + /* Enable or Disable the Output Compare Preload feature */ + temp_value |= (uint16_t)(TIM_output_channel_preload << 8); + /* Write to TIMx CCMOD1 register */ + TIMx->CCMOD1 = temp_value; +} + +/** +*\*\name TIM_Output_Channel3_Preload_Set +*\*\param TIMx: +*\*\ - TIM1 +*\*\param TIM_output_channel_preload +*\*\ - TIM_OC_PRELOAD_ENABLE +*\*\ - TIM_OC_PRELOAD_DISABLE +*\*\return none +**/ +void TIM_Output_Channel3_Preload_Set(TIM_Module* TIMx, uint16_t TIM_output_channel_preload) +{ + uint16_t temp_value = 0; + + temp_value = TIMx->CCMOD2; + /* Reset the OC1PE Bit */ + temp_value &= (uint16_t) ~((uint16_t)TIM_OC3_PRELOAD_MASK); + /* Enable or Disable the Output Compare Preload feature */ + temp_value |= TIM_output_channel_preload; + /* Write to TIMx CCMOD2 register */ + TIMx->CCMOD2 = temp_value; +} + +/** +*\*\name TIM_Output_Channel4_Preload_Set +*\*\param TIMx: +*\*\ - TIM1 +*\*\param TIM_output_channel_preload +*\*\ - TIM_OC_PRELOAD_ENABLE +*\*\ - TIM_OC_PRELOAD_DISABLE +*\*\return none +**/ +void TIM_Output_Channel4_Preload_Set(TIM_Module* TIMx, uint16_t TIM_output_channel_preload) +{ + uint16_t temp_value = 0; + + temp_value = TIMx->CCMOD2; + /* Reset the OC1PE Bit */ + temp_value &= (uint16_t) ~((uint16_t)TIM_OC4_PRELOAD_MASK); + /* Enable or Disable the Output Compare Preload feature */ + temp_value |= (uint16_t)(TIM_output_channel_preload << 8); + /* Write to TIMx CCMOD2 register */ + TIMx->CCMOD2 = temp_value; +} + +/** +*\*\name TIM_Output_Channel5_Preload_Set +*\*\param TIMx: +*\*\ - TIM1 +*\*\param TIM_output_channel_preload +*\*\ - TIM_OC_PRELOAD_ENABLE +*\*\ - TIM_OC_PRELOAD_DISABLE +*\*\return none +**/ +void TIM_Output_Channel5_Preload_Set(TIM_Module* TIMx, uint16_t TIM_output_channel_preload) +{ + uint16_t temp_value = 0; + + temp_value = TIMx->CCMOD3; + /* Reset the OC1PE Bit */ + temp_value &= (uint16_t) ~((uint16_t)TIM_OC5_PRELOAD_MASK); + /* Enable or Disable the Output Compare Preload feature */ + temp_value |= TIM_output_channel_preload; + /* Write to TIMx CCMOD3 register */ + TIMx->CCMOD3 = temp_value; +} + + +/** +*\*\name TIM_Auto_Reload_Preload_Enable +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\return none +**/ +void TIM_Auto_Reload_Preload_Enable(TIM_Module* TIMx) +{ + TIMx->CTRL1 |= TIM_AR_PRELOAD_ENABLE; +} + +/** +*\*\name TIM_Auto_Reload_Preload_Disable +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\return none +**/ +void TIM_Auto_Reload_Preload_Disable(TIM_Module* TIMx) +{ + TIMx->CTRL1 &= (uint32_t) ~((uint32_t)TIM_AR_PRELOAD_ENABLE); +} + + +/** +*\*\name TIM_Update_Event_Enable +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\ - TIM6 +*\*\return none +**/ +void TIM_Update_Event_Enable(TIM_Module* TIMx) +{ + TIMx->CTRL1 &= (uint32_t) ~((uint32_t)TIM_UPDATE_EVENT_DISABLE); +} + +/** +*\*\name TIM_Update_Event_Disable +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\ - TIM6 +*\*\return none +**/ +void TIM_Update_Event_Disable(TIM_Module* TIMx) +{ + TIMx->CTRL1 |= TIM_UPDATE_EVENT_DISABLE; +} + +/** +*\*\name TIM_Update_Request_Source_Set +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\ - TIM6 +*\*\param TIM_update_source: +*\*\ - TIM_UPDATE_SRC_REGULAR Source of update is counter overflow/underflow +*\*\ - TIM_UPDATE_SRC_GLOBAL Source of update is the counter overflow/underflow +*\*\ or the setting of UG bit, or an update generation +*\*\ through the slave mode controller. +*\*\note TIM6 does note support slave mode and underflow counter +*\*\return none +**/ +void TIM_Update_Request_Source_Set(TIM_Module* TIMx, uint16_t TIM_update_source) +{ + if (TIM_update_source != TIM_UPDATE_SRC_GLOBAL) + { + /* Set the URS Bit */ + TIMx->CTRL1 |= TIM_UPRS_REGULAR; + } + else + { + /* Reset the URS Bit */ + TIMx->CTRL1 &= (uint32_t) ~((uint32_t)TIM_UPRS_REGULAR); + } +} + +/** +*\*\name TIM_Event_Generate +*\*\fun Enables or disables the preload register of auto reload register. +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\ - TIM6 +*\*\param TIM_event_source +*\*\ - TIM_EVT_SRC_UPDATE Timer update Event source +*\*\ - TIM_EVT_SRC_CC1 Timer Capture Compare 1 Event source +*\*\ - TIM_EVT_SRC_CC2 Timer Capture Compare 2 Event source +*\*\ - TIM_EVT_SRC_CC3 Timer Capture Compare 3 Event source +*\*\ - TIM_EVT_SRC_CC4 Timer Capture Compare 4 Event source +*\*\ - TIM_EVT_SRC_COM Timer COM event source +*\*\ - TIM_EVT_SRC_TRIG Timer Trigger Event source +*\*\ - TIM_EVT_SRC_BREAK Timer Break event source +*\*\return none +*\*\note TIM6 can only generate an update event. +*\*\ TIM_EVT_SRC_CC3,TIM_EVT_SRC_CC4,TIM_EVT_SRC_COM and TIM_EVT_SRC_BREAK are used only with TIM1. +**/ +void TIM_Event_Generate(TIM_Module* TIMx, uint16_t TIM_event_source) +{ + TIMx->EVTGEN = TIM_event_source; +} + +/** +*\*\name TIM_Commutation_Event_Enable +*\*\fun Enables the preload register of auto reload register. +*\*\param TIMx: +*\*\ - TIM1 +*\*\return none +**/ +void TIM_Commutation_Event_Enable(TIM_Module* TIMx) +{ + TIMx->CTRL2 |= TIM_CCUSEL_COM_AND_TRIG; +} + +/** +*\*\name TIM_Commutation_Event_Disable +*\*\fun Disables the preload register of auto reload register. +*\*\param TIMx: +*\*\ - TIM1 +*\*\return none +**/ +void TIM_Commutation_Event_Disable(TIM_Module* TIMx) +{ + TIMx->CTRL2 &= (uint32_t) ~((uint32_t)TIM_CCUSEL_MASK); +} + +/** +*\*\name TIM_Capture_Compare_Control_Preload_Enable +*\*\fun Disables the preload register of auto reload register. +*\*\param TIMx: +*\*\ - TIM1 +**/ +void TIM_Capture_Compare_Control_Preload_Enable(TIM_Module* TIMx) +{ + TIMx->CTRL2 |= TIM_CCPCTL_PRELOAD; +} + +/** +*\*\name TIM_Capture_Compare_Control_Preload_Disable +*\*\fun Disables the preload register of auto reload register. +*\*\param TIMx: +*\*\ - TIM1 +**/ +void TIM_Capture_Compare_Control_Preload_Disable(TIM_Module* TIMx) +{ + TIMx->CTRL2 &= (uint32_t) ~((uint32_t)TIM_CCPCTL_PRELOAD); +} + +/** +*\*\name TIM_Compare1_Set +*\*\fun Sets the TIMx Capture compare1 Register value +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\param compare1: +*\*\ - [0,0xffff] +**/ +void TIM_Compare1_Set(TIM_Module* TIMx, uint16_t compare1) +{ + TIMx->CCDAT1 = compare1; +} + +/** +*\*\name TIM_Compare2_Set +*\*\fun Sets the TIMx Capture compare2 Register value +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\param compare2: +*\*\ - [0,0xffff] +**/ +void TIM_Compare2_Set(TIM_Module* TIMx, uint16_t compare2) +{ + TIMx->CCDAT2 = compare2; +} + +/** +*\*\name TIM_Compare3_Set +*\*\fun Sets the TIMx Capture compare3 Register value +*\*\param TIMx: +*\*\ - TIM1 +*\*\param compare3: +*\*\ - [0,0xffff] +**/ +void TIM_Compare3_Set(TIM_Module* TIMx, uint16_t compare3) +{ + TIMx->CCDAT3 = compare3; +} + +/** +*\*\name TIM_Compare4_Set +*\*\fun Sets the TIMx Capture compare4 Register value +*\*\param TIMx: +*\*\ - TIM1 +*\*\param compare4: +*\*\ - [0,0xffff] +**/ +void TIM_Compare4_Set(TIM_Module* TIMx, uint16_t compare4) +{ + + TIMx->CCDAT4 = compare4; +} + +/** +*\*\name TIM_Compare5_Set +*\*\fun Sets the TIMx Capture compare5 Register value +*\*\param TIMx: +*\*\ - TIM1 +*\*\param compare5: +*\*\ - [0,0xffff] +**/ +void TIM_Compare5_Set(TIM_Module* TIMx, uint16_t compare5) +{ + TIMx->CCDAT5 = compare5; +} + + +/** +*\*\name TIM_Compare_Capture1_Get +*\*\fun Get the TIMx compare1 Register value +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\return uin16_t: +*\*\ - [0 , 0xffff] +**/ +uint16_t TIM_Compare_Capture1_Get(TIM_Module* TIMx) +{ + return (uint16_t)(TIMx->CCDAT1); +} + +/** +*\*\name TIM_Compare_Capture2_Get +*\*\fun Get the TIMx Compare2 Register value +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\return uin16_t: +*\*\ - [0 , 0xffff] +**/ +uint16_t TIM_Compare_Capture2_Get(TIM_Module* TIMx) +{ + return (uint16_t)(TIMx->CCDAT2); +} + +/** +*\*\name TIM_Compare_Capture3_Get +*\*\fun Get the TIMx Compare3 Register value +*\*\param TIMx: +*\*\ - TIM1 +*\*\return uin16_t: +*\*\ - [0 , 0xffff] +**/ +uint16_t TIM_Compare_Capture3_Get(TIM_Module* TIMx) +{ + return (uint16_t)(TIMx->CCDAT3); +} + +/** +*\*\name TIM_Compare_Capture4_Get +*\*\fun Get the TIMx Compare4 Register value +*\*\param TIMx: +*\*\ - TIM1 +*\*\return uin16_t: +*\*\ - [0 , 0xffff] +**/ +uint16_t TIM_Compare_Capture4_Get(TIM_Module* TIMx) +{ + return (uint16_t)(TIMx->CCDAT4); +} + +/** +*\*\name TIM_Compare_Capture5_Get +*\*\fun Get the TIMx Compare5 Register value +*\*\param TIMx: +*\*\ - TIM1 +*\*\return uin16_t: +*\*\ - [0 , 0xffff] +**/ +uint16_t TIM_Compare_Capture5_Get(TIM_Module* TIMx) +{ + return TIMx->CCDAT5; +} + + + +/** +*\*\name TIM_Trigger_Source_Select +*\*\fun Selects the Input Trigger source +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\param TIM_trigger_source +*\*\ - TIM_TRIG_SEL_IN_TR0 Internal Trigger 0 +*\*\ - TIM_TRIG_SEL_IN_TR1 Internal Trigger 1 +*\*\ - TIM_TRIG_SEL_IN_TR2 Internal Trigger 2 +*\*\ - TIM_TRIG_SEL_IN_TR3 Internal Trigger 3 +*\*\ - TIM_TRIG_SEL_TI1F_ED TI1 Edge Detector +*\*\ - TIM_TRIG_SEL_TI1FP1 Filtered Timer Input 1 +*\*\ - TIM_TRIG_SEL_TI2FP2 Filtered Timer Input 2 +*\*\ - TIM_TRIG_SEL_ETRF External Trigger input +*\*\return none +**/ +void TIM_Trigger_Source_Select(TIM_Module* TIMx, uint16_t TIM_trigger_source) +{ + uint16_t temp_value = 0; + + /* Get the TIMx SMCTRL register value */ + temp_value = TIMx->SMCTRL; + /* Reset the TS Bits */ + temp_value &= (uint16_t)(~((uint16_t)TIM_TRIG_SEL_MASK)); + /* Set the Input Trigger source */ + temp_value |= TIM_trigger_source; + /* Write to TIMx SMCTRL */ + TIMx->SMCTRL = temp_value; +} + + +/** +*\*\name Input_Channel1_Config +*\*\fun Configure the TI1 as Input. +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\param input_channel_polarity The Input Polarity. +*\*\ This parameter can be one of the following values: +*\*\ - TIM_IC_POLARITY_RISING +*\*\ - TIM_IC_POLARITY_FALLING +*\*\param input_channel_selection specifies the input to be used. +*\*\ This parameter can be one of the following values: +*\*\ - TIM_IC_SELECTION_DIRECTTI TIM Input 1 is selected to be connected to IC1. +*\*\ - TIM_IC_SELECTION_INDIRECTTI TIM Input 1 is selected to be connected to IC2. +*\*\ - TIM_IC_SELECTION_TRC TIM Input 1 is selected to be connected to TRC. +*\*\param input_channel_filter Specifies the Input Capture Filter. +*\*\ [0x00 0xF] +*\*\return none +**/ +void Input_Channel1_Config(TIM_Module* TIMx, uint16_t input_channel_polarity, + uint16_t input_channel_selection, uint16_t input_channel_filter) +{ + uint16_t temp_ccmod1 = 0; + uint32_t temp_ccen = 0; + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCEN &= (uint32_t) ~((uint32_t)TIM_CC1EN); + temp_ccmod1 = TIMx->CCMOD1; + temp_ccen = TIMx->CCEN; + /* Select the Input and set the filter */ + temp_ccmod1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_IC1_SELECTION_MASK)) & ((uint16_t) ~((uint16_t)TIM_IC1_FILTER_MASK))); + temp_ccmod1 |= (uint16_t)(input_channel_selection | (uint16_t)(input_channel_filter << (uint16_t)4)); + + if ((TIMx == TIM1) || (TIMx == TIM3)) + { + /* Select the Polarity and set the CC1E Bit */ + temp_ccen &= (uint32_t) ~((uint32_t)(TIM_CC1P)); + temp_ccen |= (uint32_t)(input_channel_polarity | (uint32_t)TIM_CC1EN); + } + else + { + /* Select the Polarity and set the CC1E Bit */ + temp_ccen &= (uint32_t) ~((uint32_t)(TIM_CC1P | TIM_CC1NP)); + temp_ccen |= (uint32_t)(input_channel_polarity | (uint32_t)TIM_CC1EN); + } + + /* Write to TIMx CCMOD1 and CCEN registers */ + TIMx->CCMOD1 = temp_ccmod1; + TIMx->CCEN = temp_ccen; +} + +/** +*\*\name Input_Channel2_Config +*\*\fun Configure the TI2 as Input. +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\param input_channel_polarity The Input Polarity. +*\*\ This parameter can be one of the following values: +*\*\ - TIM_IC_POLARITY_RISING +*\*\ - TIM_IC_POLARITY_FALLING +*\*\param input_channel_selection specifies the input to be used. +*\*\ This parameter can be one of the following values: +*\*\ - TIM_IC_SELECTION_DIRECTTI TIM Input 2 is selected to be connected to IC2. +*\*\ - TIM_IC_SELECTION_INDIRECTTI TIM Input 2 is selected to be connected to IC1. +*\*\ - TIM_IC_SELECTION_TRC TIM Input 2 is selected to be connected to TRC. +*\*\param input_channel_filter Specifies the Input Capture Filter. +*\*\ [0x00 0x0F] +*\*\return none +**/ +void Input_Channel2_Config(TIM_Module* TIMx, uint16_t input_channel_polarity, + uint16_t input_channel_selection, uint16_t input_channel_filter) +{ + uint16_t temp_ccmod1 = 0; + uint32_t temp_ccen = 0, temp_value = 0; + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCEN &= (uint32_t) ~((uint32_t)TIM_CC2EN); + temp_ccmod1 = TIMx->CCMOD1; + temp_ccen = TIMx->CCEN; + temp_value = (uint32_t)(input_channel_polarity << 4); + /* Select the Input and set the filter */ + temp_ccmod1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_IC2_SELECTION_MASK)) & ((uint16_t) ~((uint16_t)TIM_IC2_FILTER_MASK))); + temp_ccmod1 |= (uint16_t)(input_channel_filter << 12); + temp_ccmod1 |= (uint16_t)(input_channel_selection << 8); + + if ((TIMx == TIM1) || (TIMx == TIM3)) + { + /* Select the Polarity and set the CC2E Bit */ + temp_ccen &= (uint32_t) ~((uint32_t)(TIM_CC2P)); + temp_ccen |= (uint32_t)(temp_value | (uint32_t)TIM_CC2EN); + } + else + { + /* Select the Polarity and set the CC2E Bit */ + temp_ccen &= (uint32_t) ~((uint32_t)(TIM_CC2P | TIM_CC2NP)); + temp_ccen |= (uint32_t)(input_channel_polarity | (uint32_t)TIM_CC2EN); + } + + /* Write to TIMx CCMOD1 and CCEN registers */ + TIMx->CCMOD1 = temp_ccmod1; + TIMx->CCEN = temp_ccen; +} + + +/** +*\*\name Input_Channel3_Config +*\*\fun Configure the TI3 as Input. +*\*\param TIMx: +*\*\ - TIM1 +*\*\param input_channel_polarity The Input Polarity. +*\*\ This parameter can be one of the following values: +*\*\ - TIM_IC_POLARITY_RISING +*\*\ - TIM_IC_POLARITY_FALLING +*\*\param input_channel_selection specifies the input to be used. +*\*\ This parameter can be one of the following values: +*\*\ - TIM_IC_SELECTION_DIRECTTI TIM Input 3 is selected to be connected to IC3. +*\*\ - TIM_IC_SELECTION_INDIRECTTI TIM Input 3 is selected to be connected to IC4. +*\*\ - TIM_IC_SELECTION_TRC TIM Input 3 is selected to be connected to TRC. +*\*\param input_channel_filter Specifies the Input Capture Filter. +*\*\ [0x00 0x0F] +*\*\return none +**/ +void Input_Channel3_Config(TIM_Module* TIMx, uint16_t input_channel_polarity, + uint16_t input_channel_selection, uint16_t input_channel_filter) +{ + uint16_t temp_ccmod2 = 0; + uint32_t temp_ccen = 0, temp_value = 0; + /* Disable the Channel 3: Reset the CC3E Bit */ + TIMx->CCEN &= (uint32_t) ~((uint32_t)TIM_CC3EN); + temp_ccmod2 = TIMx->CCMOD2; + temp_ccen = TIMx->CCEN; + temp_value = (uint32_t)(input_channel_polarity << 8); + /* Select the Input and set the filter */ + temp_ccmod2 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_IC3_SELECTION_MASK)) & ((uint16_t) ~((uint16_t)TIM_IC3_FILTER_MASK))); + temp_ccmod2 |= (uint16_t)(input_channel_selection | (uint16_t)(input_channel_filter << (uint16_t)4)); + + if (TIMx == TIM1) + { + /* Select the Polarity and set the CC3E Bit */ + temp_ccen &= (uint32_t) ~((uint32_t)(TIM_CC3P)); + temp_ccen |= (uint32_t)(temp_value | (uint32_t)TIM_CC3EN); + } + else + { + /* Select the Polarity and set the CC3E Bit */ + temp_ccen &= (uint32_t) ~((uint32_t)(TIM_CC3P | TIM_CC3NP)); + temp_ccen |= (uint32_t)(input_channel_polarity | (uint32_t)TIM_CC3EN); + } + + /* Write to TIMx CCMOD2 and CCEN registers */ + TIMx->CCMOD2 = temp_ccmod2; + TIMx->CCEN = temp_ccen; +} + +/** +*\*\name Input_Channel4_Config +*\*\fun Configure the TI4 as Inputt. +*\*\param TIMx: +*\*\ - TIM1 +*\*\param input_channel_polarity The Input Polarity. +*\*\ This parameter can be one of the following values: +*\*\ - TIM_IC_POLARITY_RISING +*\*\ - TIM_IC_POLARITY_FALLING +*\*\param input_channel_selection specifies the input to be used. +*\*\ This parameter can be one of the following values: +*\*\ - TIM_IC_SELECTION_DIRECTTI TIM Input 4 is selected to be connected to IC4. +*\*\ - TIM_IC_SELECTION_INDIRECTTI TIM Input 4 is selected to be connected to IC3. +*\*\ - TIM_IC_SELECTION_TRC TIM Input 4 is selected to be connected to TRC. +*\*\param input_channel_filter Specifies the Input Capture Filter. +*\*\ [0x00 0x0F] +*\*\return none +**/ +void Input_Channel4_Config(TIM_Module* TIMx, uint16_t input_channel_polarity, + uint16_t input_channel_selection, uint16_t input_channel_filter) +{ + uint16_t temp_ccmod2 = 0; + uint32_t temp_ccen = 0, temp_value = 0; + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCEN &= (uint32_t) ~((uint32_t)TIM_CC4EN); + temp_ccmod2 = TIMx->CCMOD2; + temp_ccen = TIMx->CCEN; + temp_value = (uint32_t)(input_channel_polarity << 12); + /* Select the Input and set the filter */ + temp_ccmod2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_IC4_SELECTION_MASK) & ((uint16_t) ~((uint16_t)TIM_IC4_FILTER_MASK))); + temp_ccmod2 |= (uint16_t)(input_channel_selection << 8); + temp_ccmod2 |= (uint16_t)(input_channel_filter << 12); + + if (TIMx == TIM1) + { + /* Select the Polarity and set the CC4E Bit */ + temp_ccen &= (uint32_t) ~((uint32_t)(TIM_CC4P)); + temp_ccen |= (uint32_t)(temp_value | (uint32_t)TIM_CC4EN); + } + else + { + /* Select the Polarity and set the CC4E Bit */ + temp_ccen &= (uint32_t) ~((uint32_t)(TIM_CC4P)); + temp_ccen |= (uint32_t)(input_channel_polarity | (uint32_t)TIM_CC4EN); + } + /* Write to TIMx CCMOD2 and CCEN registers */ + TIMx->CCMOD2 = temp_ccmod2; + TIMx->CCEN = temp_ccen; +} + +/** +*\*\name TIM_External_Trigger_Filter_Set +*\*\fun Configures the filter of TIMx External Trigger. +*\*\param TIMx +*\*\ - TIM1 +*\*\ - TIM3 +*\*\param external_trigger_filter +*\*\ - [0x0,0xF] +*\*\return none +**/ +void TIM_External_Trigger_Filter_Set(TIM_Module* TIMx, + uint16_t external_trigger_filter) +{ + /* Reset the ETRPSC Bits */ + uint16_t temp_value = TIMx->SMCTRL; + temp_value &= (uint16_t)(~((uint16_t)TIM_EXT_TRIG_FILTER_MASK)); + /* Set the Prescaler, the Filter value and the Polarity */ + temp_value |= (uint16_t)(external_trigger_filter << (uint16_t)8); + TIMx->SMCTRL = temp_value; +} + + +/** +*\*\name TIM_External_Trigger_Prescaler_Set +*\*\fun Configures the prescaler of External Trigger (ETR). +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\param external_trigger_prescaler +*\*\ - TIM_EXT_TRG_PSC_OFF ETRP Prescaler OFF. +*\*\ - TIM_EXT_TRG_PSC_DIV2 ETRP frequency divided by 2. +*\*\ - TIM_EXT_TRG_PSC_DIV4 ETRP frequency divided by 4. +*\*\ - TIM_EXT_TRG_PSC_DIV8 ETRP frequency divided by 8. +*\*\return - none +**/ +void TIM_External_Trigger_Prescaler_Set(TIM_Module* TIMx, + uint16_t external_trigger_prescaler) +{ + /* Reset the ETRPSC Bits */ + uint16_t temp_value = TIMx->SMCTRL; + temp_value &= (uint16_t)(~((uint16_t)TIM_EXT_TRG_PSC_MASK)); + /* Set the Prescaler, the Filter value and the Polarity */ + temp_value |= (uint16_t)(external_trigger_prescaler); + TIMx->SMCTRL = temp_value; +} + +/** +*\*\name TIM_External_Trigger_Polarity_Set +*\*\\fun Configures the polarity of TIMx External Trigger. +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\param external_trigger_polarity T +*\*\ - TIM_EXT_TRIG_POLARITY_INVERTED active low or falling edge active. +*\*\ - TIM_EXT_TRIG_POLARITY_NONINVERTED active high or rising edge active. +*\*\return none +**/ +void TIM_External_Trigger_Polarity_Set(TIM_Module* TIMx, + uint16_t external_trigger_polarity) +{ + if(external_trigger_polarity == TIM_EXT_TRIG_POLARITY_INVERTED) + { + TIMx->SMCTRL |= TIM_EXT_TRIG_POLARITY_INVERTED; + } + else + { + TIMx->SMCTRL &= (uint16_t)(~((uint16_t)TIM_EXT_TRIG_POLARITY_INVERTED)); + } +} + +/** +*\*\name TIM_Clock_Division_Set +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\param clock_division + * This parameter can be one of the following value: +*\*\ - TIM_CLK_DIV1 TDTS = Tck_tim +*\*\ - TIM_CLK_DIV2 TDTS = 2*Tck_tim +*\*\ - TIM_CLK_DIV4 TDTS = 4*Tck_tim +*\*\return none +*\*\note +*\*\ - not for TIM6 +**/ +void TIM_Clock_Division_Set(TIM_Module* TIMx, uint16_t clock_division) +{ + TIMx->CTRL1 &= (uint32_t) ~((uint32_t)TIM_CLK_DIV_MASK); + /* Set the CKD value */ + TIMx->CTRL1 |= clock_division; +} + + +/** +*\*\name TIM_Internal_Clock_Set. +*\*\fun Configures the TIMx internal Clock +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\return none +**/ +void TIM_Internal_Clock_Set(TIM_Module* TIMx) +{ + /* Disable slave mode to clock the prescaler directly with the internal clock */ + TIMx->SMCTRL &= (uint16_t)(~((uint16_t)TIM_SLAVE_MODE_MASK)); +} + + +/** +*\*\name TIM_Input_Capture1_Prescaler_Set +*\*\fun Sets the TIMx Input Capture 1 prescaler. +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\param TIM_input_capture_prescaler +*\*\ - TIM_IC_PSC_DIV1 no prescaler +*\*\ - TIM_IC_PSC_DIV2 capture is done once every 2 events +*\*\ - TIM_IC_PSC_DIV4 capture is done once every 4 events +*\*\ - TIM_IC_PSC_DIV8 capture is done once every 8 events +*\*\return none +**/ +void TIM_Input_Capture1_Prescaler_Set(TIM_Module* TIMx, uint16_t TIM_input_capture_prescaler) +{ + TIMx->CCMOD1 &= (uint16_t) ~((uint16_t)TIM_IC1_PSC_MASK); + /* Set the IC1PSC value */ + TIMx->CCMOD1 |= TIM_input_capture_prescaler; +} + +/** +*\*\name TIM_Input_Capture2_Prescaler_Set +*\*\fun Sets the TIMx Input Capture 2 prescaler. +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\param TIM_input_capture_prescaler +*\*\ - TIM_IC_PSC_DIV1 no prescaler +*\*\ - TIM_IC_PSC_DIV2 capture is done once every 2 events +*\*\ - TIM_IC_PSC_DIV4 capture is done once every 4 events +*\*\ - TIM_IC_PSC_DIV8 capture is done once every 8 events +*\*\return none +**/ +void TIM_Input_Capture2_Prescaler_Set(TIM_Module* TIMx, uint16_t TIM_input_capture_prescaler) +{ + TIMx->CCMOD1 &= (uint16_t) ~((uint16_t)TIM_IC2_PSC_MASK); + /* Set the IC1PSC value */ + TIMx->CCMOD1 |= (uint16_t)(TIM_input_capture_prescaler << 8); +} + +/** +*\*\name TIM_Input_Capture3_Prescaler_Set +*\*\fun Sets the TIMx Input Capture 3 prescaler. +*\*\param TIMx: +*\*\ - TIM1 +*\*\param TIM_input_capture_prescaler +*\*\ - TIM_IC_PSC_DIV1 no prescaler +*\*\ - TIM_IC_PSC_DIV2 capture is done once every 2 events +*\*\ - TIM_IC_PSC_DIV4 capture is done once every 4 events +*\*\ - TIM_IC_PSC_DIV8 capture is done once every 8 events +*\*\return none +**/ +void TIM_Input_Capture3_Prescaler_Set(TIM_Module* TIMx, uint16_t TIM_input_capture_prescaler) +{ + TIMx->CCMOD2 &= (uint16_t) ~((uint16_t)TIM_IC3_PSC_MASK); + /* Set the IC1PSC value */ + TIMx->CCMOD2 |= TIM_input_capture_prescaler; +} + +/** +*\*\name TIM_Input_Capture4_Prescaler_Set +*\*\fun Sets the TIMx Input Capture 4 prescaler. +*\*\param TIMx: +*\*\ - TIM1 +*\*\param TIM_input_capture_prescaler +*\*\ - TIM_IC_PSC_DIV1 no prescaler +*\*\ - TIM_IC_PSC_DIV2 capture is done once every 2 events +*\*\ - TIM_IC_PSC_DIV4 capture is done once every 4 events +*\*\ - TIM_IC_PSC_DIV8 capture is done once every 8 events +*\*\return none +**/ +void TIM_Input_Capture4_Prescaler_Set(TIM_Module* TIMx, uint16_t TIM_input_capture_prescaler) +{ + TIMx->CCMOD2 &= (uint16_t) ~((uint16_t)TIM_IC4_PSC_MASK); + /* Set the IC1PSC value */ + TIMx->CCMOD2 |= (TIM_input_capture_prescaler << 8); +} + +/** +*\*\name TIM_Internal_Trig_To_Ext_Set. +*\*\fun Configures the TIMx Internal Trigger as External Clock +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\param input_trigger_source: +*\*\ - TIM_TRIG_SEL_IN_TR0 Internal Trigger 0 +*\*\ - TIM_TRIG_SEL_IN_TR1 Internal Trigger 1 +*\*\ - TIM_TRIG_SEL_IN_TR2 Internal Trigger 2 +*\*\ - TIM_TRIG_SEL_IN_TR3 Internal Trigger 3 +*\*\return none +**/ +void TIM_Internal_Trig_To_Ext_Set(TIM_Module* TIMx, uint16_t input_trigger_source) +{ + /* Select the Internal Trigger */ + TIM_Trigger_Source_Select(TIMx, input_trigger_source); + + /* Select the External clock mode1 */ + TIMx->SMCTRL |= TIM_SLAVE_MODE_EXT1; +} + + +/** +*\*\name TIM_Trigger_As_External_Clock. +*\*\fun Configures the TIMx Trigger as External Clock +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\param external_clock_source +*\*\ - TIM_EXT_CLK_SRC_TI1ED TI1 Edge Detector +*\*\ - TIM_EXT_CLK_SRC_TI1 Filtered Timer Input 1 +*\*\ - TIM_EXT_CLK_SRC_TI2 Filtered Timer Input 2 +*\*\param input_channel_polarity specifies the TIx Polarity. +*\*\ - TIM_IC_POLARITY_RISING +*\*\ - TIM_IC_POLARITY_FALLING +*\*\param input_channel_filter +*\*\ - [0x0 0xF] +*\*\return none +**/ +void TIM_Trigger_As_External_Clock(TIM_Module* TIMx, uint16_t external_clock_source, + uint16_t input_channel_polarity, + uint16_t input_channel_filter) +{ + /* Configure the Timer Input Clock Source */ + if (external_clock_source == TIM_EXT_CLK_SRC_TI2) + { + Input_Channel2_Config(TIMx, input_channel_polarity, TIM_IC_SELECTION_DIRECTTI, input_channel_filter); + } + else + { + Input_Channel1_Config(TIMx, input_channel_polarity, TIM_IC_SELECTION_DIRECTTI, input_channel_filter); + } + /* Select the Trigger source */ + TIM_Trigger_Source_Select(TIMx, external_clock_source); + /* Select the External clock mode1 */ + TIMx->SMCTRL |= TIM_SLAVE_MODE_EXT1; +} + +/** +*\*\name TIM_External_Clock_Mode1_Set. +*\*\fun Configures the External clock Mode1 +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\param external_trigger_prescaler +*\*\ - TIM_EXT_TRG_PSC_OFF ETRP Prescaler OFF. +*\*\ - TIM_EXT_TRG_PSC_DIV2 ETRP frequency divided by 2. +*\*\ - TIM_EXT_TRG_PSC_DIV4 ETRP frequency divided by 4. +*\*\ - TIM_EXT_TRG_PSC_DIV8 ETRP frequency divided by 8. + *\*\param external_trigger_polarity The external Trigger Polarity. +*\*\ - TIM_EXT_TRIG_POLARITY_INVERTED active low or falling edge active. +*\*\ - TIM_EXT_TRIG_POLARITY_NONINVERTED active high or rising edge active. +*\*\param external_trigger_filter +*\*\ - [0x0 0xF] +*\*\return none +**/ +void TIM_External_Clock_Mode1_Set(TIM_Module* TIMx, uint16_t external_trigger_prescaler, + uint16_t external_trigger_polarity, + uint16_t external_trigger_filter) +{ + uint16_t temp_value = 0; + + TIM_External_Trigger_Filter_Set(TIMx, external_trigger_filter); + TIM_External_Trigger_Polarity_Set(TIMx, external_trigger_polarity); + TIM_External_Trigger_Prescaler_Set(TIMx, external_trigger_prescaler); + + /* Get the TIMx SMCTRL register value */ + temp_value = TIMx->SMCTRL; + /* Reset the SMS Bits */ + temp_value &= (uint16_t)(~((uint16_t)TIM_SLAVE_MODE_MASK)); + /* Select the External clock mode1 */ + temp_value |= TIM_SLAVE_MODE_EXT1; + /* Select the Trigger selection : ETRF */ + temp_value &= (uint16_t)(~((uint16_t)TIM_TRIG_SEL_MASK)); + temp_value |= TIM_TRIG_SEL_ETRF; + /* Write to TIMx SMCTRL */ + TIMx->SMCTRL = temp_value; +} + +/** +*\*\name TIM_ConfigExtClkMode2. +*\*\fun Configures the External clock Mode1 +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\param external_trigger_prescaler +*\*\ - TIM_EXT_TRG_PSC_OFF ETRP Prescaler OFF. +*\*\ - TIM_EXT_TRG_PSC_DIV2 ETRP frequency divided by 2. +*\*\ - TIM_EXT_TRG_PSC_DIV4 ETRP frequency divided by 4. +*\*\ - TIM_EXT_TRG_PSC_DIV8 ETRP frequency divided by 8. +*\*\param external_trigger_polarity The external Trigger Polarity. +*\*\ - TIM_EXT_TRIG_POLARITY_INVERTED active low or falling edge active. +*\*\ - TIM_EXT_TRIG_POLARITY_NONINVERTED active high or rising edge active. +*\*\param external_trigger_filter +*\*\ - [0x0 0xF] +*\*\return none +**/ +void TIM_External_Clock_Mode2_Set(TIM_Module* TIMx, + uint16_t external_trigger_prescaler, + uint16_t external_trigger_polarity, + uint16_t external_trigger_filter) +{ + TIM_External_Trigger_Filter_Set(TIMx, external_trigger_filter); + + TIM_External_Trigger_Polarity_Set(TIMx, external_trigger_polarity); + + TIM_External_Trigger_Prescaler_Set(TIMx, external_trigger_prescaler); + + TIMx->SMCTRL |= TIM_EXT_CLOCK_MODE2_ENABLE; + +} + +/** +*\*\name TIM_Slave_Mode_Select. +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\param TIM_slave_mode: +*\*\ - TIM_SLAVE_MODE_RESET Rising edge of the selected trigger signal (TRGI) re-initializes +*\*\ the counter and triggers an update of the registers. +*\*\ - TIM_SLAVE_MODE_GATED The counter clock is enabled when the trigger signal (TRGI) is high. +*\*\ - TIM_SLAVE_MODE_TRIG The counter starts at a rising edge of the trigger TRGI. +*\*\ - TIM_SLAVE_MODE_EXT1 Rising edges of the selected trigger (TRGI) clock the counter. +*\*\return none +**/ +void TIM_Slave_Mode_Select(TIM_Module* TIMx, uint16_t TIM_slave_mode) +{ + /* Reset the SMS Bits */ + TIMx->SMCTRL &= (uint16_t) ~((uint16_t)TIM_SLAVE_MODE_MASK); + /* Select the Slave Mode */ + TIMx->SMCTRL |= TIM_slave_mode; +} + +/** +*\*\name TIM_Break_And_Dead_Time_Set. +*\*\fun Initializes the TIM break and dead time register +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\param TIM_slave_mode: +*\*\ - TIM_MASTER_SLAVE_MODE_ENABLE synchronization between the current timer +*\*\ and its slaves (through TRGO). +*\*\ - TIM_MASTER_SLAVE_MODE_DISABLE No action +*\*\return none +**/ +void TIM_Master_Slave_Mode_Set(TIM_Module* TIMx, uint16_t TIM_master_slave_mode) +{ + /* Reset the MSM Bit */ + TIMx->SMCTRL &= (uint16_t) ~((uint16_t)TIM_MASTER_SLAVE_MODE_MASK); + + /* Set or Reset the MSM Bit */ + TIMx->SMCTRL |= TIM_master_slave_mode; +} + + + +/** +*\*\name TIM_Output_Trigger_Select. +*\*\fun Initializes the TIM break and dead time register +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\param TIM_TRGOSource +*\*\ For all TIMx: +*\*\ - TIM_TRGO_SRC_RESET The UG bit in the TIM_EVTGEN register is used as the trigger output (TRGO). +*\*\ - TIM_TRGO_SRC_ENABLE The Counter Enable CEN is used as the trigger output (TRGO). +*\*\ - TIM_TRGO_SRC_UPDATE The update event is selected as the trigger output (TRGO). +*\*\ For TIM1: +*\*\ - TIM_TRGO_SRC_OC1 The trigger output sends a positive pulse when the CC1IF flag +*\*\ is to be set, as soon as a capture or compare match occurs (TRGO). +*\*\ - TIM_TRGO_SRC_OC1REF OC1REF signal is used as the trigger output (TRGO). +*\*\ - TIM_TRGO_SRC_OC2REF OC2REF signal is used as the trigger output (TRGO). +*\*\ - TIM_TRGO_SRC_OC3REF OC3REF signal is used as the trigger output (TRGO). +*\*\ - TIM_TRGO_SRC_OC4REF OC4REF signal is used as the trigger output (TRGO). +*\*\ For TIM3: +*\*\ - TIM_TRGO_SRC_OC1 The trigger output sends a positive pulse when the CC1IF flag +*\*\ is to be set, as soon as a capture or compare match occurs (TRGO). +*\*\ - TIM_TRGO_SRC_OC1REF OC1REF signal is used as the trigger output (TRGO). +*\*\ - TIM_TRGO_SRC_OC2REF OC2REF signal is used as the trigger output (TRGO). +*\*\return none +**/ +void TIM_Output_Trigger_Select(TIM_Module* TIMx, uint16_t TIM_trigger_output_source) +{ + /* Reset the MMS Bits */ + TIMx->CTRL2 &= (uint32_t) ~((uint32_t)TIM_TRGO_SRC_MASK); + /* Select the TRGO source */ + TIMx->CTRL2 |= TIM_trigger_output_source; +} + + + + + +/** +*\*\name TIM_One_Pulse_Mode_Select. +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\param TIM_slave_mode: +*\*\ - TIM_OPMODE_SINGLE +*\*\ - TIM_OPMODE_REPET +*\*\return none +**/ +void TIM_One_Pulse_Mode_Select(TIM_Module* TIMx, uint16_t TIM_one_pulse_mode) +{ + /* Reset the OPM Bit */ + TIMx->CTRL1 &= (uint32_t) ~((uint32_t)TIM_OPMODE_MASK); + /* Configure the OPM Mode */ + TIMx->CTRL1 |= TIM_one_pulse_mode; +} + +/** +*\*name TIM_Input_Struct_Initialize +*\*\fun Initialize the TIM_ICInitStruct +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\param TIM_ICInitStruct +*\*\ - refer to the definition of TIM_ICInitType +*\*\return none +**/ +void TIM_Input_Struct_Initialize(TIM_ICInitType* TIM_ICInitStruct) +{ + /* Set the default configuration */ + TIM_ICInitStruct->IcPolarity = TIM_IC_POLARITY_RISING; + TIM_ICInitStruct->IcSelection = TIM_IC_SELECTION_DIRECTTI; + TIM_ICInitStruct->IcPrescaler = TIM_IC_PSC_DIV1; + TIM_ICInitStruct->IcFilter = 0x00; +} + +/** +*\*\name TIM_Input_Channel_Initialize +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\param TIM_ICInitStruct +*\* - refer to the definition of TIM_ICInitType +*\*\return none +**/ +void TIM_Input_Channel_Initialize(TIM_Module* TIMx, TIM_ICInitType* TIM_ICInitStruct) +{ + if (TIM_ICInitStruct->Channel == TIM_CH_1) + { + /* TI1 Configuration */ + Input_Channel1_Config(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter); + /* Set the Input Capture Prescaler value */ + TIM_Input_Capture1_Prescaler_Set(TIMx, TIM_ICInitStruct->IcPrescaler); + } + else if (TIM_ICInitStruct->Channel == TIM_CH_2) + { + /* TI2 Configuration */ + Input_Channel2_Config(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter); + /* Set the Input Capture Prescaler value */ + TIM_Input_Capture2_Prescaler_Set(TIMx, TIM_ICInitStruct->IcPrescaler); + } + else if (TIM_ICInitStruct->Channel == TIM_CH_3) + { + /* TI3 Configuration */ + Input_Channel3_Config(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter); + /* Set the Input Capture Prescaler value */ + TIM_Input_Capture3_Prescaler_Set(TIMx, TIM_ICInitStruct->IcPrescaler); + } + else + { + /* TI4 Configuration */ + Input_Channel4_Config(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter); + /* Set the Input Capture Prescaler value */ + TIM_Input_Capture4_Prescaler_Set(TIMx, TIM_ICInitStruct->IcPrescaler); + } +} + + +/** +*\*\name TIM_PWM_Input_Channel_Operation +*\*\fun Configures the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct to measure an external PWM signal. +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\param TIM_ICInitStruct +*\* - refer to the definition of TIM_ICInitType +*\*\return none +*\*\note - TIM3 does not support channel 6,channel 5,channel 4 and channel 3 +**/ +void TIM_PWM_Input_Channel_Config(TIM_Module* TIMx, TIM_ICInitType* TIM_ICInitStruct) +{ + uint16_t input_channel_opposite_polarity = TIM_IC_POLARITY_RISING; + uint16_t input_channel_opposite_selection = TIM_IC_SELECTION_DIRECTTI; + /* Select the Opposite Input Polarity */ + if (TIM_ICInitStruct->IcPolarity == TIM_IC_POLARITY_RISING) + { + input_channel_opposite_polarity = TIM_IC_POLARITY_FALLING; + } + else + { + input_channel_opposite_polarity = TIM_IC_POLARITY_RISING; + } + /* Select the Opposite Input */ + if (TIM_ICInitStruct->IcSelection == TIM_IC_SELECTION_DIRECTTI) + { + input_channel_opposite_selection = TIM_IC_SELECTION_INDIRECTTI; + } + else + { + input_channel_opposite_selection = TIM_IC_SELECTION_DIRECTTI; + } + if (TIM_ICInitStruct->Channel == TIM_CH_1) + { + /* TI1 Configuration */ + Input_Channel1_Config(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter); + /* Set the Input Capture Prescaler value */ + TIM_Input_Capture1_Prescaler_Set(TIMx, TIM_ICInitStruct->IcPrescaler); + /* TI2 Configuration */ + Input_Channel2_Config(TIMx, input_channel_opposite_polarity, input_channel_opposite_selection, TIM_ICInitStruct->IcFilter); + /* Set the Input Capture Prescaler value */ + TIM_Input_Capture2_Prescaler_Set(TIMx, TIM_ICInitStruct->IcPrescaler); + } + else + { + /* TI2 Configuration */ + Input_Channel2_Config(TIMx, TIM_ICInitStruct->IcPolarity, TIM_ICInitStruct->IcSelection, TIM_ICInitStruct->IcFilter); + /* Set the Input Capture Prescaler value */ + TIM_Input_Capture2_Prescaler_Set(TIMx, TIM_ICInitStruct->IcPrescaler); + /* TI1 Configuration */ + Input_Channel1_Config(TIMx, input_channel_opposite_polarity, input_channel_opposite_selection, TIM_ICInitStruct->IcFilter); + /* Set the Input Capture Prescaler value */ + TIM_Input_Capture1_Prescaler_Set(TIMx, TIM_ICInitStruct->IcPrescaler); + } +} + + + +/** +*\*\name TIM_Output_Channel_Polarity_Set. +*\*\fun set the polarity of TIMx channel +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\param output_channel_polarity: +**\ - TIM_OC_POLARITY_LOW +**\ - TIM_OC_POLARITY_HIGH +*\*\param channel: +**\ - TIM_CH_1 +**\ - TIM_CH_2 +**\ - TIM_CH_3 +**\ - TIM_CH_4 +**\ - TIM_CH_5 +*\*\return none +*\*\note - TIM3 does not support channel 6,channel 5,channel 4 and channel 3 +**/ +void TIM_Output_Channel_Polarity_Set(TIM_Module* TIMx, uint32_t output_channel_polarity, uint16_t channel) +{ + uint32_t temp_value = TIMx->CCEN; + /* Clear the CCxEN bit */ + temp_value &= (uint32_t)(~(uint32_t)(TIM_OC_POLARITY_MASK << channel)); + + /* Set the CCxEN bit */ + temp_value |= (uint32_t)(output_channel_polarity << channel); + + /* Write to TIMx CCEN register */ + TIMx->CCEN = temp_value; +} + +/** +*\*\name TIM_Output_Channel_N_Polarity_Set. +*\*\fun set the mode of polarity of TIMx channel +*\*\param TIMx: +*\*\ - TIM1 +*\*\param output_channel_N_polarity: +**\ - TIM_OCN_POLARITY_LOW +**\ - TIM_OCN_POLARITY_HIGH +*\*\param channel: +**\ - TIM_CH_1 +**\ - TIM_CH_2 +**\ - TIM_CH_3 +*\*\return none +*\*\note This function is only for TIM1 +**/ +void TIM_Output_Channel_N_Polarity_Set(TIM_Module* TIMx, uint32_t output_channel_N_polarity, uint16_t channel) +{ + uint32_t temp_value = TIMx->CCEN; + /* Clear the CCxEN bit */ + temp_value &= (uint32_t)(~(uint32_t)(TIM_OCN_POLARITY_MASK << channel)); + + /* Set the CCxEN bit */ + temp_value |= (uint32_t)(output_channel_N_polarity << channel); + + TIMx->CCEN = temp_value; +} + +/** +*\*\name TIM_Capture_Compare_Ch_Enable. +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\param channel: +**\ - TIM_CH_1 +**\ - TIM_CH_2 +**\ - TIM_CH_3 +**\ - TIM_CH_4 +**\ - TIM_CH_5 +*\*\return none +*\*\note - TIM3 does not support channel 6,channel 5,channel 4 and channel 3 +**/ +void TIM_Capture_Compare_Ch_Enable(TIM_Module* TIMx, uint16_t channel) +{ + TIMx->CCEN |= (uint32_t)(TIM_CAP_CMP_ENABLE << channel); +} + +/** +*\*\name TIM_Capture_Compare_Ch_Disable. +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\param channel: +**\ - TIM_CH_1 +**\ - TIM_CH_2 +**\ - TIM_CH_3 +**\ - TIM_CH_4 +**\ - TIM_CH_5 +*\*\return none +*\*\note - TIM3 does not support channel 6,channel 5,channel 4 and channel 3 +**/ +void TIM_Capture_Compare_Ch_Disable(TIM_Module* TIMx, uint16_t channel) +{ + TIMx->CCEN &= (uint32_t)(~(TIM_CAP_CMP_ENABLE << channel)); +} + +/** +*\*\name TIM_Capture_Compare_Ch_N_Enable. +*\*\param TIMx: +*\*\ - TIM1 +*\*\param channel: +**\ - TIM_CH_1 +**\ - TIM_CH_2 +**\ - TIM_CH_3 +*\*\return none +**/ +void TIM_Capture_Compare_Ch_N_Enable(TIM_Module* TIMx, uint16_t channel) +{ + TIMx->CCEN |= (uint32_t)(TIM_CAP_CMP_N_ENABLE << channel); +} + +/** +*\*\name TIM_Capture_Compare_Ch_N_Disable. +*\*\param TIMx: +*\*\ - TIM1 +*\*\param channel: +**\ - TIM_CH_1 +**\ - TIM_CH_2 +**\ - TIM_CH_3 +*\*\return none +**/ +void TIM_Capture_Compare_Ch_N_Disable(TIM_Module* TIMx, uint16_t channel) +{ + TIMx->CCEN &= (uint32_t)(~(TIM_CAP_CMP_N_ENABLE << channel)); +} + +/** +*\*\name TIM_CCEN_Status_Get +*\*\fun Checks whether the specified TIM flag is set or not. +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\param TIM_CCEN: +*\*\ - TIM_CC1EN Bit +*\*\ - TIM_CC1NEN Bit +*\*\ - TIM_CC2EN Bit +*\*\ - TIM_CC2NEN Bit +*\*\ - TIM_CC3EN Bit +*\*\ - TIM_CC3NEN Bit +*\*\ - TIM_CC4EN Bit +*\*\ - TIM_CC5EN Bit +*\*\return: +*\*\ - SET +*\*\ - RESET +*\*\note： +*\*\ - TIM_CC1NEN TIM_CC2NEN TIM_CC3EN TIM_CC3NEN TIM_CC4EN TIM_CC5EN is used only with TIM1. +**/ +FlagStatus TIM_CCEN_Status_Get(TIM_Module* TIMx, uint32_t TIM_CCEN) +{ + if ((TIMx->CCEN & TIM_CCEN) != (uint32_t)RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/** +*\*\name TIM_Output_Channel_Mode_Set. +*\*\fun set the mode of output channel of TIMx +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\param output_channel_mode: +*\*\ - TIM_OCMODE_TIMING +*\*\ - TIM_OCMODE_ACTIVE +*\*\ - TIM_OCMODE_TOGGLE +*\*\ - TIM_OCMODE_PWM1 +*\*\ - TIM_OCMODE_PWM2 +*\*\ - TIM_FORCED_ACTION_ACTIVE +*\*\ - TIM_FORCED_ACTION_INACTIVE +*\*\param channel: +**\ - For TIM1: +**\ - TIM_CH_1 +**\ - TIM_CH_2 +**\ - TIM_CH_3 +**\ - TIM_CH_4 +**\ - For TIM3: +**\ - TIM_CH_1 +**\ - TIM_CH_2 +*\*\return none +*\*\note - This function disables the selected channel before changing the Output Compare Mode. +*\*\ User has to enable this channel using TIM_Capture_Compare_Ch_Enable,TIM_Capture_Compare_Ch_N_Enable functions. +**/ +void TIM_Output_Channel_Mode_Set(TIM_Module* TIMx, uint32_t output_channel_mode, uint16_t channel) +{ + uint32_t temp = 0; + uint16_t temp1 = 0; + + temp = (uint32_t)TIMx; + temp += CAPCMPMOD_OFFSET; + + temp1 = CAPCMPEN_CCE_SET << (uint16_t)channel; + + /* Disable the channel: Reset the CCxE Bit */ + TIMx->CCEN &= (uint16_t)~temp1; + + if ((channel == TIM_CH_1) || (channel == TIM_CH_3)) + { + temp += (channel >> 1); + + /* Reset the OCxM bits in the CCMRx register */ + *(__IO uint32_t*)temp &= (uint32_t) ~((uint32_t)TIM_OC1MODE_MASK); + + /* Configure the OCxM bits in the CCMRx register */ + *(__IO uint32_t*)temp |= output_channel_mode; + } + else + { + temp += (uint16_t)(channel - (uint16_t)4) >> (uint16_t)1; + + /* Reset the OCxM bits in the CCMRx register */ + *(__IO uint32_t*)temp &= (uint32_t) ~((uint32_t)TIM_OC2MODE_MASK); + + /* Configure the OCxM bits in the CCMRx register */ + *(__IO uint32_t*)temp |= (uint16_t)(output_channel_mode << 8); + } +} + +/** +*\*\name TIM_Forced_Output_Channel1_Set. +*\*\fun set the mode of output channel of TIMx +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\param TIM_forced_action: +*\*\ - TIM_FORCED_ACTION_ACTIVE Force active level on OC1REF +*\*\ - TIM_FORCED_ACTION_INACTIVE Force inactive level on OC1REF. +*\*\return none +**/ +void TIM_Forced_Output_Channel1_Set(TIM_Module* TIMx, uint16_t TIM_forced_action) +{ + uint16_t temp_value = 0; + /* Check the parameters */ + temp_value = TIMx->CCMOD1; + /* Reset the OC1M Bits */ + temp_value &= (uint16_t) ~((uint16_t)TIM_OC1MODE_MASK); + /* Configure The Forced output Mode */ + temp_value |= TIM_forced_action; + /* Write to TIMx CCMOD1 register */ + TIMx->CCMOD1 = temp_value; +} + +/** +*\*\name TIM_Output_Channe2_Mode_Set. +*\*\fun set the mode of output channe2 of TIMx +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\param TIM_forced_action: +*\*\ - TIM_FORCED_ACTION_ACTIVE Force active level on OC2REF +*\*\ - TIM_FORCED_ACTION_INACTIVE Force inactive level on OC2REF. +*\*\return none +**/ +void TIM_Forced_Output_Channel2_Set(TIM_Module* TIMx, uint16_t TIM_forced_action) +{ + uint16_t temp_value = 0; + /* Check the parameters */ + temp_value = TIMx->CCMOD1; + /* Reset the OC1M Bits */ + temp_value &= (uint16_t) ~((uint16_t)TIM_OC2MODE_MASK); + /* Configure The Forced output Mode */ + temp_value |= (uint16_t)(TIM_forced_action << 8); + /* Write to TIMx CCMOD1 register */ + TIMx->CCMOD1 = temp_value; +} + +/** +*\*\name TIM_Output_Channe3_Mode_Set. +*\*\fun set the mode of output channe3 of TIMx +*\*\param TIMx: +*\*\ - TIM1 +*\*\param TIM_forced_action: +*\*\ - TIM_FORCED_ACTION_ACTIVE Force active level on OC3REF +*\*\ - TIM_FORCED_ACTION_INACTIVE Force inactive level on OC3REF. +*\*\return none +**/ +void TIM_Forced_Output_Channel3_Set(TIM_Module* TIMx, uint16_t TIM_forced_action) +{ + uint16_t temp_value = 0; + /* Check the parameters */ + temp_value = TIMx->CCMOD2; + /* Reset the OC1M Bits */ + temp_value &= (uint16_t) ~((uint16_t)TIM_OC3MODE_MASK); + /* Configure The Forced output Mode */ + temp_value |= TIM_forced_action; + /* Write to TIMx CCMOD1 register */ + TIMx->CCMOD2 = temp_value; +} + +/** +*\*\name TIM_Output_Channe4_Mode_Set. +*\*\fun set the mode of output channe4 of TIMx +*\*\param TIMx: +*\*\ - TIM1 +*\*\param TIM_forced_action: +*\*\ - TIM_FORCED_ACTION_ACTIVE Force active level on OC4REF +*\*\ - TIM_FORCED_ACTION_INACTIVE Force inactive level on OC4REF. +*\*\return none +**/ +void TIM_Forced_Output_Channel4_Set(TIM_Module* TIMx, uint16_t TIM_forced_action) +{ + uint16_t temp_value = 0; + /* Check the parameters */ + temp_value = TIMx->CCMOD2; + /* Reset the OC1M Bits */ + temp_value &= (uint16_t) ~((uint16_t)TIM_OC4MODE_MASK); + /* Configure The Forced output Mode */ + temp_value |= (uint16_t)(TIM_forced_action << 8); + /* Write to TIMx CCMOD1 register */ + TIMx->CCMOD2 = temp_value; +} + +/** +*\*\name TIM_Output_Channe5_Mode_Set. +*\*\fun set the mode of output channe5 of TIMx +*\*\param TIMx: +*\*\ - TIM1 +*\*\param TIM_forced_action: +*\*\ - TIM_FORCED_ACTION_ACTIVE Force active level on OC5REF +*\*\ - TIM_FORCED_ACTION_INACTIVE Force inactive level on OC5REF. +*\*\return none +**/ +void TIM_Forced_Output_Channel5_Set(TIM_Module* TIMx, uint16_t TIM_forced_action) +{ + uint16_t temp_value = 0; + /* Check the parameters */ + temp_value = TIMx->CCMOD3; + /* Reset the OC1M Bits */ + temp_value &= (uint16_t) ~((uint16_t)TIM_OC5MODE_MASK); + /* Configure The Forced output Mode */ + temp_value |= TIM_forced_action; + /* Write to TIMx CCMOD3 register */ + TIMx->CCMOD3 = temp_value; +} + + +/** +*\*\name TIM_Output_Channel1_Fast_Set +*\*\fun Initializes the TIM break and dead time register +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\param TIM_output_channel_fast: +*\*\ - TIM_OC_FAST_ENABLE TIM Output fast enable +*\*\ - TIM_OC_FAST_DISABLE TIM Output fast disable +*\*\return none +**/ +void TIM_Output_Channel1_Fast_Set(TIM_Module* TIMx, uint16_t TIM_output_channel_fast) +{ + uint16_t temp_value = 0; + /* Get the TIMx CCMOD1 register value */ + temp_value = TIMx->CCMOD1; + /* Reset the OC1FE Bit */ + temp_value &= (uint16_t) ~((uint16_t)TIM_OC_FAST_ENABLE); + /* Enable or Disable the Output Compare Fast Bit */ + temp_value |= TIM_output_channel_fast; + /* Write to TIMx CCMOD1 */ + TIMx->CCMOD1 = temp_value; +} + +/** +*\*\name TIM_Output_Channel2_Fast_Set +*\*\fun Initializes the TIM break and dead time register +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\param TIM_output_channel_fast: +*\*\ - TIM_OC_FAST_ENABLE TIM Output fast enable +*\*\ - TIM_OC_FAST_DISABLE TIM Output fast disable +*\*\return none +**/ +void TIM_Output_Channel2_Fast_Set(TIM_Module* TIMx, uint16_t TIM_output_channel_fast) +{ + uint16_t temp_value = 0; + /* Get the TIMx CCMOD1 register value */ + temp_value = TIMx->CCMOD1; + /* Reset the OC1FE Bit */ + temp_value &= (uint16_t) ~((uint16_t)TIM_CCMOD1_OC2FEN); + /* Enable or Disable the Output Compare Fast Bit */ + temp_value |= (uint16_t)(TIM_output_channel_fast << 8); + /* Write to TIMx CCMOD1 */ + TIMx->CCMOD1 = temp_value; +} + +/** +*\*\name TIM_Output_Channel3_Fast_Set +*\*\fun Initializes the TIM break and dead time register +*\*\param TIMx: +*\*\ - TIM1 +*\*\param TIM_output_channel_fast: +*\*\ - TIM_OC_FAST_ENABLE TIM Output fast enable +*\*\ - TIM_OC_FAST_DISABLE TIM Output fast disable +*\*\return none +**/ +void TIM_Output_Channel3_Fast_Set(TIM_Module* TIMx, uint16_t TIM_output_channel_fast) +{ + uint16_t temp_value = 0; + /* Get the TIMx CCMOD1 register value */ + temp_value = TIMx->CCMOD2; + /* Reset the OC1FE Bit */ + temp_value &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC3FEN); + /* Enable or Disable the Output Compare Fast Bit */ + temp_value |= TIM_output_channel_fast; + /* Write to TIMx CCMOD2 */ + TIMx->CCMOD2 = temp_value; +} + +/** +*\*\name TIM_Output_Channel4_Fast_Set +*\*\fun Initializes the TIM break and dead time register +*\*\param TIMx: +*\*\ - TIM1 +*\*\param TIM_output_channel_fast: +*\*\ - TIM_OC_FAST_ENABLE TIM Output fast enable +*\*\ - TIM_OC_FAST_DISABLE TIM Output fast disable +*\*\return none +**/ +void TIM_Output_Channel4_Fast_Set(TIM_Module* TIMx, uint16_t TIM_output_channel_fast) +{ + uint16_t temp_value = 0; + /* Get the TIMx CCMOD1 register value */ + temp_value = TIMx->CCMOD2; + /* Reset the OC1FE Bit */ + temp_value &= (uint16_t) ~((uint16_t)TIM_CCMOD2_OC4FEN); + /* Enable or Disable the Output Compare Fast Bit */ + temp_value |= (uint16_t)(TIM_output_channel_fast << 8); + /* Write to TIMx CCMOD2 */ + TIMx->CCMOD2 = temp_value; +} + +/** +*\*\name TIM_Output_Channel5_Fast_Set +*\*\fun Initializes the TIM break and dead time register +*\*\param TIMx: +*\*\ - TIM1 +*\*\param TIM_output_channel_fast: +*\*\ - TIM_OC_FAST_ENABLE TIM Output fast enable +*\*\ - TIM_OC_FAST_DISABLE TIM Output fast disable +*\*\return none +**/ +void TIM_Output_Channel5_Fast_Set(TIM_Module* TIMx, uint16_t TIM_output_channel_fast) +{ + uint16_t temp_value = 0; + /* Get the TIMx CCMOD1 register value */ + temp_value = TIMx->CCMOD3; + /* Reset the OC1FE Bit */ + temp_value &= (uint16_t) ~((uint16_t)TIM_CCMOD3_OC5FEN); + /* Enable or Disable the Output Compare Fast Bit */ + temp_value |= TIM_output_channel_fast; + /* Write to TIMx CCMOD3 */ + TIMx->CCMOD3 = temp_value; +} + + +/** +*\*\name TIM_Output_Channel1_Reference_Clear +*\*\fun Initializes the TIM break and dead time register +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\param TIM_output_channel_clear: +*\*\ - TIM_OC_CLEAR_ENABLE TIM Output clear enable +*\*\ - TIM_OC_CLEAR_DISABLE TIM Output clear disable +*\*\return none +**/ +void TIM_Output_Channel1_Reference_Clear(TIM_Module* TIMx, uint16_t TIM_output_channel_clear) +{ + uint16_t temp_value = 0; + /* Check the parameters */ + + temp_value = TIMx->CCMOD1; + + /* Reset the OC1CE Bit */ + temp_value &= (uint16_t) ~((uint16_t)TIM_OC1_CLEAR_MASK); + /* Enable or Disable the Output Compare Clear Bit */ + temp_value |= TIM_output_channel_clear; + /* Write to TIMx CCMOD1 register */ + TIMx->CCMOD1 = temp_value; +} + +/** +*\*\name TIM_Output_Channel2_Reference_Clear +*\*\fun Initializes the TIM break and dead time register +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\param TIM_output_channel_clear: +*\*\ - TIM_OC_CLEAR_ENABLE TIM Output clear enable +*\*\ - TIM_OC_CLEAR_DISABLE TIM Output clear disable +*\*\return none +**/ +void TIM_Output_Channel2_Reference_Clear(TIM_Module* TIMx, uint16_t TIM_output_channel_clear) +{ + uint16_t temp_value = 0; + /* Check the parameters */ + + temp_value = TIMx->CCMOD1; + + /* Reset the OC1CE Bit */ + temp_value &= (uint16_t) ~((uint16_t)TIM_OC2_CLEAR_MASK); + /* Enable or Disable the Output Compare Clear Bit */ + temp_value |= (uint16_t)(TIM_output_channel_clear << 8); + /* Write to TIMx CCMOD1 register */ + TIMx->CCMOD1 = temp_value; +} + +/** +*\*\name TIM_Output_Channel3_Reference_Clear +*\*\fun Initializes the TIM break and dead time register +*\*\param TIMx: +*\*\ - TIM1 +*\*\param TIM_output_channel_clear: +*\*\ - TIM_OC_CLEAR_ENABLE TIM Output clear enable +*\*\ - TIM_OC_CLEAR_DISABLE TIM Output clear disable +*\*\return none +**/ +void TIM_Output_Channel3_Reference_Clear(TIM_Module* TIMx, uint16_t TIM_output_channel_clear) +{ + uint16_t temp_value = 0; + /* Check the parameters */ + + temp_value = TIMx->CCMOD2; + + /* Reset the OC1CE Bit */ + temp_value &= (uint16_t) ~((uint16_t)TIM_OC3_CLEAR_MASK); + /* Enable or Disable the Output Compare Clear Bit */ + temp_value |= TIM_output_channel_clear; + /* Write to TIMx CCMOD2 register */ + TIMx->CCMOD2 = temp_value; +} + +/** +*\*\name TIM_Output_Channel4_Reference_Clear +*\*\fun Initializes the TIM break and dead time register +*\*\param TIMx: +*\*\ - TIM1 +*\*\param TIM_output_channel_clear: +*\*\ - TIM_OC_CLEAR_ENABLE TIM Output clear enable +*\*\ - TIM_OC_CLEAR_DISABLE TIM Output clear disable +*\*\return none +**/ +void TIM_Output_Channel4_Reference_Clear(TIM_Module* TIMx, uint16_t TIM_output_channel_clear) +{ + uint16_t temp_value = 0; + /* Check the parameters */ + + temp_value = TIMx->CCMOD2; + + /* Reset the OC1CE Bit */ + temp_value &= (uint16_t) ~((uint16_t)TIM_OC4_CLEAR_MASK); + /* Enable or Disable the Output Compare Clear Bit */ + temp_value |= (uint16_t)(TIM_output_channel_clear << 8); + /* Write to TIMx CCMOD2 register */ + TIMx->CCMOD2 = temp_value; +} +/** +*\*\name TIM_Output_Channel5_Reference_Clear +*\*\fun Initializes the TIM break and dead time register +*\*\param TIMx: +*\*\ - TIM1 +*\*\param TIM_output_channel_clear: +*\*\ - TIM_OC_CLEAR_ENABLE TIM Output clear enable +*\*\ - TIM_OC_CLEAR_DISABLE TIM Output clear disable +*\*\return none +**/ +void TIM_Output_Channel5_Reference_Clear(TIM_Module* TIMx, uint16_t TIM_output_channel_clear) +{ + uint16_t temp_value = 0; + /* Check the parameters */ + + temp_value = TIMx->CCMOD3; + + /* Reset the OC1CE Bit */ + temp_value &= (uint16_t) ~((uint16_t)TIM_OC5_CLEAR_MASK); + /* Enable or Disable the Output Compare Clear Bit */ + temp_value |= TIM_output_channel_clear; + /* Write to TIMx CCMOD3 register */ + TIMx->CCMOD3 = temp_value; +} + + +/** +*\*\name TIM_Output_Channel1_Initialize +*\*\fun Initializes the TIM break and dead time register +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\param TIM_OCInitStruct: +*\*\ - Refer to the definition of OCInitType. +*\*\return none +**/ +void TIM_Output_Channel1_Initialize(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct) +{ + uint16_t temp_value1 = 0; + uint32_t temp_value2 = 0; + + /* Disable the Channel 1， Reset the CC1EN Bit */ + TIM_Capture_Compare_Ch_Disable(TIMx, TIM_CH_1); + + /* Get the TIMx CTRL2 register value */ + temp_value2 = TIMx->CTRL2; + + /* Get the TIMx CCMOD1 register value */ + temp_value1 = TIMx->CCMOD1; + + /* Reset the Output Compare Mode Bits */ + temp_value1 &= (uint16_t)(~((uint16_t)TIM_OC1MODE_MASK)); + temp_value1 &= (uint16_t)(~((uint16_t)TIM_IC1_SELECTION_MASK)); + + /* Select the Output Compare Mode */ + temp_value1 |= TIM_OCInitStruct->OcMode; + + TIM_Output_Channel_Polarity_Set(TIMx, TIM_OCInitStruct->OcPolarity, TIM_CH_1); + + /* Set the Output State */ + if(TIM_OCInitStruct->OutputState) + { + TIM_Capture_Compare_Ch_Enable(TIMx, TIM_CH_1); + } + else + { + TIM_Capture_Compare_Ch_Disable(TIMx, TIM_CH_1); + } + + if (TIMx == TIM1) + { + /* Set the Output N Polarity level */ + TIM_Output_Channel_N_Polarity_Set(TIMx, TIM_OCInitStruct->OcNPolarity, TIM_CH_1); + + /* Set the Output N State */ + if(TIM_OCInitStruct->OutputNState) + { + TIM_Capture_Compare_Ch_N_Enable(TIMx, TIM_CH_1); + } + else + { + TIM_Capture_Compare_Ch_N_Disable(TIMx, TIM_CH_1); + } + + /* Reset the Output Compare and Output Compare N IDLE State */ + temp_value2 &= (uint32_t)(~((uint32_t)TIM_OC1_IDLE_STATE_MASK)); + temp_value2 &= (uint32_t)(~((uint32_t)TIM_OC1N_IDLE_STATE_MASK)); + + /* Set the Output Idle state */ + temp_value2 |= TIM_OCInitStruct->OcIdleState; + /* Set the Output N Idle state */ + temp_value2 |= TIM_OCInitStruct->OcNIdleState; + } + /* Write to TIMx CTRL2 */ + TIMx->CTRL2 = temp_value2; + + /* Write to TIMx CCMOD1 */ + TIMx->CCMOD1 = temp_value1; + + /* Set the Capture Compare Register value */ + TIMx->CCDAT1 = TIM_OCInitStruct->Pulse; + +} + +/** +*\*\name TIM_Output_Channel2_Initialize +*\*\fun Initializes the TIM break and dead time register +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\param TIM_OCInitStruct: +*\*\ - Refer to the definition of OCInitType. +*\*\return none +**/ +void TIM_Output_Channel2_Initialize(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct) +{ + uint16_t temp_value1 = 0; + uint32_t temp_value2 = 0; + + /* Disable the Channel 2， Reset the CC2EN Bit */ + TIM_Capture_Compare_Ch_Disable(TIMx, TIM_CH_2); + + /* Get the TIMx CTRL2 register value */ + temp_value2 = TIMx->CTRL2; + + /* Get the TIMx CCMOD1 register value */ + temp_value1 = TIMx->CCMOD1; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + temp_value1 &= (uint16_t)(~((uint16_t)TIM_OC2MODE_MASK)); + temp_value1 &= (uint16_t)(~((uint16_t)TIM_IC2_SELECTION_MASK)); + + /* Select the Output Compare Mode */ + temp_value1 |= (uint16_t)(TIM_OCInitStruct->OcMode << 8); + + TIM_Output_Channel_Polarity_Set(TIMx, TIM_OCInitStruct->OcPolarity, TIM_CH_2); + + /* Set the Output State */ + if(TIM_OCInitStruct->OutputState) + { + TIM_Capture_Compare_Ch_Enable(TIMx, TIM_CH_2); + } + else + { + TIM_Capture_Compare_Ch_Disable(TIMx, TIM_CH_2); + } + + if (TIMx == TIM1) + { + /* Set the Output N Polarity level */ + TIM_Output_Channel_N_Polarity_Set(TIMx, TIM_OCInitStruct->OcNPolarity, TIM_CH_2); + + /* Set the Output N State */ + if(TIM_OCInitStruct->OutputNState) + { + TIM_Capture_Compare_Ch_N_Enable(TIMx, TIM_CH_2); + } + else + { + TIM_Capture_Compare_Ch_N_Disable(TIMx, TIM_CH_2); + } + + /* Reset the Output Compare and Output Compare N IDLE State */ + temp_value2 &= (uint32_t)(~((uint32_t)TIM_OC2_IDLE_STATE_MASK)); + temp_value2 &= (uint32_t)(~((uint32_t)TIM_OC2N_IDLE_STATE_MASK)); + + /* Set the Output Idle state */ + temp_value2 |= (uint32_t)(TIM_OCInitStruct->OcIdleState << 2); + /* Set the Output N Idle state */ + temp_value2 |= (uint32_t)(TIM_OCInitStruct->OcNIdleState << 2); + } + /* Write to TIMx CTRL2 */ + TIMx->CTRL2 = temp_value2; + + /* Write to TIMx CCMOD1 */ + TIMx->CCMOD1 = temp_value1; + + /* Set the Capture Compare Register value */ + TIMx->CCDAT2 = TIM_OCInitStruct->Pulse; + +} + +/** +*\*\name TIM_Output_Channel3_Initialize +*\*\fun Initializes the TIM break and dead time register +*\*\param TIMx: +*\*\ - TIM1 +*\*\param TIM_OCInitStruct: +*\*\ - Refer to the definition of OCInitType. +*\*\return none +**/ +void TIM_Output_Channel3_Initialize(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct) +{ + uint16_t temp_value1 = 0; + uint32_t temp_value2 = 0; + + /* Disable the Channel 3， Reset the CC3EN Bit */ + TIM_Capture_Compare_Ch_Disable(TIMx, TIM_CH_3); + + /* Get the TIMx CTRL2 register value */ + temp_value2 = TIMx->CTRL2; + + /* Get the TIMx CCMOD2 register value */ + temp_value1 = TIMx->CCMOD2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + temp_value1 &= (uint16_t)(~((uint16_t)TIM_OC3MODE_MASK)); + temp_value1 &= (uint16_t)(~((uint16_t)TIM_IC3_SELECTION_MASK)); + /* Select the Output Compare Mode */ + temp_value1 |= TIM_OCInitStruct->OcMode; + + TIM_Output_Channel_Polarity_Set(TIMx, TIM_OCInitStruct->OcPolarity, TIM_CH_3); + + /* Set the Output State */ + if(TIM_OCInitStruct->OutputState) + { + TIM_Capture_Compare_Ch_Enable(TIMx, TIM_CH_3); + } + else + { + TIM_Capture_Compare_Ch_Disable(TIMx, TIM_CH_3); + } + + if (TIMx == TIM1) + { + /* Set the Output N Polarity level */ + TIM_Output_Channel_N_Polarity_Set(TIMx, TIM_OCInitStruct->OcNPolarity, TIM_CH_3); + + /* Set the Output N State */ + if(TIM_OCInitStruct->OutputNState) + { + TIM_Capture_Compare_Ch_N_Enable(TIMx, TIM_CH_3); + } + else + { + TIM_Capture_Compare_Ch_N_Disable(TIMx, TIM_CH_3); + } + /* Reset the Output Compare and Output Compare N IDLE State */ + temp_value2 &= (uint32_t)(~((uint32_t)TIM_OC3_IDLE_STATE_MASK)); + temp_value2 &= (uint32_t)(~((uint32_t)TIM_OC3N_IDLE_STATE_MASK)); + /* Set the Output Idle state */ + temp_value2 |= (uint32_t)(TIM_OCInitStruct->OcIdleState << 4); + /* Set the Output N Idle state */ + temp_value2 |= (uint32_t)(TIM_OCInitStruct->OcNIdleState << 4); + } + /* Write to TIMx CTRL2 */ + TIMx->CTRL2 = temp_value2; + + /* Write to TIMx CCMOD2 */ + TIMx->CCMOD2 = temp_value1; + + /* Set the Capture Compare Register value */ + TIMx->CCDAT3 = TIM_OCInitStruct->Pulse; + +} + +/** +*\*\name TIM_Output_Channel4_Initialize +*\*\fun Initializes the TIM break and dead time register +*\*\param TIMx: +*\*\ - TIM1 +*\*\param TIM_OCInitStruct: +*\*\ - Refer to the definition of OCInitType. +*\*\return none +*\*\note The CH4N is only for TIM1. +**/ +void TIM_Output_Channel4_Initialize(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct) +{ + uint16_t temp_value1 = 0; + uint32_t temp_value2 = 0; + + /* Disable the Channel 4， Reset the CC4EN Bit */ + TIM_Capture_Compare_Ch_Disable(TIMx, TIM_CH_4); + + /* Get the TIMx CTRL2 register value */ + temp_value2 = TIMx->CTRL2; + + /* Get the TIMx CCMOD2 register value */ + temp_value1 = TIMx->CCMOD2; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + temp_value1 &= (uint16_t)(~((uint16_t)TIM_OC4MODE_MASK)); + temp_value1 &= (uint16_t)(~((uint16_t)TIM_IC4_SELECTION_MASK)); + + /* Select the Output Compare Mode */ + temp_value1 |= (uint16_t)(TIM_OCInitStruct->OcMode << 8); + + TIM_Output_Channel_Polarity_Set(TIMx, TIM_OCInitStruct->OcPolarity, TIM_CH_4); + + /* Set the Output State */ + if(TIM_OCInitStruct->OutputState) + { + TIM_Capture_Compare_Ch_Enable(TIMx, TIM_CH_4); + } + else + { + TIM_Capture_Compare_Ch_Disable(TIMx, TIM_CH_4); + } + + if (TIMx == TIM1) + { + /* Reset the Output Compare IDLE State */ + temp_value2 &= (uint32_t)(~((uint32_t)TIM_OC4_IDLE_STATE_MASK)); + /* Set the Output Idle state */ + temp_value2 |= (uint32_t)(TIM_OCInitStruct->OcIdleState << 6); + } + + /* Write to TIMx CTRL2 */ + TIMx->CTRL2 = temp_value2; + + /* Write to TIMx CCMOD2 */ + TIMx->CCMOD2 = temp_value1; + + /* Set the Capture Compare Register value */ + TIMx->CCDAT4 = TIM_OCInitStruct->Pulse; + +} + +/** +*\*\name TIM_Output_Channel5_Initialize +*\*\fun Initializes the TIM break and dead time register +*\*\param TIMx: +*\*\ - TIM1 +*\*\param TIM_OCInitStruct: +*\*\ - Refer to the definition of OCInitType. +*\*\return none +**/ +void TIM_Output_Channel5_Initialize(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct) +{ + uint16_t temp_value1 = 0; + uint32_t temp_value2 = 0; + + /* Disable the Channel 5， Reset the CC5EN Bit */ + TIM_Capture_Compare_Ch_Disable(TIMx, TIM_CH_5); + + /* Get the TIMx CTRL2 register value */ + temp_value2 = TIMx->CTRL2; + + /* Get the TIMx CCMOD3 register value */ + temp_value1 = TIMx->CCMOD3; + + /* Reset the Output Compare mode and Capture/Compare selection Bits */ + temp_value1 &= (uint16_t)(~((uint16_t)TIM_OC5MODE_MASK)); + + /* Select the Output Compare Mode */ + temp_value1 |= (uint16_t)(TIM_OCInitStruct->OcMode); + + TIM_Output_Channel_Polarity_Set(TIMx, TIM_OCInitStruct->OcPolarity, TIM_CH_5); + + /* Set the Output State */ + if(TIM_OCInitStruct->OutputState) + { + TIM_Capture_Compare_Ch_Enable(TIMx, TIM_CH_5); + } + else + { + TIM_Capture_Compare_Ch_Disable(TIMx, TIM_CH_5); + } + + if (TIMx == TIM1) + { + + /* Reset the Output Compare IDLE State */ + temp_value2 &= (uint32_t)(~((uint32_t)TIM_OC5_IDLE_STATE_MASK)); + /* Set the Output Idle state */ + temp_value2 |= (uint32_t)(TIM_OCInitStruct->OcIdleState << 8); + } + /* Write to TIMx CTRL2 */ + TIMx->CTRL2 = temp_value2; + + /* Write to TIMx CCMOD3 */ + TIMx->CCMOD3 = temp_value1; + + /* Set the Capture Compare Register value */ + TIMx->CCDAT5 = TIM_OCInitStruct->Pulse; + +} + + + + + +/** +*\*\name TIM_PWM_Output_Enable. +*\*\fun Initializes the TIM break and dead time register +*\*\param TIMx: +*\*\ - TIM1 +*\*\return none +**/ +void TIM_PWM_Output_Enable(TIM_Module* TIMx) +{ + TIMx->BKDT |= TIM_MAIN_OUTPUT_ENABLE; +} + +/** +*\*\name TIM_PWM_Output_Disable. +*\*\fun Initializes the TIM break and dead time register +*\*\param TIMx: +*\*\ - TIM1 +*\*\return none +**/ +void TIM_PWM_Output_Disable(TIM_Module* TIMx) +{ + TIMx->BKDT &= (uint16_t)(~((uint16_t)TIM_MAIN_OUTPUT_ENABLE)); +} + + + +void TIM_Output_Channel_Struct_Initialize(OCInitType* TIM_OCInitStruct) +{ + /* Set the default configuration */ + TIM_OCInitStruct->OcMode = TIM_OCMODE_TIMING; + TIM_OCInitStruct->OutputState = TIM_OUTPUT_STATE_DISABLE; + TIM_OCInitStruct->OutputNState = TIM_OUTPUT_NSTATE_DISABLE; + TIM_OCInitStruct->Pulse = 0x0000; + TIM_OCInitStruct->OcPolarity = TIM_OC_POLARITY_HIGH; + TIM_OCInitStruct->OcNPolarity = TIM_OC_POLARITY_HIGH; + TIM_OCInitStruct->OcIdleState = TIM_OC_IDLE_STATE_RESET; + TIM_OCInitStruct->OcNIdleState = TIM_OCN_IDLE_STATE_RESET; +} + + +/** +*\*\name TIM_Lock_Up_Break_Enable. +*\*\param TIMx: +*\*\ - TIM1 +*\*\return none +**/ +void TIM_Lock_Up_Break_Enable(TIM_Module* TIMx) +{ + TIMx->CTRL1 |= TIM_LOCKUP_AS_BREAK_IN; +} +/** +*\*\name TIM_Lock_Up_Break_Disable. +*\*\param TIMx: +*\*\ - TIM1 +*\*\return none +**/ +void TIM_Lock_Up_Break_Disable(TIM_Module* TIMx) +{ + TIMx->CTRL1 &= (uint32_t)(~TIM_LOCKUP_AS_BREAK_IN); +} +/** +*\*\name TIM_Pvd_Break_Enable. +*\*\param TIMx: +*\*\ - TIM1 +*\*\return none +**/ +void TIM_Pvd_Break_Enable(TIM_Module* TIMx) +{ + TIMx->CTRL1 |= TIM_PVD_AS_BREAK_IN; +} + +/** +*\*\name TIM_Pvd_Break_Disable. +*\*\param TIMx: +*\*\ - TIM1 +*\*\return none +**/ +void TIM_Pvd_Break_Disable(TIM_Module* TIMx) +{ + TIMx->CTRL1 &= (uint32_t)(~TIM_PVD_AS_BREAK_IN); +} + +/** +*\*\name TIM_IOM_Comp_Break. +*\*\param TIMx: +*\*\ - TIM1 +*\*\param IOM_Comp_Selection: +*\*\ - true Comp as break in source +*\*\ - false IOM as break in source +*\*\return none +**/ +void TIM_IOM_Comp_Break(TIM_Module* TIMx, bool IOM_Comp_Selection) +{ + if(IOM_Comp_Selection) + { + TIMx->CTRL1 |= TIM_COMP_AS_BREAK_IN; + } + else + { + TIMx->CTRL1 &= (uint32_t)(~TIM_COMP_AS_BREAK_IN); + } +} + +/** +*\*\name TIM_Break_And_Dead_Time_Set. +*\*\param TIMx: +*\*\ - TIM1 +*\*\param TIM_BDTRInitStruct: +*\*\ - refer to the definition of TIM_BDTRInitType +*\*\return none +**/ +void TIM_Break_And_Dead_Time_Set(TIM_Module* TIMx, TIM_BDTRInitType* TIM_BDTRInitStruct) +{ + /* Set the Lock level, the Break enable Bit and the Ploarity, the OSSR State, + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + TIMx->BKDT = (uint16_t)TIM_BDTRInitStruct->OssrState | TIM_BDTRInitStruct->OssiState | TIM_BDTRInitStruct->LockLevel + | TIM_BDTRInitStruct->DeadTime | TIM_BDTRInitStruct->Break | TIM_BDTRInitStruct->BreakPolarity + | TIM_BDTRInitStruct->AutomaticOutput; + + /*IOMBKPEN 0 meaning iom as break enable*/ + if (TIM_BDTRInitStruct->IomBreakEn) + { + TIM_IOM_Comp_Break(TIMx, false); + } + /*IOMBKPEN 1 meaning comp as break enable*/ + else + { + TIM_IOM_Comp_Break(TIMx, true); + } + + if (TIM_BDTRInitStruct->LockUpBreakEn) + { + TIM_Lock_Up_Break_Enable(TIMx); + } + else + { + TIM_Lock_Up_Break_Disable(TIMx); + } + + if(TIM_BDTRInitStruct->PvdBreakEn) + { + TIM_Pvd_Break_Enable(TIMx); + } + else + { + TIM_Pvd_Break_Disable(TIMx); + } +} + + +/** +*\*\name TIM_Break_And_Dead_Time_Struct_Initialize. +*\*\param TIM_BDTRInitStruct: +*\*\ - refer to the definition of TIM_BDTRInitType +*\*\return none +**/ +void TIM_Break_And_Dead_Time_Struct_Initialize(TIM_BDTRInitType* TIM_BDTRInitStruct) +{ + /* Set the default configuration */ + TIM_BDTRInitStruct->OssrState = TIM_OSSR_STATE_DISABLE; + TIM_BDTRInitStruct->OssiState = TIM_OSSI_STATE_DISABLE; + TIM_BDTRInitStruct->LockLevel = TIM_LOCK_LEVEL_OFF; + TIM_BDTRInitStruct->DeadTime = 0x00; + TIM_BDTRInitStruct->Break = TIM_BREAK_IN_DISABLE; + TIM_BDTRInitStruct->BreakPolarity = TIM_BREAK_POLARITY_LOW; + TIM_BDTRInitStruct->AutomaticOutput = TIM_AUTO_OUTPUT_DISABLE; + TIM_BDTRInitStruct->IomBreakEn = false; + TIM_BDTRInitStruct->LockUpBreakEn = false; + TIM_BDTRInitStruct->PvdBreakEn = false; +} + +/** +*\*\name TIM_Interrupt_Enable. +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\ - TIM6 +*\*\param TIM_IT +*\*\ - TIM_INT_UPDATE TIM update Interrupt source +*\*\ - TIM_INT_CC1 TIM Capture Compare 1 Interrupt source +*\*\ - TIM_INT_CC2 TIM Capture Compare 2 Interrupt source +*\*\ - TIM_INT_CC3 TIM Capture Compare 3 Interrupt source +*\*\ - TIM_INT_CC4 TIM Capture Compare 4 Interrupt source +*\*\ - TIM_INT_COM TIM Commutation Interrupt source +*\*\ - TIM_INT_TRIG TIM Trigger Interrupt source +*\*\ - TIM_INT_BREAK TIM Break Interrupt source +*\*\note +*\*\ - TIM6 can only generate an update interrupt. +*\*\ - TIM_INT_BREAK TIM_INT_CC3 TIM_INT_CC4 TIM_INT_COM is used only with TIM1. +*\*\return none +**/ +void TIM_Interrupt_Enable(TIM_Module* TIMx, uint16_t TIM_IT) +{ + TIMx->DINTEN |= TIM_IT; +} + +/** +*\*\name TIM_Interrupt_Disable. +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\ - TIM6 +*\*\param TIM_IT +*\*\ - TIM_INT_UPDATE TIM update Interrupt source +*\*\ - TIM_INT_CC1 TIM Capture Compare 1 Interrupt source +*\*\ - TIM_INT_CC2 TIM Capture Compare 2 Interrupt source +*\*\ - TIM_INT_CC3 TIM Capture Compare 3 Interrupt source +*\*\ - TIM_INT_CC4 TIM Capture Compare 4 Interrupt source +*\*\ - TIM_INT_COM TIM Commutation Interrupt source +*\*\ - TIM_INT_TRIG TIM Trigger Interrupt source +*\*\ - TIM_INT_BREAK TIM Break Interrupt source +*\*\note +*\*\ - TIM6 can only generate an update interrupt. +*\*\ - TIM_INT_BREAK TIM_INT_CC3 TIM_INT_CC4 TIM_INT_COM is used only with TIM1. +*\*\return none +**/ +void TIM_Interrupt_Disable(TIM_Module* TIMx, uint16_t TIM_IT) +{ + TIMx->DINTEN &= (uint16_t)(~TIM_IT); +} + + + +/** +*\*\name TIM_Interrupt_Status_Get +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\ - TIM6 +*\*\param TIM_IT specifies the TIM interrupt source to check. +*\*\ - TIM_INT_UPDATE TIM update Interrupt source +*\*\ - TIM_INT_CC1 TIM Capture Compare 1 Interrupt source +*\*\ - TIM_INT_CC2 TIM Capture Compare 2 Interrupt source +*\*\ - TIM_INT_CC3 TIM Capture Compare 3 Interrupt source +*\*\ - TIM_INT_CC4 TIM Capture Compare 4 Interrupt source +*\*\ - TIM_INT_COM TIM Commutation Interrupt source +*\*\ - TIM_INT_TRIG TIM Trigger Interrupt source +*\*\ - TIM_INT_BREAK TIM Break Interrupt source +*\*\note +*\*\ - TIM6 can generate only an update interrupt. +*\*\ - TIM_INT_BREAK TIM_INT_CC3 TIM_INT_CC4 TIM_INT_COM is used only with TIM1. +*\*\return +*\*\ - SET +*\*\ - RESET +**/ +ITStatus TIM_Interrupt_Status_Get(TIM_Module* TIMx, uint32_t TIM_IT) +{ + uint32_t interrupt_status = 0x0, interrupt_enable = 0x0; + + interrupt_status = TIMx->STS & TIM_IT; + + interrupt_enable = TIMx->DINTEN & TIM_IT; + if ((interrupt_status != (uint32_t)RESET) && (interrupt_enable != (uint32_t)RESET)) + { + return SET; + } + else + { + return RESET; + } +} + +/** +*\*\name TIM_Interrupt_Pending_Bit_Clear +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\ - TIM6 +*\*\param TIM_IT +*\*\ - TIM_INT_UPDATE TIM1 update Interrupt source +*\*\ - TIM_INT_CC1 TIM Capture Compare 1 Interrupt source +*\*\ - TIM_INT_CC2 TIM Capture Compare 2 Interrupt source +*\*\ - TIM_INT_CC3 TIM Capture Compare 3 Interrupt source +*\*\ - TIM_INT_CC4 TIM Capture Compare 4 Interrupt source +*\*\ - TIM_INT_COM TIM Commutation Interrupt source +*\*\ - TIM_INT_TRIG TIM Trigger Interrupt source +*\*\ - TIM_INT_BREAK TIM Break Interrupt source +*\*\note +*\*\ - TIM6 and TIM7 can have only one update flag. +*\*\ - TIM6 can generate only an update interrupt. +*\*\ - TIM_INT_BREAK TIM_INT_CC3 TIM_INT_CC4 TIM_INT_COM is used only with TIM1. +*\*\return none +**/ +void TIM_Interrupt_Status_Clear(TIM_Module* TIMx, uint32_t TIM_IT) +{ + TIMx->STS = (uint32_t)~TIM_IT; +} + + +/** +*\*\name TIM_Flag_Status_Get +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\ - TIM6 +*\*\param TIM_IT +*\*\This parameter can be one of the following values: +*\*\ - TIM_FLAG_UPDATE TIM update Flag +*\*\ - TIM_FLAG_CC1 TIM Capture Compare 1 Flag +*\*\ - TIM_FLAG_CC2 TIM Capture Compare 2 Flag +*\*\ - TIM_FLAG_CC3 TIM Capture Compare 3 Flag +*\*\ - TIM_FLAG_CC4 TIM Capture Compare 4 Flag +*\*\ - TIM_FLAG_COM TIM Commutation Flag +*\*\ - TIM_FLAG_TRIG TIM Trigger Flag +*\*\ - TIM_FLAG_BREAK TIM Break Flag +*\*\ - TIM_FLAG_CC1OF TIM Capture Compare 1 overcapture Flag +*\*\ - TIM_FLAG_CC2OF TIM Capture Compare 2 overcapture Flag +*\*\ - TIM_FLAG_CC3OF TIM Capture Compare 3 overcapture Flag +*\*\ - TIM_FLAG_CC4OF TIM Capture Compare 4 overcapture Flag +*\*\ - TIM_FLAG_CC5 TIM Capture Compare 5 Flag +*\*\note +*\*\ - TIM6 can have only one update flag. +*\*\ - TIM_FLAG_BREAK TIM_FLAG_CC3 TIM_FLAG_CC4 TIM_FLAG_COM TIM_FLAG_CC3OF TIM_FLAG_CC4OF TIM_FLAG_CC5 is used only with TIM1. +*\*\return The new state of TIM_FLAG (SET or RESET). +**/ +FlagStatus TIM_Flag_Status_Get(TIM_Module* TIMx, uint32_t TIM_FLAG) +{ + if ((TIMx->STS & TIM_FLAG) != (uint32_t)RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/** +*\*\name TIM_Flag_Clear +*\*\param TIMx: +*\*\ - TIM1 +*\*\ - TIM3 +*\*\ - TIM6 +*\*\param TIM_IT +*\*\ - TIM_FLAG_UPDATE TIM update Flag +*\*\ - TIM_FLAG_CC1 TIM Capture Compare 1 Flag +*\*\ - TIM_FLAG_CC2 TIM Capture Compare 2 Flag +*\*\ - TIM_FLAG_CC3 TIM Capture Compare 3 Flag +*\*\ - TIM_FLAG_CC4 TIM Capture Compare 4 Flag +*\*\ - TIM_FLAG_COM TIM Commutation Flag +*\*\ - TIM_FLAG_TRIG TIM Trigger Flag +*\*\ - TIM_FLAG_BREAK TIM Break Flag +*\*\ - TIM_FLAG_CC1OF TIM Capture Compare 1 overcapture Flag +*\*\ - TIM_FLAG_CC2OF TIM Capture Compare 2 overcapture Flag +*\*\ - TIM_FLAG_CC3OF TIM Capture Compare 3 overcapture Flag +*\*\ - TIM_FLAG_CC4OF TIM Capture Compare 4 overcapture Flag +*\*\ - TIM_FLAG_CC5 TIM Capture Compare 5 Flag +*\*\ - TIM_FLAG_CC6 TIM Capture Compare 6 Flag +*\*\note +*\*\ - TIM6 can have only one update flag. +*\*\ - TIM_FLAG_BREAK TIM_FLAG_CC3 TIM_FLAG_CC4 TIM_FLAG_COM TIM_FLAG_CC3OF TIM_FLAG_CC4OF TIM_FLAG_CC5 is used only with TIM1. +*\*\return none +**/ +void TIM_Flag_Clear(TIM_Module* TIMx, uint32_t TIM_FLAG) +{ + TIMx->STS = (uint32_t)~TIM_FLAG; +} + + diff --git a/firmware/n32g003_std_periph_driver/src/n32g003_uart.c b/firmware/n32g003_std_periph_driver/src/n32g003_uart.c new file mode 100644 index 0000000..cd65b0b --- /dev/null +++ b/firmware/n32g003_std_periph_driver/src/n32g003_uart.c @@ -0,0 +1,627 @@ +/** +* Copyright (c) 2022, Nations Technologies Inc. +* +* All rights reserved. +* +* This software is the exclusive property of Nations Technologies Inc. (Hereinafter +* referred to as NATIONS). This software, and the product of NATIONS described herein +* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties +* of the People's Republic of China and other applicable jurisdictions worldwide. +* +* NATIONS does not grant any license under its patents, copyrights, trademarks, or other +* intellectual property rights. Names and brands of third party may be mentioned or referred +* thereto (if any) for identification purposes only. +* +* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and +* improvements to this software at any time without notice. Please contact NATIONS and obtain +* the latest version of this software before placing orders. + +* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes +* no responsibility for the accuracy and reliability of this software. +* +* It is the responsibility of the user of this software to properly design, program, and test +* the functionality and safety of any application made of this information and any resulting product. +* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or +* consequential damages arising in any way out of the use of this software or the Product. +* +* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any +* malfunction or failure of which may cause loss of human life, bodily injury or severe property +* damage. Such applications are deemed, "Insecure Usage". +* +* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS +* harmless from and against all claims, costs, damages, and other liabilities, arising from or related +* to any customer's Insecure Usage. + +* Any express or implied warranty with regard to this software or the Product, including,but not +* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement +* are disclaimed to the fullest extent permitted by law. + +* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe +* or otherwise distribute this software for any purposes, in whole or in part. +* +* NATIONS products and technologies shall not be used for or incorporated into any products or systems +* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. +* User shall comply with any applicable export control laws and regulations promulgated and administered by +* the governments of any countries asserting jurisdiction over the parties or transactions. +**/ + + /** +*\*\file n32g003_uart.c +*\*\author Nations +*\*\version v1.0.0 +*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved. +**/ + +#include "n32g003_uart.h" +#include "n32g003_rcc.h" + +/** +*\*\name UART_Reset +*\*\fun Reset the UARTx registers. +*\*\param UARTx : +*\*\ - UART1 +*\*\ - UART2 +*\*\return none +**/ +void UART_Reset(UART_Module* UARTx) +{ + if (UARTx == UART1) + { + /* UART1 Reset */ + RCC_Peripheral_Reset(RCC_RST_UART1RST); + } + else if (UARTx == UART2) + { + /* UART2 Reset */ + RCC_Peripheral_Reset(RCC_RST_UART2RST); + } +} + +/** +*\*\name UART_Initializes +*\*\fun Initializes the UARTx peripheral according to UART_InitStruct . +*\*\param UARTx : +*\*\ - UART1 +*\*\ - UART2 +*\*\param UART_InitStruct : +*\*\ - buad_rate : +*\*\ - (((buad_rate) > 0) && ((buad_rate) < 0x00337F99)) +*\*\ - WordLength +*\*\ - UART_WL_8B +*\*\ - UART_WL_9B +*\*\ - StopBits +*\*\ - UART_STPB_1 +*\*\ - UART_STPB_2 +*\*\ - Parity +*\*\ - UART_PE_NO +*\*\ - UART_PE_EVEN +*\*\ - UART_PE_ODD +*\*\ - Mode +*\*\ - UART_MODE_RX +*\*\ - UART_MODE_TX +*\*\return none +**/ +void UART_Initializes(UART_Module* UARTx, UART_InitType* UART_InitStruct) +{ + UART_Baud_Rate_Config(UARTx,UART_InitStruct->BaudRate); + UART_Word_Length_Config(UARTx,UART_InitStruct->WordLength); + UART_Stop_Bits_Config(UARTx,UART_InitStruct->StopBits); + UART_Parity_Config(UARTx,UART_InitStruct->Parity); + UART_Mode_Config(UARTx,UART_InitStruct->Mode); +} + +/** +*\*\name UART_Baud_Rate_Config +*\*\fun Configure the baud rate of the UART. +*\*\ The baud rate is computed using the following formula: +*\*\ - IntegerDivider = ((PCLKx) / (16 * (UART_InitStruct->BaudRate))) +*\*\ - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 +*\*\param UARTx : +*\*\ - UART1 +*\*\ - UART2 +*\*\param buad_rate : +*\*\ - (((buad_rate) > 0) && ((buad_rate) < 0x00337F99)) +*\*\return none +**/ +void UART_Baud_Rate_Config(UART_Module* UARTx,uint32_t buad_rate) +{ + uint32_t temp_value = 0x00, apb_clock_value = 0x00; + uint32_t integer_divider_value = 0x00; + uint32_t fractional_divider_value = 0x00; + RCC_ClocksType RCC_ClocksStatus; + + RCC_Clocks_Frequencies_Value_Get(&RCC_ClocksStatus); + apb_clock_value = RCC_ClocksStatus.PclkFreq; + + /* Determine the integer part */ + integer_divider_value = ((25 * apb_clock_value) / (4 * buad_rate)); + temp_value = (integer_divider_value / 100) << 4; + + /* Determine the fractional part */ + fractional_divider_value = integer_divider_value - (100 * (temp_value >> 4)); + + /* Implement the fractional part in the register */ + temp_value |= ((((fractional_divider_value * 16) + 50) / 100)) & ((uint8_t)0x0F); + + /* Write to UART BRR */ + UARTx->BRCF = (uint16_t)temp_value; +} + +/** +*\*\name UART_Word_Length_Config +*\*\fun Configure the word length of the UART. +*\*\param UARTx : +*\*\ - UART1 +*\*\ - UART2 +*\*\param word_length : +*\*\ - UART_WL_8B +*\*\ - UART_WL_9B +*\*\return none +**/ +void UART_Word_Length_Config(UART_Module* UARTx,uint16_t word_length) +{ + uint32_t temp_value = 0x00; + temp_value = UARTx->CTRL1; + /* Clear M bit */ + temp_value &= UART_WL_MASK; + /* Configure the UART Word Length */ + temp_value |= word_length; + UARTx->CTRL1 = (uint16_t)temp_value; +} + +/** +*\*\name UART_Stop_Bits_Config +*\*\fun Configure the stop bits of the UART. +*\*\param UARTx : +*\*\ - UART1 +*\*\ - UART2 +*\*\param stop_bits : +*\*\ - UART_STPB_1 +*\*\ - UART_STPB_2 +*\*\return none +**/ +void UART_Stop_Bits_Config(UART_Module* UARTx,uint16_t stop_bits) +{ + uint32_t temp_value = 0x00; + temp_value = UARTx->CTRL2; + /* Clear STOP[13:12] bits */ + temp_value &= CTRL2_STPB_CLR_MASK; + /* Set STOP[13:12] bits according to stop bits value */ + temp_value |= stop_bits; + UARTx->CTRL2 = (uint16_t)temp_value; +} + +/** +*\*\name UART_Parity_Config +*\*\fun Configure the parity of the UART. +*\*\param UARTx : +*\*\ - UART1 +*\*\ - UART2 +*\*\param parity : +*\*\ - UART_PE_NO +*\*\ - UART_PE_EVEN +*\*\ - UART_PE_ODD +*\*\return none +**/ +void UART_Parity_Config(UART_Module* UARTx,uint16_t parity) +{ + uint32_t temp_value = 0x00; + temp_value = UARTx->CTRL1; + /* Clear parity[10:9] bits */ + temp_value &= UART_PE_MASK; + /* Configure the UART parity */ + temp_value |= parity; + UARTx->CTRL1 = (uint16_t)temp_value; +} + +/** +*\*\name UART_Mode_Config +*\*\fun Configure the mode of the UART. +*\*\param UARTx : +*\*\ - UART1 +*\*\ - UART2 +*\*\param mode : +*\*\ - UART_MODE_RX +*\*\ - UART_MODE_TX +*\*\return none +**/ +void UART_Mode_Config(UART_Module* UARTx,uint16_t mode) +{ + uint32_t temp_value = 0x00; + temp_value = UARTx->CTRL1; + /* Clear mode[3:2] bits */ + temp_value &= UART_MODE_MASK; + /* Configure the UART parity */ + temp_value |= mode; + UARTx->CTRL1 = (uint16_t)temp_value; +} + +/** +*\*\name UART_Structure_Initializes. +*\*\fun Fills each UART_InitStruct member with its default value. +*\*\param UART_InitStruct : +*\*\ - BaudRate +*\*\ - WordLength +*\*\ - StopBits +*\*\ - Parity +*\*\ - Mode +*\*\ - HardwareFlowControl +*\*\return none +**/ +void UART_Structure_Initializes(UART_InitType* UART_InitStruct) +{ + /* UART_InitStruct members default value */ + UART_InitStruct->BaudRate = 9600; + UART_InitStruct->WordLength = UART_WL_8B; + UART_InitStruct->StopBits = UART_STPB_1; + UART_InitStruct->Parity = UART_PE_NO; + UART_InitStruct->Mode = UART_MODE_RX | UART_MODE_TX; +} + +/** +*\*\name UART_Enable. +*\*\fun Enables the specified UART peripheral. +*\*\param UARTx : +*\*\ - UART1 +*\*\ - UART2 +*\*\return none +**/ +void UART_Enable(UART_Module* UARTx) +{ + /* Enable the selected UART by setting the UE bit in the CTRL1 register */ + UARTx->CTRL1 |= CTRL1_UEN_SET; +} + +/** +*\*\name UART_Disable. +*\*\fun Disables the specified UART peripheral. +*\*\param UARTx : +*\*\ - UART1 +*\*\ - UART2 +*\*\return none +**/ +void UART_Disable(UART_Module* UARTx) +{ + /* Disable the selected UART by clearing the UE bit in the CTRL1 register */ + UARTx->CTRL1 &= CTRL1_UEN_RESET; +} + +/** +*\*\name UART_Interrput_Enable. +*\*\fun Enables the specified UART interrupts. +*\*\param UARTx : +*\*\ - UART1 +*\*\ - UART2 +*\*\param UART_interrupt : +*\*\ - UART_INT_PEF +*\*\ - UART_INT_TXDE +*\*\ - UART_INT_TXC +*\*\ - UART_INT_RXDNE +*\*\ - UART_INT_IDLEF +*\*\return none +**/ +void UART_Interrput_Enable(UART_Module* UARTx, uint16_t UART_interrupt) +{ + uint32_t register_value = 0x00, interrupt_position = 0x00, temp_value = 0x00; + uint32_t base_value = 0x00; + + base_value = (uint32_t)UARTx; + + /* Get the UART register index */ + register_value = (((uint8_t)UART_interrupt) >> 0x5); + + /* Get the interrupt position */ + interrupt_position = UART_interrupt & INT_MASK; + temp_value = (((uint32_t)0x01) << interrupt_position); + + if (register_value == 0x01) /* The IT is in CTRL1 register */ + { + base_value += 0x0C; + } + else if (register_value == 0x02) /* The IT is in CTRL2 register */ + { + base_value += 0x10; + } + else /* The IT is in CTRL3 register */ + { + base_value += 0x14; + } + + *(__IO uint32_t*)base_value |= temp_value; +} + +/** +*\*\name UART_Interrput_Disable. +*\*\fun Disables the specified UART interrupts. +*\*\param UARTx : +*\*\ - UART1 +*\*\ - UART2 +*\*\param UART_interrupt : +*\*\ - UART_INT_PEF +*\*\ - UART_INT_TXDE +*\*\ - UART_INT_TXC +*\*\ - UART_INT_RXDNE +*\*\ - UART_INT_IDLEF +*\*\return none +**/ +void UART_Interrput_Disable(UART_Module* UARTx, uint16_t UART_interrupt) +{ + uint32_t register_value = 0x00, interrupt_position = 0x00, temp_value = 0x00; + uint32_t base_value = 0x00; + base_value = (uint32_t)UARTx; + + /* Get the UART register index */ + register_value = (((uint8_t)UART_interrupt) >> 0x5); + + /* Get the interrupt position */ + interrupt_position = UART_interrupt & INT_MASK; + temp_value = (((uint32_t)0x01) << interrupt_position); + + if (register_value == 0x01) /* The IT is in CTRL1 register */ + { + base_value += 0x0C; + } + else if (register_value == 0x02) /* The IT is in CTRL2 register */ + { + base_value += 0x10; + } + else /* The IT is in CTRL3 register */ + { + base_value += 0x14; + } + + *(__IO uint32_t*)base_value &= ~temp_value; +} + +/** +*\*\name UART_Address_Set. +*\*\fun Sets the address of the UART node. +*\*\param UARTx : +*\*\ - UART1 +*\*\ - UART2 +*\*\param UART_address : +*\*\ - (((UART_address)>=0x00)&&((UART_address)<0x10)) +*\*\return none +**/ +void UART_Address_Set(UART_Module* UARTx, uint8_t UART_address) +{ + /* Clear the UART address */ + UARTx->CTRL2 &= CTRL2_ADDR_MASK; + /* Set the UART address node */ + UARTx->CTRL2 |= UART_address; +} + +/** +*\*\name UART_WakeUp_Mode_Set. +*\*\fun Selects the UART WakeUp method. +*\*\param UARTx : +*\*\ - UART1 +*\*\ - UART2 +*\*\param UART_wake_up_mode : +*\*\ - UART_WUM_IDLELINE +*\*\ - UART_WUM_ADDRMASK +*\*\return none +**/ +void UART_WakeUp_Mode_Set(UART_Module* UARTx, uint16_t UART_wake_up_mode) +{ + UARTx->CTRL1 &= CTRL1_WUM_MASK; + UARTx->CTRL1 |= UART_wake_up_mode; +} + +/** +*\*\name UART_Receiver_Wakeup_Enable. +*\*\fun Enable the UART mute mode. +*\*\param UARTx : +*\*\ - UART1 +*\*\ - UART2 +*\*\return none +**/ +void UART_Receiver_Wakeup_Enable(UART_Module* UARTx) +{ + /* Enable the UART mute mode by setting the RWU bit in the CTRL1 register */ + UARTx->CTRL1 |= CTRL1_RCVWU_SET; +} + +/** +*\*\name UART_Receiver_Wakeup_Disable. +*\*\fun Disable the UART mute mode. +*\*\param UARTx : +*\*\ - UART1 +*\*\ - UART2 +*\*\return none +**/ +void UART_Receiver_Wakeup_Disable(UART_Module* UARTx) +{ + /* Disable the UART mute mode by clearing the RWU bit in the CTRL1 register */ + UARTx->CTRL1 &= CTRL1_RCVWU_RESET; +} + +/** +*\*\name UART_Data_Send. +*\*\fun Transmits single data through the UARTx peripheral. +*\*\param UARTx : +*\*\ - UART1 +*\*\ - UART2 +*\*\param data : +*\*\ - The data to transmit. +*\*\return none +**/ +void UART_Data_Send(UART_Module* UARTx, uint16_t data) +{ + /* Transmit Data */ + UARTx->DAT = (data & (uint16_t)0x01FF); +} + +/** +*\*\name UART_Data_Receive. +*\*\fun Returns the most recent received data by the UARTx peripheral. +*\*\param UARTx : +*\*\ - UART1 +*\*\ - UART2 +*\*\return The received data. +**/ +uint16_t UART_Data_Receive(UART_Module* UARTx) +{ + /* Receive Data */ + return (uint16_t)(UARTx->DAT & (uint16_t)0x01FF); +} + +/** +*\*\name UART_Break_Frame_Send. +*\*\fun Transmits break characters. +*\*\param UARTx : +*\*\ - UART1 +*\*\ - UART2 +*\*\return none +**/ +void UART_Break_Frame_Send(UART_Module* UARTx) +{ + /* Send break characters */ + UARTx->CTRL1 |= CTRL1_SDBRK_SET; +} + +/** +*\*\name UART_Half_Duplex_Enable. +*\*\fun Enables the UART's Half Duplex communication. +*\*\param UARTx : +*\*\ - UART1 +*\*\ - UART2 +*\*\return none +**/ +void UART_Half_Duplex_Enable(UART_Module* UARTx) +{ + /* Enable the Half-Duplex mode by setting the HDSEL bit in the CTRL3 register */ + UARTx->CTRL3 |= CTRL3_HDMEN_SET; +} + +/** +*\*\name UART_Half_Duplex_Disable. +*\*\fun Disables the UART's Half Duplex communication. +*\*\param UARTx : +*\*\ - UART1 +*\*\ - UART2 +*\*\return none +**/ +void UART_Half_Duplex_Disable(UART_Module* UARTx) +{ + /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CTRL3 register */ + UARTx->CTRL3 &= CTRL3_HDMEN_RESET; +} + +/** +*\*\name UART_Flag_Status_Get. +*\*\fun Checks whether the specified UART flag is set or not. +*\*\param UARTx : +*\*\ - UART1 +*\*\ - UART2 +*\*\param UART_flag : +*\*\ - UART_FLAG_TXDE +*\*\ - UART_FLAG_TXC +*\*\ - UART_FLAG_RXDNE +*\*\ - UART_FLAG_IDLEF +*\*\ - UART_FLAG_OREF +*\*\ - UART_FLAG_NEF +*\*\ - UART_FLAG_FEF +*\*\ - UART_FLAG_PEF +*\*\return SET or RESET +**/ +FlagStatus UART_Flag_Status_Get(UART_Module* UARTx, uint16_t UART_flag) +{ + if ((UARTx->STS & UART_flag) != (uint16_t)RESET) + { + return SET; + } + else + { + return RESET; + } +} + +/** +*\*\name UART_Flag_Clear. +*\*\fun Clears the UARTx's pending flags. +*\*\param UARTx : +*\*\ - UART1 +*\*\ - UART2 +*\*\param UART_flag : +*\*\ - UART_FLAG_TXC +*\*\ - UART_FLAG_RXDNE +*\*\return none +**/ +void UART_Flag_Clear(UART_Module* UARTx, uint16_t UART_flag) +{ + UARTx->STS = (uint16_t)~UART_flag; +} + +/** +*\*\name UART_Interrupt_Status_Get. +*\*\fun Checks whether the specified UART interrupt has occurred or not. +*\*\param UARTx : +*\*\ - UART1 +*\*\ - UART2 +*\*\param UART_interrupt : +*\*\ - UART_INT_TXDE +*\*\ - UART_INT_TXC +*\*\ - UART_INT_RXDNE +*\*\ - UART_INT_IDLEF +*\*\ - UART_INT_PEF +*\*\ - UART_INT_OREF +*\*\return SET or RESET +**/ +ITStatus UART_Interrupt_Status_Get(UART_Module* UARTx, uint16_t UART_interrupt) +{ + uint32_t bit_position = 0x00, temp_value = 0x00, register_value = 0x00; + + /* Get the UART register index */ + register_value = (((uint8_t)UART_interrupt) >> 0x5); + /* Get the interrupt position */ + temp_value = UART_interrupt & INT_MASK; + temp_value = (uint32_t)0x01 << temp_value; + + if (register_value == 0x01) /* The IT is in CTRL1 register */ + { + temp_value &= UARTx->CTRL1; + } + else if (register_value == 0x02) /* The IT is in CTRL2 register */ + { + temp_value &= UARTx->CTRL2; + } + else /* The IT is in CTRL3 register */ + { + temp_value &= UARTx->CTRL3; + } + + bit_position = UART_interrupt >> 0x8; + bit_position = (uint32_t)0x01 << bit_position; + bit_position &= UARTx->STS; + if ((temp_value != (uint16_t)RESET) && (bit_position != (uint16_t)RESET)) + { + return SET; + } + else + { + return RESET; + } +} + +/** +*\*\name UART_Interrupt_Status_Clear. +*\*\fun Clears the UARTx's interrupt Status. +*\*\param UARTx : +*\*\ - UART1 +*\*\ - UART2 +*\*\param UART_Interrupt : +*\*\ - UART_INT_TXC +*\*\ - UART_INT_RXDNE +*\*\return none +**/ +void UART_Interrupt_Status_Clear(UART_Module* UARTx, uint16_t UART_Interrupt) +{ + uint16_t bit_position = 0x00, temp_value = 0x00; + + bit_position = UART_Interrupt >> 0x8; + temp_value = ((uint16_t)0x01 << (uint16_t)bit_position); + UARTx->STS = (uint16_t)~temp_value; +} + + diff --git a/main.c b/main.c new file mode 100644 index 0000000..3cc4c6f --- /dev/null +++ b/main.c @@ -0,0 +1,134 @@ +/****************************************************************************** + * @file main.c + * @brief N32G003F5S7-STB 开发板 闪灯 + 调试串口打印示例 + * + * 硬件连接（原理图 N32G003F5S7-STB_V1.0.sch，目标 MCU 为 U1）： + * - 用户灯 D1：PA6(U1.16) -> 跳线 J16 -> D1 -> R1 -> GND， + * PA6 输出高电平点亮（需短接 J16 跳线帽）。 + * 可选：D2 接 PA7（跳线 J17）、D3 接 PA10（跳线 J18）。 + * - 调试串口（DEBUG USB）：UART1 TX = PA2(U1.6)、RX = PA3(U1.10)， + * 经 J5 跳线（7-8、9-10 短接）连到板载 Nu-Link 虚拟串口。 + * 参数：115200，8 数据位，无校验，1 停止位，无流控。 + * - 注意：N32G003 没有 DMA 外设，串口发送只能用查询/中断方式， + * 本程序采用查询方式发送。 + * 另外 PA8/PA9 与 SWDIO/SWCLK 双键合在同一封装引脚， + * 禁止用作普通 GPIO，否则 SWD 调试会断开。 + * + * 功能：主循环翻转 D1 闪烁，同时通过 printf 向调试串口打印 + * 循环计数（约每 0.8s 一行）。 + * + * 说明：系统时钟初始化 SystemInit() 由启动文件在进入 main 之前 + * 自动调用；printf 重定向依赖工程勾选 MicroLIB。 + *****************************************************************************/ +#include "n32g003.h" +#include + +/* 用户灯 D1 连接的引脚（详见板卡原理图），注意不要用 PA8/PA9（与 SWD 冲突） */ +#define LED_PORT GPIOA +#define LED_PIN GPIO_PIN_6 +#define LED_CLK RCC_APB_PERIPH_IOPA + +/* 调试串口：UART1，TX = PA2，RX = PA3（AF5，见用户手册表 5-7） */ +#define UARTx UART1 +#define UARTx_CLK RCC_APB_PERIPH_UART1 +#define UARTx_GPIO GPIOA +#define UARTx_TX_PIN GPIO_PIN_2 +#define UARTx_RX_PIN GPIO_PIN_3 +#define UARTx_GPIO_AF GPIO_AF5_UART1 +#define UARTx_BAUDRATE 115200u + +/* 循环计数器：调试时可在 Watch 窗口观察，确认程序正常运行 */ +static volatile uint32_t g_loop_count = 0; + +/** + * @brief 简单的软件延时（空指令循环） + * @param n 循环次数（默认 48MHz 主频下约 5000000 ≈ 0.4s，可按需调整） + */ +static void delay_loop(volatile uint32_t n) +{ + while (n--) { + __NOP(); + } +} + +/** + * @brief LED 引脚初始化：开时钟 + 推挽输出 + */ +static void led_init(void) +{ + GPIO_InitType gpio_init; + + RCC_APB_Peripheral_Clock_Enable(LED_CLK); + + GPIO_Structure_Initialize(&gpio_init); + gpio_init.Pin = LED_PIN; + gpio_init.GPIO_Mode = GPIO_MODE_OUT_PP; /* 推挽输出 */ + gpio_init.GPIO_Pull = GPIO_NO_PULL; + gpio_init.GPIO_Slew_Rate = GPIO_SLEW_RATE_FAST; + gpio_init.GPIO_Alternate = GPIO_NO_AF; + GPIO_Peripheral_Initialize(LED_PORT, &gpio_init); +} + +/** + * @brief 调试串口初始化：UART1，PA2(TX)/PA3(RX) 复用 AF5 + * 115200，8 数据位，无校验，1 停止位，无流控 + */ +static void uart_init(void) +{ + GPIO_InitType gpio_init; + UART_InitType uart_init; + + /* 开 GPIOA 和 UART1 时钟 */ + RCC_APB_Peripheral_Clock_Enable(RCC_APB_PERIPH_IOPA | UARTx_CLK); + + /* TX：复用推挽输出 */ + GPIO_Structure_Initialize(&gpio_init); + gpio_init.Pin = UARTx_TX_PIN; + gpio_init.GPIO_Mode = GPIO_MODE_AF_PP; + gpio_init.GPIO_Alternate = UARTx_GPIO_AF; + GPIO_Peripheral_Initialize(UARTx_GPIO, &gpio_init); + + /* RX：复用输入 */ + gpio_init.Pin = UARTx_RX_PIN; + gpio_init.GPIO_Mode = GPIO_MODE_INPUT; + gpio_init.GPIO_Alternate = UARTx_GPIO_AF; + GPIO_Peripheral_Initialize(UARTx_GPIO, &gpio_init); + + uart_init.BaudRate = UARTx_BAUDRATE; + uart_init.WordLength = UART_WL_8B; + uart_init.StopBits = UART_STPB_1; + uart_init.Parity = UART_PE_NO; + uart_init.Mode = UART_MODE_RX | UART_MODE_TX; + UART_Initializes(UARTx, &uart_init); + UART_Enable(UARTx); +} + +/** + * @brief 重定向 printf 到调试串口（查询方式发送，需勾选 MicroLIB） + */ +int fputc(int ch, FILE *f) +{ + (void)f; + UART_Data_Send(UARTx, (uint8_t)ch); + while (UART_Flag_Status_Get(UARTx, UART_FLAG_TXDE) == RESET) { + } + return ch; +} + +/** + * @brief 主函数 + */ +int main(void) +{ + led_init(); + uart_init(); + + printf("\r\nN32G003F5S7-STB: LED blink + UART printf demo\r\n"); + + while (1) { + GPIO_Pin_Toggle(LED_PORT, LED_PIN); /* 翻转 LED */ + g_loop_count++; /* 观察点：递增说明 CPU 正在运行 */ + printf("loop count = %u\r\n", (unsigned int)g_loop_count); + delay_loop(5000000u); + } +} diff --git a/test.map b/test.map new file mode 100644 index 0000000..04d0559 --- /dev/null +++ b/test.map @@ -0,0 +1,689 @@ +Component: ARM Compiler 6.14 Tool: armlink [5db06800] + +============================================================================== + +Section Cross References + + main.o(.text.main) refers to main.o(.text.delay_loop) for delay_loop + main.o(.text.main) refers to main.o(.bss.g_loop_count) for [Anonymous Symbol] + main.o(.ARM.exidx.text.main) refers to main.o(.text.main) for [Anonymous Symbol] + main.o(.ARM.exidx.text.delay_loop) refers to main.o(.text.delay_loop) for [Anonymous Symbol] + system_n32g003.o(.text.System_Initializes) refers to system_n32g003.o(.text.System_Clock_Set) for System_Clock_Set + system_n32g003.o(.ARM.exidx.text.System_Initializes) refers to system_n32g003.o(.text.System_Initializes) for [Anonymous Symbol] + system_n32g003.o(.text.System_Clock_Set) refers to system_n32g003.o(.text.Systeminit_Flash_Latency_Set) for Systeminit_Flash_Latency_Set + system_n32g003.o(.text.System_Clock_Set) refers to n32g003_rcc.o(.text.RCC_Sysclk_Config) for RCC_Sysclk_Config + system_n32g003.o(.ARM.exidx.text.System_Clock_Set) refers to system_n32g003.o(.text.System_Clock_Set) for [Anonymous Symbol] + system_n32g003.o(.text.System_Core_Clock_Frequency_Update) refers to aeabi_sdivfast.o(.text_divfast) for __aeabi_uidiv + system_n32g003.o(.text.System_Core_Clock_Frequency_Update) refers to system_n32g003.o(.data.SystemCoreClockFrequency) for SystemCoreClockFrequency + system_n32g003.o(.text.System_Core_Clock_Frequency_Update) refers to system_n32g003.o(.rodata.AHBPrescTable) for AHBPrescTable + system_n32g003.o(.ARM.exidx.text.System_Core_Clock_Frequency_Update) refers to system_n32g003.o(.text.System_Core_Clock_Frequency_Update) for [Anonymous Symbol] + system_n32g003.o(.ARM.exidx.text.Systeminit_Flash_Latency_Set) refers to system_n32g003.o(.text.Systeminit_Flash_Latency_Set) for [Anonymous Symbol] + n32g003_rcc.o(.ARM.exidx.text.RCC_Reset) refers to n32g003_rcc.o(.text.RCC_Reset) for [Anonymous Symbol] + n32g003_rcc.o(.ARM.exidx.text.RCC_HSI_Calibration_Value_Set) refers to n32g003_rcc.o(.text.RCC_HSI_Calibration_Value_Set) for [Anonymous Symbol] + n32g003_rcc.o(.ARM.exidx.text.RCC_LSI_Calibration_Value_Set) refers to n32g003_rcc.o(.text.RCC_LSI_Calibration_Value_Set) for [Anonymous Symbol] + n32g003_rcc.o(.ARM.exidx.text.RCC_Sysclk_Config) refers to n32g003_rcc.o(.text.RCC_Sysclk_Config) for [Anonymous Symbol] + n32g003_rcc.o(.ARM.exidx.text.RCC_Hclk_Config) refers to n32g003_rcc.o(.text.RCC_Hclk_Config) for [Anonymous Symbol] + n32g003_rcc.o(.ARM.exidx.text.RCC_Pclk_Config) refers to n32g003_rcc.o(.text.RCC_Pclk_Config) for [Anonymous Symbol] + n32g003_rcc.o(.ARM.exidx.text.RCC_TIM1_Clock_Config) refers to n32g003_rcc.o(.text.RCC_TIM1_Clock_Config) for [Anonymous Symbol] + n32g003_rcc.o(.ARM.exidx.text.RCC_ADC_1M_Clock_Config) refers to n32g003_rcc.o(.text.RCC_ADC_1M_Clock_Config) for [Anonymous Symbol] + n32g003_rcc.o(.ARM.exidx.text.RCC_ADC_Clock_Config) refers to n32g003_rcc.o(.text.RCC_ADC_Clock_Config) for [Anonymous Symbol] + n32g003_rcc.o(.ARM.exidx.text.RCC_TIM6_Clock_Config) refers to n32g003_rcc.o(.text.RCC_TIM6_Clock_Config) for [Anonymous Symbol] + n32g003_rcc.o(.text.RCC_Clocks_Frequencies_Value_Get) refers to aeabi_sdivfast.o(.text_divfast) for __aeabi_uidiv + n32g003_rcc.o(.text.RCC_Clocks_Frequencies_Value_Get) refers to n32g003_rcc.o(.rodata.ADCCLKPresTable) for [Anonymous Symbol] + n32g003_rcc.o(.text.RCC_Clocks_Frequencies_Value_Get) refers to n32g003_rcc.o(.rodata.ADC1MCLKPresTable) for [Anonymous Symbol] + n32g003_rcc.o(.text.RCC_Clocks_Frequencies_Value_Get) refers to n32g003_rcc.o(.rodata.AHBPresTable) for [Anonymous Symbol] + n32g003_rcc.o(.text.RCC_Clocks_Frequencies_Value_Get) refers to n32g003_rcc.o(.rodata.APBPresTable) for [Anonymous Symbol] + n32g003_rcc.o(.ARM.exidx.text.RCC_Clocks_Frequencies_Value_Get) refers to n32g003_rcc.o(.text.RCC_Clocks_Frequencies_Value_Get) for [Anonymous Symbol] + n32g003_rcc.o(.ARM.exidx.text.RCC_AHB_Peripheral_Clock_Enable) refers to n32g003_rcc.o(.text.RCC_AHB_Peripheral_Clock_Enable) for [Anonymous Symbol] + n32g003_rcc.o(.ARM.exidx.text.RCC_AHB_Peripheral_Clock_Disable) refers to n32g003_rcc.o(.text.RCC_AHB_Peripheral_Clock_Disable) for [Anonymous Symbol] + n32g003_rcc.o(.ARM.exidx.text.RCC_APB_Peripheral_Clock_Enable) refers to n32g003_rcc.o(.text.RCC_APB_Peripheral_Clock_Enable) for [Anonymous Symbol] + n32g003_rcc.o(.ARM.exidx.text.RCC_APB_Peripheral_Clock_Disable) refers to n32g003_rcc.o(.text.RCC_APB_Peripheral_Clock_Disable) for [Anonymous Symbol] + n32g003_rcc.o(.ARM.exidx.text.RCC_Peripheral_Reset) refers to n32g003_rcc.o(.text.RCC_Peripheral_Reset) for [Anonymous Symbol] + n32g003_rcc.o(.ARM.exidx.text.RCC_MCO_Prescaler_Config) refers to n32g003_rcc.o(.text.RCC_MCO_Prescaler_Config) for [Anonymous Symbol] + n32g003_rcc.o(.ARM.exidx.text.RCC_MCO_Source_Config) refers to n32g003_rcc.o(.text.RCC_MCO_Source_Config) for [Anonymous Symbol] + n32g003_rcc.o(.ARM.exidx.text.RCC_Flag_Status_Get) refers to n32g003_rcc.o(.text.RCC_Flag_Status_Get) for [Anonymous Symbol] + n32g003_rcc.o(.ARM.exidx.text.RCC_Reset_Flag_Clear) refers to n32g003_rcc.o(.text.RCC_Reset_Flag_Clear) for [Anonymous Symbol] + n32g003_rcc.o(.ARM.exidx.text.RCC_EMC_Reset_Disable) refers to n32g003_rcc.o(.text.RCC_EMC_Reset_Disable) for [Anonymous Symbol] + n32g003_rcc.o(.ARM.exidx.text.RCC_EMC_Reset_Enable) refers to n32g003_rcc.o(.text.RCC_EMC_Reset_Enable) for [Anonymous Symbol] + n32g003_rcc.o(.ARM.exidx.text.RCC_EMC_Detect_Disable) refers to n32g003_rcc.o(.text.RCC_EMC_Detect_Disable) for [Anonymous Symbol] + n32g003_rcc.o(.ARM.exidx.text.RCC_EMC_Detect_Enable) refers to n32g003_rcc.o(.text.RCC_EMC_Detect_Enable) for [Anonymous Symbol] + n32g003_rcc.o(.ARM.exidx.text.RCC_LSI_Detect_Disable) refers to n32g003_rcc.o(.text.RCC_LSI_Detect_Disable) for [Anonymous Symbol] + n32g003_rcc.o(.ARM.exidx.text.RCC_LSI_Detect_Enable) refers to n32g003_rcc.o(.text.RCC_LSI_Detect_Enable) for [Anonymous Symbol] + n32g003_rcc.o(.ARM.exidx.text.RCC_LSI_Clocks_Frequencies_Get) refers to n32g003_rcc.o(.text.RCC_LSI_Clocks_Frequencies_Get) for [Anonymous Symbol] + startup_n32g003.o(STACK) refers (Special) to heapauxi.o(.text) for __use_two_region_memory + startup_n32g003.o(HEAP) refers (Special) to heapauxi.o(.text) for __use_two_region_memory + startup_n32g003.o(RESET) refers (Special) to heapauxi.o(.text) for __use_two_region_memory + startup_n32g003.o(RESET) refers to startup_n32g003.o(STACK) for __initial_sp + startup_n32g003.o(RESET) refers to startup_n32g003.o(.text) for Reset_Handler + startup_n32g003.o(.text) refers (Special) to heapauxi.o(.text) for __use_two_region_memory + startup_n32g003.o(.text) refers to system_n32g003.o(.text.System_Initializes) for System_Initializes + startup_n32g003.o(.text) refers to __main.o(!!!main) for __main + startup_n32g003.o(.text) refers to startup_n32g003.o(HEAP) for Heap_Mem + startup_n32g003.o(.text) refers to startup_n32g003.o(STACK) for Stack_Mem + __main.o(!!!main) refers to __rtentry.o(.ARM.Collect$$rtentry$$00000000) for __rt_entry + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) for __rt_entry_li + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) for __rt_entry_main + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000C) for __rt_entry_postli_1 + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$00000009) for __rt_entry_postsh_1 + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$00000002) for __rt_entry_presh_1 + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry4.o(.ARM.Collect$$rtentry$$00000004) for __rt_entry_sh + aeabi_idiv0_sigfpe.o(.text) refers to rt_div0.o(.text) for __rt_div0 + __rtentry2.o(.ARM.Collect$$rtentry$$00000008) refers to boardinit2.o(.text) for _platform_post_stackheap_init + __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) refers to libinit.o(.ARM.Collect$$libinit$$00000000) for __rt_lib_init + __rtentry2.o(.ARM.Collect$$rtentry$$0000000B) refers to boardinit3.o(.text) for _platform_post_lib_init + __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) refers to main.o(.text.main) for main + __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) refers to exit.o(.text) for exit + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$00000001) for .ARM.Collect$$rtentry$$00000001 + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$00000008) for .ARM.Collect$$rtentry$$00000008 + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) for .ARM.Collect$$rtentry$$0000000A + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000B) for .ARM.Collect$$rtentry$$0000000B + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) for .ARM.Collect$$rtentry$$0000000D + __rtentry4.o(.ARM.Collect$$rtentry$$00000004) refers to sys_stackheap_outer.o(.text) for __user_setup_stackheap + __rtentry4.o(.ARM.exidx) refers to __rtentry4.o(.ARM.Collect$$rtentry$$00000004) for .ARM.Collect$$rtentry$$00000004 + rt_div0.o(.text) refers to defsig_fpe_outer.o(.text) for __rt_SIGFPE + sys_stackheap_outer.o(.text) refers to libspace.o(.text) for __user_perproc_libspace + sys_stackheap_outer.o(.text) refers to startup_n32g003.o(.text) for __user_initial_stackheap + sys_stackheap_outer.o(__vectab_stack_and_reset_area) refers to tempstk.o(.text) for __temporary_stack_top + sys_stackheap_outer.o(__vectab_stack_and_reset_area) refers to __main.o(!!!main) for __main + exit.o(.text) refers to rtexit.o(.ARM.Collect$$rtexit$$00000000) for __rt_exit + defsig_fpe_outer.o(.text) refers to defsig_fpe_inner.o(.text) for __rt_SIGFPE_inner + defsig_fpe_outer.o(.text) refers to defsig_exit.o(.text) for __sig_exit + defsig_fpe_formal.o(.text) refers to rt_raise.o(.text) for __rt_raise + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000002E) for __rt_lib_init_alloca_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000002C) for __rt_lib_init_argv_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001B) for __rt_lib_init_atexit_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000021) for __rt_lib_init_clock_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000032) for __rt_lib_init_cpp_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000030) for __rt_lib_init_exceptions_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000002) for __rt_lib_init_fp_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001F) for __rt_lib_init_fp_trap_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000023) for __rt_lib_init_getenv_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000A) for __rt_lib_init_heap_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000011) for __rt_lib_init_lc_collate_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000013) for __rt_lib_init_lc_ctype_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000015) for __rt_lib_init_lc_monetary_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000017) for __rt_lib_init_lc_numeric_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000019) for __rt_lib_init_lc_time_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000004) for __rt_lib_init_preinit_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000E) for __rt_lib_init_rand_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000033) for __rt_lib_init_return + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001D) for __rt_lib_init_signal_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000025) for __rt_lib_init_stdio_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000C) for __rt_lib_init_user_alloc_1 + libspace.o(.text) refers to libspace.o(.bss) for __libspace_start + rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for __rt_exit_exit + rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for __rt_exit_ls + rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000002) for __rt_exit_prels_1 + rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for __rt_exit_exit + rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for __rt_exit_ls + rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000002) for __rt_exit_prels_1 + rtexit.o(.ARM.exidx) refers to rtexit.o(.ARM.Collect$$rtexit$$00000000) for .ARM.Collect$$rtexit$$00000000 + rt_raise.o(.text) refers to __raise.o(.text) for __raise + rt_raise.o(.text) refers to sys_exit.o(.text) for _sys_exit + defsig_exit.o(.text) refers to sys_exit.o(.text) for _sys_exit + defsig_fpe_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + libinit2.o(.ARM.Collect$$libinit$$00000010) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F + libinit2.o(.ARM.Collect$$libinit$$00000012) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F + libinit2.o(.ARM.Collect$$libinit$$00000014) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F + libinit2.o(.ARM.Collect$$libinit$$00000016) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F + libinit2.o(.ARM.Collect$$libinit$$00000018) refers to libinit2.o(.ARM.Collect$$libinit$$0000000F) for .ARM.Collect$$libinit$$0000000F + libinit2.o(.ARM.Collect$$libinit$$00000026) refers to argv_veneer.o(.text) for __ARM_argv_veneer + libinit2.o(.ARM.Collect$$libinit$$00000027) refers to argv_veneer.o(.text) for __ARM_argv_veneer + sys_exit.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting + sys_exit.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function + sys_exit_hlt.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting + sys_exit_hlt.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function + rtexit2.o(.ARM.Collect$$rtexit$$00000003) refers to libshutdown.o(.ARM.Collect$$libshutdown$$00000000) for __rt_lib_shutdown + rtexit2.o(.ARM.Collect$$rtexit$$00000004) refers to sys_exit.o(.text) for _sys_exit + rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000001) for .ARM.Collect$$rtexit$$00000001 + rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for .ARM.Collect$$rtexit$$00000003 + rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for .ARM.Collect$$rtexit$$00000004 + __raise.o(.text) refers to defsig.o(CL$$defsig) for __default_signal_handler + defsig_general.o(.text) refers to sys_wrch.o(.text) for _ttywrch + sys_wrch.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting + sys_wrch.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function + sys_wrch_hlt.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting + sys_wrch_hlt.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function + defsig.o(CL$$defsig) refers to defsig_fpe_inner.o(.text) for __rt_SIGFPE_inner + defsig.o(CL$$defsig) refers to defsig_rtmem_inner.o(.text) for __rt_SIGRTMEM_inner + _get_argv_nomalloc.o(.text) refers (Special) to hrguard.o(.text) for __heap_region$guard + _get_argv_nomalloc.o(.text) refers to defsig_rtmem_outer.o(.text) for __rt_SIGRTMEM + _get_argv_nomalloc.o(.text) refers to sys_command.o(.text) for _sys_command_string + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000002) for __rt_lib_shutdown_cpp_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000007) for __rt_lib_shutdown_fp_trap_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000F) for __rt_lib_shutdown_heap_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000010) for __rt_lib_shutdown_return + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000A) for __rt_lib_shutdown_signal_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000004) for __rt_lib_shutdown_stdio_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C) for __rt_lib_shutdown_user_alloc_1 + sys_command.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting + sys_command.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function + sys_command_hlt.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting + sys_command_hlt.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function + defsig_abrt_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_rtred_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_rtmem_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_rtmem_outer.o(.text) refers to defsig_rtmem_inner.o(.text) for __rt_SIGRTMEM_inner + defsig_rtmem_outer.o(.text) refers to defsig_exit.o(.text) for __sig_exit + defsig_rtmem_formal.o(.text) refers to rt_raise.o(.text) for __rt_raise + defsig_stak_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_pvfn_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_cppl_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_segv_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_other.o(.text) refers to defsig_general.o(.text) for __default_signal_display + + +============================================================================== + +Removing Unused input sections from the image. + + Removing main.o(.text), (0 bytes). + Removing main.o(.ARM.exidx.text.main), (8 bytes). + Removing main.o(.ARM.exidx.text.delay_loop), (8 bytes). + Removing main.o(.ARM.use_no_argv), (4 bytes). + Removing system_n32g003.o(.text), (0 bytes). + Removing system_n32g003.o(.ARM.exidx.text.System_Initializes), (8 bytes). + Removing system_n32g003.o(.ARM.exidx.text.System_Clock_Set), (8 bytes). + Removing system_n32g003.o(.text.System_Core_Clock_Frequency_Update), (116 bytes). + Removing system_n32g003.o(.ARM.exidx.text.System_Core_Clock_Frequency_Update), (8 bytes). + Removing system_n32g003.o(.ARM.exidx.text.Systeminit_Flash_Latency_Set), (8 bytes). + Removing system_n32g003.o(.data.SystemCoreClockFrequency), (4 bytes). + Removing system_n32g003.o(.rodata.AHBPrescTable), (16 bytes). + Removing n32g003_rcc.o(.text), (0 bytes). + Removing n32g003_rcc.o(.text.RCC_Reset), (64 bytes). + Removing n32g003_rcc.o(.ARM.exidx.text.RCC_Reset), (8 bytes). + Removing n32g003_rcc.o(.text.RCC_HSI_Calibration_Value_Set), (20 bytes). + Removing n32g003_rcc.o(.ARM.exidx.text.RCC_HSI_Calibration_Value_Set), (8 bytes). + Removing n32g003_rcc.o(.text.RCC_LSI_Calibration_Value_Set), (20 bytes). + Removing n32g003_rcc.o(.ARM.exidx.text.RCC_LSI_Calibration_Value_Set), (8 bytes). + Removing n32g003_rcc.o(.ARM.exidx.text.RCC_Sysclk_Config), (8 bytes). + Removing n32g003_rcc.o(.text.RCC_Hclk_Config), (20 bytes). + Removing n32g003_rcc.o(.ARM.exidx.text.RCC_Hclk_Config), (8 bytes). + Removing n32g003_rcc.o(.text.RCC_Pclk_Config), (20 bytes). + Removing n32g003_rcc.o(.ARM.exidx.text.RCC_Pclk_Config), (8 bytes). + Removing n32g003_rcc.o(.text.RCC_TIM1_Clock_Config), (20 bytes). + Removing n32g003_rcc.o(.ARM.exidx.text.RCC_TIM1_Clock_Config), (8 bytes). + Removing n32g003_rcc.o(.text.RCC_ADC_1M_Clock_Config), (20 bytes). + Removing n32g003_rcc.o(.ARM.exidx.text.RCC_ADC_1M_Clock_Config), (8 bytes). + Removing n32g003_rcc.o(.text.RCC_ADC_Clock_Config), (20 bytes). + Removing n32g003_rcc.o(.ARM.exidx.text.RCC_ADC_Clock_Config), (8 bytes). + Removing n32g003_rcc.o(.text.RCC_TIM6_Clock_Config), (20 bytes). + Removing n32g003_rcc.o(.ARM.exidx.text.RCC_TIM6_Clock_Config), (8 bytes). + Removing n32g003_rcc.o(.text.RCC_Clocks_Frequencies_Value_Get), (200 bytes). + Removing n32g003_rcc.o(.ARM.exidx.text.RCC_Clocks_Frequencies_Value_Get), (8 bytes). + Removing n32g003_rcc.o(.text.RCC_AHB_Peripheral_Clock_Enable), (16 bytes). + Removing n32g003_rcc.o(.ARM.exidx.text.RCC_AHB_Peripheral_Clock_Enable), (8 bytes). + Removing n32g003_rcc.o(.text.RCC_AHB_Peripheral_Clock_Disable), (16 bytes). + Removing n32g003_rcc.o(.ARM.exidx.text.RCC_AHB_Peripheral_Clock_Disable), (8 bytes). + Removing n32g003_rcc.o(.text.RCC_APB_Peripheral_Clock_Enable), (16 bytes). + Removing n32g003_rcc.o(.ARM.exidx.text.RCC_APB_Peripheral_Clock_Enable), (8 bytes). + Removing n32g003_rcc.o(.text.RCC_APB_Peripheral_Clock_Disable), (16 bytes). + Removing n32g003_rcc.o(.ARM.exidx.text.RCC_APB_Peripheral_Clock_Disable), (8 bytes). + Removing n32g003_rcc.o(.text.RCC_Peripheral_Reset), (20 bytes). + Removing n32g003_rcc.o(.ARM.exidx.text.RCC_Peripheral_Reset), (8 bytes). + Removing n32g003_rcc.o(.text.RCC_MCO_Prescaler_Config), (20 bytes). + Removing n32g003_rcc.o(.ARM.exidx.text.RCC_MCO_Prescaler_Config), (8 bytes). + Removing n32g003_rcc.o(.text.RCC_MCO_Source_Config), (20 bytes). + Removing n32g003_rcc.o(.ARM.exidx.text.RCC_MCO_Source_Config), (8 bytes). + Removing n32g003_rcc.o(.text.RCC_Flag_Status_Get), (36 bytes). + Removing n32g003_rcc.o(.ARM.exidx.text.RCC_Flag_Status_Get), (8 bytes). + Removing n32g003_rcc.o(.text.RCC_Reset_Flag_Clear), (24 bytes). + Removing n32g003_rcc.o(.ARM.exidx.text.RCC_Reset_Flag_Clear), (8 bytes). + Removing n32g003_rcc.o(.text.RCC_EMC_Reset_Disable), (20 bytes). + Removing n32g003_rcc.o(.ARM.exidx.text.RCC_EMC_Reset_Disable), (8 bytes). + Removing n32g003_rcc.o(.text.RCC_EMC_Reset_Enable), (20 bytes). + Removing n32g003_rcc.o(.ARM.exidx.text.RCC_EMC_Reset_Enable), (8 bytes). + Removing n32g003_rcc.o(.text.RCC_EMC_Detect_Disable), (16 bytes). + Removing n32g003_rcc.o(.ARM.exidx.text.RCC_EMC_Detect_Disable), (8 bytes). + Removing n32g003_rcc.o(.text.RCC_EMC_Detect_Enable), (16 bytes). + Removing n32g003_rcc.o(.ARM.exidx.text.RCC_EMC_Detect_Enable), (8 bytes). + Removing n32g003_rcc.o(.text.RCC_LSI_Detect_Disable), (16 bytes). + Removing n32g003_rcc.o(.ARM.exidx.text.RCC_LSI_Detect_Disable), (8 bytes). + Removing n32g003_rcc.o(.text.RCC_LSI_Detect_Enable), (16 bytes). + Removing n32g003_rcc.o(.ARM.exidx.text.RCC_LSI_Detect_Enable), (8 bytes). + Removing n32g003_rcc.o(.text.RCC_LSI_Clocks_Frequencies_Get), (16 bytes). + Removing n32g003_rcc.o(.ARM.exidx.text.RCC_LSI_Clocks_Frequencies_Get), (8 bytes). + Removing n32g003_rcc.o(.rodata.ADCCLKPresTable), (16 bytes). + Removing n32g003_rcc.o(.rodata.ADC1MCLKPresTable), (4 bytes). + Removing n32g003_rcc.o(.rodata.AHBPresTable), (16 bytes). + Removing n32g003_rcc.o(.rodata.APBPresTable), (8 bytes). + +70 unused section(s) (total 1176 bytes) removed from the image. + +============================================================================== + +Image Symbol Table + + Local Symbols + + Symbol Name Value Ov Type Size Object(Section) + + ../clib/angel/boardlib.s 0x00000000 Number 0 boardinit1.o ABSOLUTE + ../clib/angel/boardlib.s 0x00000000 Number 0 boardinit2.o ABSOLUTE + ../clib/angel/boardlib.s 0x00000000 Number 0 boardinit3.o ABSOLUTE + ../clib/angel/boardlib.s 0x00000000 Number 0 boardshut.o ABSOLUTE + ../clib/angel/handlers.s 0x00000000 Number 0 __scatter_zi.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 __rtentry.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 __rtentry2.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 __rtentry4.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 rtexit.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 rtexit2.o ABSOLUTE + ../clib/angel/rt.s 0x00000000 Number 0 aeabi_idiv0.o ABSOLUTE + ../clib/angel/rt.s 0x00000000 Number 0 aeabi_idiv0_sigfpe.o ABSOLUTE + ../clib/angel/rt.s 0x00000000 Number 0 rt_div0.o ABSOLUTE + ../clib/angel/rt.s 0x00000000 Number 0 rt_raise.o ABSOLUTE + ../clib/angel/scatterp.s 0x00000000 Number 0 __scatter.o ABSOLUTE + ../clib/angel/startup.s 0x00000000 Number 0 __main.o ABSOLUTE + ../clib/angel/sys.s 0x00000000 Number 0 sys_stackheap_outer.o ABSOLUTE + ../clib/angel/sys.s 0x00000000 Number 0 libspace.o ABSOLUTE + ../clib/angel/sys.s 0x00000000 Number 0 tempstk.o ABSOLUTE + ../clib/angel/sys.s 0x00000000 Number 0 use_no_semi.o ABSOLUTE + ../clib/angel/sys.s 0x00000000 Number 0 indicate_semi.o ABSOLUTE + ../clib/angel/sysapp.c 0x00000000 Number 0 sys_exit.o ABSOLUTE + ../clib/angel/sysapp.c 0x00000000 Number 0 sys_exit_hlt.o ABSOLUTE + ../clib/angel/sysapp.c 0x00000000 Number 0 sys_wrch.o ABSOLUTE + ../clib/angel/sysapp.c 0x00000000 Number 0 sys_wrch_hlt.o ABSOLUTE + ../clib/angel/sysapp.c 0x00000000 Number 0 sys_command.o ABSOLUTE + ../clib/angel/sysapp.c 0x00000000 Number 0 sys_command_hlt.o ABSOLUTE + ../clib/armsys.c 0x00000000 Number 0 argv_veneer.o ABSOLUTE + ../clib/armsys.c 0x00000000 Number 0 _get_argv_nomalloc.o ABSOLUTE + ../clib/armsys.c 0x00000000 Number 0 no_argv.o ABSOLUTE + ../clib/division.s 0x00000000 Number 0 aeabi_sdivfast.o ABSOLUTE + ../clib/division.s 0x00000000 Number 0 aeabi_sdivfast_div0.o ABSOLUTE + ../clib/heapalloc.c 0x00000000 Number 0 hrguard.o ABSOLUTE + ../clib/heapaux.c 0x00000000 Number 0 heapauxi.o ABSOLUTE + ../clib/libinit.s 0x00000000 Number 0 libinit.o ABSOLUTE + ../clib/libinit.s 0x00000000 Number 0 libinit2.o ABSOLUTE + ../clib/libinit.s 0x00000000 Number 0 libshutdown.o ABSOLUTE + ../clib/libinit.s 0x00000000 Number 0 libshutdown2.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_fpe_outer.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_fpe_formal.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_exit.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_fpe_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 __raise.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_general.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_abrt_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_rtred_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_rtmem_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_rtmem_outer.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_rtmem_formal.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_stak_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_pvfn_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_cppl_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_segv_inner.o ABSOLUTE + ../clib/signal.c 0x00000000 Number 0 defsig_other.o ABSOLUTE + ../clib/signal.s 0x00000000 Number 0 defsig.o ABSOLUTE + ../clib/stdlib.c 0x00000000 Number 0 exit.o ABSOLUTE + ../fplib/cfplib/fpinit.c 0x00000000 Number 0 fpinit.o ABSOLUTE + dc.s 0x00000000 Number 0 dc.o ABSOLUTE + firmware/CMSIS/device/startup/startup_n32g003.s 0x00000000 Number 0 startup_n32g003.o ABSOLUTE + main.c 0x00000000 Number 0 main.o ABSOLUTE + n32g003_rcc.c 0x00000000 Number 0 n32g003_rcc.o ABSOLUTE + system_n32g003.c 0x00000000 Number 0 system_n32g003.o ABSOLUTE + RESET 0x08000000 Section 128 startup_n32g003.o(RESET) + !!!main 0x08000080 Section 8 __main.o(!!!main) + !!!scatter 0x08000088 Section 60 __scatter.o(!!!scatter) + !!handler_zi 0x080000c4 Section 28 __scatter_zi.o(!!handler_zi) + .ARM.Collect$$libinit$$00000000 0x080000e0 Section 2 libinit.o(.ARM.Collect$$libinit$$00000000) + .ARM.Collect$$libinit$$00000002 0x080000e2 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000002) + .ARM.Collect$$libinit$$00000004 0x080000e2 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000004) + .ARM.Collect$$libinit$$0000000A 0x080000e2 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000000A) + .ARM.Collect$$libinit$$0000000C 0x080000e2 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000000C) + .ARM.Collect$$libinit$$0000000E 0x080000e2 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000000E) + .ARM.Collect$$libinit$$00000011 0x080000e2 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000011) + .ARM.Collect$$libinit$$00000013 0x080000e2 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000013) + .ARM.Collect$$libinit$$00000015 0x080000e2 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000015) + .ARM.Collect$$libinit$$00000017 0x080000e2 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000017) + .ARM.Collect$$libinit$$00000019 0x080000e2 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000019) + .ARM.Collect$$libinit$$0000001B 0x080000e2 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000001B) + .ARM.Collect$$libinit$$0000001D 0x080000e2 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000001D) + .ARM.Collect$$libinit$$0000001F 0x080000e2 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000001F) + .ARM.Collect$$libinit$$00000021 0x080000e2 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000021) + .ARM.Collect$$libinit$$00000023 0x080000e2 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000023) + .ARM.Collect$$libinit$$00000025 0x080000e2 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000025) + .ARM.Collect$$libinit$$0000002C 0x080000e2 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000002C) + .ARM.Collect$$libinit$$0000002E 0x080000e2 Section 0 libinit2.o(.ARM.Collect$$libinit$$0000002E) + .ARM.Collect$$libinit$$00000030 0x080000e2 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000030) + .ARM.Collect$$libinit$$00000032 0x080000e2 Section 0 libinit2.o(.ARM.Collect$$libinit$$00000032) + .ARM.Collect$$libinit$$00000033 0x080000e2 Section 2 libinit2.o(.ARM.Collect$$libinit$$00000033) + .ARM.Collect$$libshutdown$$00000000 0x080000e4 Section 2 libshutdown.o(.ARM.Collect$$libshutdown$$00000000) + .ARM.Collect$$libshutdown$$00000002 0x080000e6 Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000002) + .ARM.Collect$$libshutdown$$00000004 0x080000e6 Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000004) + .ARM.Collect$$libshutdown$$00000007 0x080000e6 Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000007) + .ARM.Collect$$libshutdown$$0000000A 0x080000e6 Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000A) + .ARM.Collect$$libshutdown$$0000000C 0x080000e6 Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C) + .ARM.Collect$$libshutdown$$0000000F 0x080000e6 Section 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000F) + .ARM.Collect$$libshutdown$$00000010 0x080000e6 Section 2 libshutdown2.o(.ARM.Collect$$libshutdown$$00000010) + .ARM.Collect$$rtentry$$00000000 0x080000e8 Section 0 __rtentry.o(.ARM.Collect$$rtentry$$00000000) + .ARM.Collect$$rtentry$$00000002 0x080000e8 Section 0 __rtentry2.o(.ARM.Collect$$rtentry$$00000002) + .ARM.Collect$$rtentry$$00000004 0x080000e8 Section 6 __rtentry4.o(.ARM.Collect$$rtentry$$00000004) + .ARM.Collect$$rtentry$$00000009 0x080000ee Section 0 __rtentry2.o(.ARM.Collect$$rtentry$$00000009) + .ARM.Collect$$rtentry$$0000000A 0x080000ee Section 4 __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) + .ARM.Collect$$rtentry$$0000000C 0x080000f2 Section 0 __rtentry2.o(.ARM.Collect$$rtentry$$0000000C) + .ARM.Collect$$rtentry$$0000000D 0x080000f2 Section 8 __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) + .ARM.Collect$$rtexit$$00000000 0x080000fa Section 2 rtexit.o(.ARM.Collect$$rtexit$$00000000) + .ARM.Collect$$rtexit$$00000002 0x080000fc Section 0 rtexit2.o(.ARM.Collect$$rtexit$$00000002) + .ARM.Collect$$rtexit$$00000003 0x080000fc Section 4 rtexit2.o(.ARM.Collect$$rtexit$$00000003) + .ARM.Collect$$rtexit$$00000004 0x08000100 Section 6 rtexit2.o(.ARM.Collect$$rtexit$$00000004) + .text 0x08000108 Section 56 startup_n32g003.o(.text) + .text 0x08000140 Section 0 heapauxi.o(.text) + .text 0x08000146 Section 62 sys_stackheap_outer.o(.text) + .text 0x08000184 Section 0 exit.o(.text) + .text 0x08000194 Section 8 libspace.o(.text) + .text 0x0800019c Section 0 sys_exit.o(.text) + .text 0x080001a8 Section 2 use_no_semi.o(.text) + .text 0x080001aa Section 0 indicate_semi.o(.text) + [Anonymous Symbol] 0x080001ac Section 0 n32g003_rcc.o(.text.RCC_Sysclk_Config) + System_Clock_Set 0x080001bd Thumb Code 88 system_n32g003.o(.text.System_Clock_Set) + [Anonymous Symbol] 0x080001bc Section 0 system_n32g003.o(.text.System_Clock_Set) + [Anonymous Symbol] 0x08000214 Section 0 system_n32g003.o(.text.System_Initializes) + __arm_cp.0_0 0x08000264 Number 4 system_n32g003.o(.text.System_Initializes) + __arm_cp.0_1 0x08000268 Number 4 system_n32g003.o(.text.System_Initializes) + __arm_cp.0_2 0x0800026c Number 4 system_n32g003.o(.text.System_Initializes) + __arm_cp.0_3 0x08000270 Number 4 system_n32g003.o(.text.System_Initializes) + __arm_cp.0_4 0x08000274 Number 4 system_n32g003.o(.text.System_Initializes) + Systeminit_Flash_Latency_Set 0x08000279 Thumb Code 20 system_n32g003.o(.text.Systeminit_Flash_Latency_Set) + [Anonymous Symbol] 0x08000278 Section 0 system_n32g003.o(.text.Systeminit_Flash_Latency_Set) + __arm_cp.3_0 0x08000288 Number 4 system_n32g003.o(.text.Systeminit_Flash_Latency_Set) + delay_loop 0x0800028d Thumb Code 36 main.o(.text.delay_loop) + [Anonymous Symbol] 0x0800028c Section 0 main.o(.text.delay_loop) + __arm_cp.1_0 0x080002ac Number 4 main.o(.text.delay_loop) + [Anonymous Symbol] 0x080002b0 Section 0 main.o(.text.main) + __arm_cp.0_0 0x080002c4 Number 4 main.o(.text.main) + .bss 0x20000000 Section 96 libspace.o(.bss) + g_loop_count 0x20000060 Data 4 main.o(.bss.g_loop_count) + [Anonymous Symbol] 0x20000060 Section 0 main.o(.bss.g_loop_count) + Heap_Mem 0x20000068 Data 512 startup_n32g003.o(HEAP) + HEAP 0x20000068 Section 512 startup_n32g003.o(HEAP) + Stack_Mem 0x20000268 Data 1024 startup_n32g003.o(STACK) + STACK 0x20000268 Section 1024 startup_n32g003.o(STACK) + __initial_sp 0x20000668 Data 0 startup_n32g003.o(STACK) + + Global Symbols + + Symbol Name Value Ov Type Size Object(Section) + + BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$~IW$USESV6$~STKCKD$USESV7$~SHL$OTIME$ROPI$EBA8$UX$STANDARDLIB$REQ8$PRES8$EABIv2 0x00000000 Number 0 anon$$obj.o ABSOLUTE + __ARM_exceptions_init - Undefined Weak Reference + __alloca_initialize - Undefined Weak Reference + __arm_preinit_ - Undefined Weak Reference + __cpp_initialize__aeabi_ - Undefined Weak Reference + __cxa_finalize - Undefined Weak Reference + __rt_locale - Undefined Weak Reference + __sigvec_lookup - Undefined Weak Reference + _atexit_init - Undefined Weak Reference + _call_atexit_fns - Undefined Weak Reference + _clock_init - Undefined Weak Reference + _fp_trap_init - Undefined Weak Reference + _fp_trap_shutdown - Undefined Weak Reference + _get_lc_collate - Undefined Weak Reference + _get_lc_ctype - Undefined Weak Reference + _get_lc_monetary - Undefined Weak Reference + _get_lc_numeric - Undefined Weak Reference + _get_lc_time - Undefined Weak Reference + _getenv_init - Undefined Weak Reference + _handle_redirection - Undefined Weak Reference + _init_alloc - Undefined Weak Reference + _init_user_alloc - Undefined Weak Reference + _initio - Undefined Weak Reference + _rand_init - Undefined Weak Reference + _signal_finish - Undefined Weak Reference + _signal_init - Undefined Weak Reference + _terminate_alloc - Undefined Weak Reference + _terminate_user_alloc - Undefined Weak Reference + _terminateio - Undefined Weak Reference + __Vectors_Size 0x00000080 Number 0 startup_n32g003.o ABSOLUTE + __Vectors 0x08000000 Data 4 startup_n32g003.o(RESET) + __Vectors_End 0x08000080 Data 0 startup_n32g003.o(RESET) + __main 0x08000081 Thumb Code 8 __main.o(!!!main) + __scatterload 0x08000089 Thumb Code 0 __scatter.o(!!!scatter) + __scatterload_rt2 0x08000089 Thumb Code 52 __scatter.o(!!!scatter) + __scatterload_rt2_thumb_only 0x08000089 Thumb Code 0 __scatter.o(!!!scatter) + __scatterload_null 0x08000099 Thumb Code 0 __scatter.o(!!!scatter) + __scatterload_zeroinit 0x080000c5 Thumb Code 28 __scatter_zi.o(!!handler_zi) + __rt_lib_init 0x080000e1 Thumb Code 0 libinit.o(.ARM.Collect$$libinit$$00000000) + __rt_lib_init_alloca_1 0x080000e3 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000002E) + __rt_lib_init_argv_1 0x080000e3 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000002C) + __rt_lib_init_atexit_1 0x080000e3 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000001B) + __rt_lib_init_clock_1 0x080000e3 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000021) + __rt_lib_init_cpp_1 0x080000e3 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000032) + __rt_lib_init_exceptions_1 0x080000e3 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000030) + __rt_lib_init_fp_1 0x080000e3 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000002) + __rt_lib_init_fp_trap_1 0x080000e3 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000001F) + __rt_lib_init_getenv_1 0x080000e3 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000023) + __rt_lib_init_heap_1 0x080000e3 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000000A) + __rt_lib_init_lc_collate_1 0x080000e3 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000011) + __rt_lib_init_lc_ctype_1 0x080000e3 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000013) + __rt_lib_init_lc_monetary_1 0x080000e3 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000015) + __rt_lib_init_lc_numeric_1 0x080000e3 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000017) + __rt_lib_init_lc_time_1 0x080000e3 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000019) + __rt_lib_init_preinit_1 0x080000e3 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000004) + __rt_lib_init_rand_1 0x080000e3 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000000E) + __rt_lib_init_return 0x080000e3 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000033) + __rt_lib_init_signal_1 0x080000e3 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000001D) + __rt_lib_init_stdio_1 0x080000e3 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000025) + __rt_lib_init_user_alloc_1 0x080000e3 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000000C) + __rt_lib_shutdown 0x080000e5 Thumb Code 0 libshutdown.o(.ARM.Collect$$libshutdown$$00000000) + __rt_lib_shutdown_cpp_1 0x080000e7 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000002) + __rt_lib_shutdown_fp_trap_1 0x080000e7 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000007) + __rt_lib_shutdown_heap_1 0x080000e7 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000F) + __rt_lib_shutdown_return 0x080000e7 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000010) + __rt_lib_shutdown_signal_1 0x080000e7 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000A) + __rt_lib_shutdown_stdio_1 0x080000e7 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000004) + __rt_lib_shutdown_user_alloc_1 0x080000e7 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C) + __rt_entry 0x080000e9 Thumb Code 0 __rtentry.o(.ARM.Collect$$rtentry$$00000000) + __rt_entry_presh_1 0x080000e9 Thumb Code 0 __rtentry2.o(.ARM.Collect$$rtentry$$00000002) + __rt_entry_sh 0x080000e9 Thumb Code 0 __rtentry4.o(.ARM.Collect$$rtentry$$00000004) + __rt_entry_li 0x080000ef Thumb Code 0 __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) + __rt_entry_postsh_1 0x080000ef Thumb Code 0 __rtentry2.o(.ARM.Collect$$rtentry$$00000009) + __rt_entry_main 0x080000f3 Thumb Code 0 __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) + __rt_entry_postli_1 0x080000f3 Thumb Code 0 __rtentry2.o(.ARM.Collect$$rtentry$$0000000C) + __rt_exit 0x080000fb Thumb Code 0 rtexit.o(.ARM.Collect$$rtexit$$00000000) + __rt_exit_ls 0x080000fd Thumb Code 0 rtexit2.o(.ARM.Collect$$rtexit$$00000003) + __rt_exit_prels_1 0x080000fd Thumb Code 0 rtexit2.o(.ARM.Collect$$rtexit$$00000002) + __rt_exit_exit 0x08000101 Thumb Code 0 rtexit2.o(.ARM.Collect$$rtexit$$00000004) + Reset_Handler 0x08000109 Thumb Code 8 startup_n32g003.o(.text) + NMI_Handler 0x08000111 Thumb Code 2 startup_n32g003.o(.text) + HardFault_Handler 0x08000113 Thumb Code 2 startup_n32g003.o(.text) + SVC_Handler 0x08000115 Thumb Code 2 startup_n32g003.o(.text) + PendSV_Handler 0x08000117 Thumb Code 2 startup_n32g003.o(.text) + SysTick_Handler 0x08000119 Thumb Code 2 startup_n32g003.o(.text) + ADC_IRQHandler 0x0800011b Thumb Code 0 startup_n32g003.o(.text) + COMP_IRQHandler 0x0800011b Thumb Code 0 startup_n32g003.o(.text) + EXTI0_1_IRQHandler 0x0800011b Thumb Code 0 startup_n32g003.o(.text) + EXTI2_3_IRQHandler 0x0800011b Thumb Code 0 startup_n32g003.o(.text) + EXTI4_17_IRQHandler 0x0800011b Thumb Code 0 startup_n32g003.o(.text) + FLASH_IRQHandler 0x0800011b Thumb Code 0 startup_n32g003.o(.text) + I2C_ER_IRQHandler 0x0800011b Thumb Code 0 startup_n32g003.o(.text) + I2C_EV_IRQHandler 0x0800011b Thumb Code 0 startup_n32g003.o(.text) + PVD_IRQHandler 0x0800011b Thumb Code 0 startup_n32g003.o(.text) + SPI_IRQHandler 0x0800011b Thumb Code 0 startup_n32g003.o(.text) + TIM1_BRK_UP_TRG_COM_IRQHandler 0x0800011b Thumb Code 0 startup_n32g003.o(.text) + TIM1_CC_IRQHandler 0x0800011b Thumb Code 0 startup_n32g003.o(.text) + TIM3_IRQHandler 0x0800011b Thumb Code 0 startup_n32g003.o(.text) + TIM6_IRQHandler 0x0800011b Thumb Code 0 startup_n32g003.o(.text) + UART1_IRQHandler 0x0800011b Thumb Code 0 startup_n32g003.o(.text) + UART2_IRQHandler 0x0800011b Thumb Code 0 startup_n32g003.o(.text) + __user_initial_stackheap 0x0800011d Thumb Code 0 startup_n32g003.o(.text) + __use_two_region_memory 0x08000141 Thumb Code 2 heapauxi.o(.text) + __rt_heap_escrow$2region 0x08000143 Thumb Code 2 heapauxi.o(.text) + __rt_heap_expand$2region 0x08000145 Thumb Code 2 heapauxi.o(.text) + __user_setup_stackheap 0x08000147 Thumb Code 62 sys_stackheap_outer.o(.text) + exit 0x08000185 Thumb Code 16 exit.o(.text) + __user_libspace 0x08000195 Thumb Code 8 libspace.o(.text) + __user_perproc_libspace 0x08000195 Thumb Code 0 libspace.o(.text) + __user_perthread_libspace 0x08000195 Thumb Code 0 libspace.o(.text) + _sys_exit 0x0800019d Thumb Code 8 sys_exit.o(.text) + __I$use$semihosting 0x080001a9 Thumb Code 0 use_no_semi.o(.text) + __use_no_semihosting_swi 0x080001a9 Thumb Code 2 use_no_semi.o(.text) + __semihosting_library_function 0x080001ab Thumb Code 0 indicate_semi.o(.text) + RCC_Sysclk_Config 0x080001ad Thumb Code 16 n32g003_rcc.o(.text.RCC_Sysclk_Config) + System_Initializes 0x08000215 Thumb Code 100 system_n32g003.o(.text.System_Initializes) + main 0x080002b1 Thumb Code 24 main.o(.text.main) + Region$$Table$$Base 0x080002c8 Number 0 anon$$obj.o(Region$$Table) + Region$$Table$$Limit 0x080002d8 Number 0 anon$$obj.o(Region$$Table) + __libspace_start 0x20000000 Data 96 libspace.o(.bss) + __temporary_stack_top$libspace 0x20000060 Data 0 libspace.o(.bss) + + + +============================================================================== + +Memory Map of the image + + Image Entry point : 0x08000081 + + Load Region LR_IROM1 (Base: 0x08000000, Size: 0x000002d8, Max: 0x00007600, ABSOLUTE) + + Execution Region ER_IROM1 (Exec base: 0x08000000, Load base: 0x08000000, Size: 0x000002d8, Max: 0x00007600, ABSOLUTE) + + Exec Addr Load Addr Size Type Attr Idx E Section Name Object + + 0x08000000 0x08000000 0x00000080 Data RO 100 RESET startup_n32g003.o + 0x08000080 0x08000080 0x00000008 Code RO 119 * !!!main c_p.l(__main.o) + 0x08000088 0x08000088 0x0000003c Code RO 294 !!!scatter c_p.l(__scatter.o) + 0x080000c4 0x080000c4 0x0000001c Code RO 296 !!handler_zi c_p.l(__scatter_zi.o) + 0x080000e0 0x080000e0 0x00000002 Code RO 157 .ARM.Collect$$libinit$$00000000 c_p.l(libinit.o) + 0x080000e2 0x080000e2 0x00000000 Code RO 171 .ARM.Collect$$libinit$$00000002 c_p.l(libinit2.o) + 0x080000e2 0x080000e2 0x00000000 Code RO 173 .ARM.Collect$$libinit$$00000004 c_p.l(libinit2.o) + 0x080000e2 0x080000e2 0x00000000 Code RO 176 .ARM.Collect$$libinit$$0000000A c_p.l(libinit2.o) + 0x080000e2 0x080000e2 0x00000000 Code RO 178 .ARM.Collect$$libinit$$0000000C c_p.l(libinit2.o) + 0x080000e2 0x080000e2 0x00000000 Code RO 180 .ARM.Collect$$libinit$$0000000E c_p.l(libinit2.o) + 0x080000e2 0x080000e2 0x00000000 Code RO 183 .ARM.Collect$$libinit$$00000011 c_p.l(libinit2.o) + 0x080000e2 0x080000e2 0x00000000 Code RO 185 .ARM.Collect$$libinit$$00000013 c_p.l(libinit2.o) + 0x080000e2 0x080000e2 0x00000000 Code RO 187 .ARM.Collect$$libinit$$00000015 c_p.l(libinit2.o) + 0x080000e2 0x080000e2 0x00000000 Code RO 189 .ARM.Collect$$libinit$$00000017 c_p.l(libinit2.o) + 0x080000e2 0x080000e2 0x00000000 Code RO 191 .ARM.Collect$$libinit$$00000019 c_p.l(libinit2.o) + 0x080000e2 0x080000e2 0x00000000 Code RO 193 .ARM.Collect$$libinit$$0000001B c_p.l(libinit2.o) + 0x080000e2 0x080000e2 0x00000000 Code RO 195 .ARM.Collect$$libinit$$0000001D c_p.l(libinit2.o) + 0x080000e2 0x080000e2 0x00000000 Code RO 197 .ARM.Collect$$libinit$$0000001F c_p.l(libinit2.o) + 0x080000e2 0x080000e2 0x00000000 Code RO 199 .ARM.Collect$$libinit$$00000021 c_p.l(libinit2.o) + 0x080000e2 0x080000e2 0x00000000 Code RO 201 .ARM.Collect$$libinit$$00000023 c_p.l(libinit2.o) + 0x080000e2 0x080000e2 0x00000000 Code RO 203 .ARM.Collect$$libinit$$00000025 c_p.l(libinit2.o) + 0x080000e2 0x080000e2 0x00000000 Code RO 207 .ARM.Collect$$libinit$$0000002C c_p.l(libinit2.o) + 0x080000e2 0x080000e2 0x00000000 Code RO 209 .ARM.Collect$$libinit$$0000002E c_p.l(libinit2.o) + 0x080000e2 0x080000e2 0x00000000 Code RO 211 .ARM.Collect$$libinit$$00000030 c_p.l(libinit2.o) + 0x080000e2 0x080000e2 0x00000000 Code RO 213 .ARM.Collect$$libinit$$00000032 c_p.l(libinit2.o) + 0x080000e2 0x080000e2 0x00000002 Code RO 214 .ARM.Collect$$libinit$$00000033 c_p.l(libinit2.o) + 0x080000e4 0x080000e4 0x00000002 Code RO 249 .ARM.Collect$$libshutdown$$00000000 c_p.l(libshutdown.o) + 0x080000e6 0x080000e6 0x00000000 Code RO 277 .ARM.Collect$$libshutdown$$00000002 c_p.l(libshutdown2.o) + 0x080000e6 0x080000e6 0x00000000 Code RO 279 .ARM.Collect$$libshutdown$$00000004 c_p.l(libshutdown2.o) + 0x080000e6 0x080000e6 0x00000000 Code RO 282 .ARM.Collect$$libshutdown$$00000007 c_p.l(libshutdown2.o) + 0x080000e6 0x080000e6 0x00000000 Code RO 285 .ARM.Collect$$libshutdown$$0000000A c_p.l(libshutdown2.o) + 0x080000e6 0x080000e6 0x00000000 Code RO 287 .ARM.Collect$$libshutdown$$0000000C c_p.l(libshutdown2.o) + 0x080000e6 0x080000e6 0x00000000 Code RO 290 .ARM.Collect$$libshutdown$$0000000F c_p.l(libshutdown2.o) + 0x080000e6 0x080000e6 0x00000002 Code RO 291 .ARM.Collect$$libshutdown$$00000010 c_p.l(libshutdown2.o) + 0x080000e8 0x080000e8 0x00000000 Code RO 121 .ARM.Collect$$rtentry$$00000000 c_p.l(__rtentry.o) + 0x080000e8 0x080000e8 0x00000000 Code RO 127 .ARM.Collect$$rtentry$$00000002 c_p.l(__rtentry2.o) + 0x080000e8 0x080000e8 0x00000006 Code RO 139 .ARM.Collect$$rtentry$$00000004 c_p.l(__rtentry4.o) + 0x080000ee 0x080000ee 0x00000000 Code RO 129 .ARM.Collect$$rtentry$$00000009 c_p.l(__rtentry2.o) + 0x080000ee 0x080000ee 0x00000004 Code RO 130 .ARM.Collect$$rtentry$$0000000A c_p.l(__rtentry2.o) + 0x080000f2 0x080000f2 0x00000000 Code RO 132 .ARM.Collect$$rtentry$$0000000C c_p.l(__rtentry2.o) + 0x080000f2 0x080000f2 0x00000008 Code RO 133 .ARM.Collect$$rtentry$$0000000D c_p.l(__rtentry2.o) + 0x080000fa 0x080000fa 0x00000002 Code RO 162 .ARM.Collect$$rtexit$$00000000 c_p.l(rtexit.o) + 0x080000fc 0x080000fc 0x00000000 Code RO 220 .ARM.Collect$$rtexit$$00000002 c_p.l(rtexit2.o) + 0x080000fc 0x080000fc 0x00000004 Code RO 221 .ARM.Collect$$rtexit$$00000003 c_p.l(rtexit2.o) + 0x08000100 0x08000100 0x00000006 Code RO 222 .ARM.Collect$$rtexit$$00000004 c_p.l(rtexit2.o) + 0x08000106 0x08000106 0x00000002 PAD + 0x08000108 0x08000108 0x00000038 Code RO 101 .text startup_n32g003.o + 0x08000140 0x08000140 0x00000006 Code RO 117 .text c_p.l(heapauxi.o) + 0x08000146 0x08000146 0x0000003e Code RO 143 .text c_p.l(sys_stackheap_outer.o) + 0x08000184 0x08000184 0x00000010 Code RO 146 .text c_p.l(exit.o) + 0x08000194 0x08000194 0x00000008 Code RO 158 .text c_p.l(libspace.o) + 0x0800019c 0x0800019c 0x0000000c Code RO 215 .text c_p.l(sys_exit.o) + 0x080001a8 0x080001a8 0x00000002 Code RO 238 .text c_p.l(use_no_semi.o) + 0x080001aa 0x080001aa 0x00000000 Code RO 240 .text c_p.l(indicate_semi.o) + 0x080001aa 0x080001aa 0x00000002 PAD + 0x080001ac 0x080001ac 0x00000010 Code RO 39 .text.RCC_Sysclk_Config n32g003_rcc.o + 0x080001bc 0x080001bc 0x00000058 Code RO 17 .text.System_Clock_Set system_n32g003.o + 0x08000214 0x08000214 0x00000064 Code RO 15 .text.System_Initializes system_n32g003.o + 0x08000278 0x08000278 0x00000014 Code RO 21 .text.Systeminit_Flash_Latency_Set system_n32g003.o + 0x0800028c 0x0800028c 0x00000024 Code RO 4 .text.delay_loop main.o + 0x080002b0 0x080002b0 0x00000018 Code RO 2 .text.main main.o + 0x080002c8 0x080002c8 0x00000010 Data RO 293 Region$$Table anon$$obj.o + + + Execution Region RW_IRAM1 (Exec base: 0x20000000, Load base: 0x080002d8, Size: 0x00000668, Max: 0x00000c00, ABSOLUTE) + + Exec Addr Load Addr Size Type Attr Idx E Section Name Object + + 0x20000000 - 0x00000060 Zero RW 159 .bss c_p.l(libspace.o) + 0x20000060 - 0x00000004 Zero RW 6 .bss.g_loop_count main.o + 0x20000064 0x080002d8 0x00000004 PAD + 0x20000068 - 0x00000200 Zero RW 99 HEAP startup_n32g003.o + 0x20000268 - 0x00000400 Zero RW 98 STACK startup_n32g003.o + + +============================================================================== + +Image component sizes + + + Code (inc. data) RO Data RW Data ZI Data Debug Object Name + + 60 8 0 0 4 767 main.o + 16 0 0 0 0 6802 n32g003_rcc.o + 56 26 128 0 1536 636 startup_n32g003.o + 208 24 0 0 0 2482 system_n32g003.o + + ---------------------------------------------------------------------- + 340 58 144 0 1544 10687 Object Totals + 0 0 16 0 0 0 (incl. Generated) + 0 0 0 0 4 0 (incl. Padding) + + ---------------------------------------------------------------------- + + Code (inc. data) RO Data RW Data ZI Data Debug Library Member Name + + 8 0 0 0 0 68 __main.o + 0 0 0 0 0 0 __rtentry.o + 12 0 0 0 0 0 __rtentry2.o + 6 0 0 0 0 0 __rtentry4.o + 60 8 0 0 0 0 __scatter.o + 28 0 0 0 0 0 __scatter_zi.o + 16 0 0 0 0 68 exit.o + 6 0 0 0 0 136 heapauxi.o + 0 0 0 0 0 0 indicate_semi.o + 2 0 0 0 0 0 libinit.o + 2 0 0 0 0 0 libinit2.o + 2 0 0 0 0 0 libshutdown.o + 2 0 0 0 0 0 libshutdown2.o + 8 4 0 0 96 68 libspace.o + 2 0 0 0 0 0 rtexit.o + 10 0 0 0 0 0 rtexit2.o + 12 4 0 0 0 60 sys_exit.o + 62 0 0 0 0 80 sys_stackheap_outer.o + 2 0 0 0 0 68 use_no_semi.o + + ---------------------------------------------------------------------- + 244 16 0 0 96 548 Library Totals + 4 0 0 0 0 0 (incl. Padding) + + ---------------------------------------------------------------------- + + Code (inc. data) RO Data RW Data ZI Data Debug Library Name + + 240 16 0 0 96 548 c_p.l + + ---------------------------------------------------------------------- + 244 16 0 0 96 548 Library Totals + + ---------------------------------------------------------------------- + +============================================================================== + + + Code (inc. data) RO Data RW Data ZI Data Debug + + 584 74 144 0 1640 11043 Grand Totals + 584 74 144 0 1640 11043 ELF Image Totals + 584 74 144 0 0 0 ROM Totals + +============================================================================== + + Total RO Size (Code + RO Data) 728 ( 0.71kB) + Total RW Size (RW Data + ZI Data) 1640 ( 1.60kB) + Total ROM Size (Code + RO Data + RW Data) 728 ( 0.71kB) + +============================================================================== + diff --git a/test.uvguix.Administrator b/test.uvguix.Administrator new file mode 100644 index 0000000..e3af4be --- /dev/null +++ b/test.uvguix.Administrator @@ -0,0 +1,3691 @@ + + + + -6.1 + +
### uVision Project, (C) Keil Software
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+ + + + 0 + 2048 + 1152 + + + + + + 1 + 0 + + 100 + 8 + + main.c + 0 + 63 + 64 + 1 + + 0 + + + firmware\CMSIS\device\system_n32g003.c + 0 + 1 + 1 + 1 + + 0 + + + firmware\CMSIS\device\startup\startup_n32g003.s + 0 + 110 + 124 + 1 + + 0 + + + firmware\CMSIS\core\core_cmInstr.h + 0 + 356 + 385 + 1 + + 0 + + + firmware\n32g003_std_periph_driver\src\n32g003_gpio.c + 22 + 714 + 743 + 1 + + 0 + + + firmware\n32g003_std_periph_driver\inc\n32g003_gpio.h + 0 + 278 + 307 + 1 + + 0 + + + firmware\n32g003_std_periph_driver\src\n32g003_rcc.c + 0 + 1 + 1 + 1 + + 0 + + + firmware\CMSIS\core\core_cm0.h + 0 + 545 + 574 + 1 + + 0 + + + firmware\n32g003_std_periph_driver\src\n32g003_uart.c + 0 + 106 + 1 + 1 + + 0 + + + + + diff --git a/test.uvoptx b/test.uvoptx new file mode 100644 index 0000000..d64548d --- /dev/null +++ b/test.uvoptx @@ -0,0 +1,301 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + ARMRTXEVENTFLAGS + -L70 -Z18 -C0 -M0 -T1 + + + 0 + DLGTARM + (1010=-1,-1,-1,-1,0)(1007=-1,-1,-1,-1,0)(1008=-1,-1,-1,-1,0) + + + 0 + ARMDBGFLAGS + + + + 0 + DLGUARM + + + + 0 + CMSIS_AGDI + -X"CMSIS-DAP-NSLink" -U0001A0000002 -O206 -S0 -C0 -P00000000 -N00("ARM CoreSight SW-DP") -D00(0BB11477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8009 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO7 -FD20000000 -FC800 -FN1 -FF0N32G003x.FLM -FS08000000 -FL07600 -FP0($$Device:N32G003F5$Flash\N32G003x.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC800 -FN1 -FF0N32G003x -FS08000000 -FL07600 -FP0($$Device:N32G003F5$Flash\N32G003x.FLM)) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Source Group 1 + 1 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + main.c + main.c + 0 + 0 + + + + + CMSIS + 0 + 0 + 0 + 0 + + 2 + 2 + 1 + 1 + 0 + 0 + firmware\CMSIS\device\system_n32g003.c + system_n32g003.c + 0 + 0 + + + + + STARTUP + 1 + 0 + 0 + 0 + + 3 + 3 + 2 + 0 + 0 + 0 + firmware\CMSIS\device\startup\startup_n32g003.s + startup_n32g003.s + 0 + 0 + + + + + FWLB + 1 + 0 + 0 + 0 + + 4 + 4 + 1 + 0 + 0 + 0 + firmware\n32g003_std_periph_driver\src\n32g003_rcc.c + n32g003_rcc.c + 0 + 0 + + + 4 + 5 + 1 + 0 + 0 + 0 + firmware\n32g003_std_periph_driver\src\n32g003_gpio.c + n32g003_gpio.c + 0 + 0 + + + 4 + 6 + 1 + 0 + 0 + 0 + firmware\n32g003_std_periph_driver\src\n32g003_uart.c + n32g003_uart.c + 0 + 0 + + + + diff --git a/test.uvprojx b/test.uvprojx new file mode 100644 index 0000000..51f2dc5 --- /dev/null +++ b/test.uvprojx @@ -0,0 +1,458 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 6140000::V6.14::ARMCLANG + 1 + + + N32G003F5 + Nationstech + Nationstech.N32G003_DFP.1.0.1 + http://www.keil.com/pack/ + IRAM(0x20000000,0x0C00) IROM(0x08000000,0x7600) CPUTYPE("Cortex-M0") CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20000000 -FC800 -FN1 -FF0N32G003x -FS08000000 -FL07600 -FP0($$Device:N32G003F5$Flash\N32G003x.FLM)) + 0 + firmware\CMSIS\device\n32g003.h + + + + + + + + + + $$Device:N32G003F5$svd\N32G003.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + test + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP + DARMCM1.DLL + -pCM0 + SARMCM3.DLL + + TARMCM1.DLL + -pCM0 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + -1 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M0" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 8 + 1 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0xc00 + + + 1 + 0x8000000 + 0x7600 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x7600 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20000000 + 0xc00 + + + 0 + 0x0 + 0x0 + + + + + + 1 + 2 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 3 + 3 + 1 + 1 + 0 + 0 + 0 + + + N32G003, USE_STDPERIPH_DRIVER + + .\firmware\CMSIS\core;.\firmware\CMSIS\device;.\firmware\n32g003_std_periph_driver\inc + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20000000 + + + + + + + + + + + + + Source Group 1 + + + main.c + 1 + main.c + + + + + CMSIS + + + system_n32g003.c + 1 + firmware\CMSIS\device\system_n32g003.c + + + + + STARTUP + + + startup_n32g003.s + 2 + firmware\CMSIS\device\startup\startup_n32g003.s + + + + + FWLB + + + n32g003_rcc.c + 1 + firmware\n32g003_std_periph_driver\src\n32g003_rcc.c + + + n32g003_gpio.c + 1 + firmware\n32g003_std_periph_driver\src\n32g003_gpio.c + + + n32g003_uart.c + 1 + firmware\n32g003_std_periph_driver\src\n32g003_uart.c + + + + + + + + + + + + + + + + + <Project Info> + + + + + + 0 + 1 + + + + +