545 lines
24 KiB
C
545 lines
24 KiB
C
/**
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* Copyright (c) 2022, Nations Technologies Inc.
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*
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* All rights reserved.
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*
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* This software is the exclusive property of Nations Technologies Inc. (Hereinafter
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* referred to as NATIONS). This software, and the product of NATIONS described herein
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* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties
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* of the People's Republic of China and other applicable jurisdictions worldwide.
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*
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* NATIONS does not grant any license under its patents, copyrights, trademarks, or other
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* intellectual property rights. Names and brands of third party may be mentioned or referred
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* thereto (if any) for identification purposes only.
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*
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* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and
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* improvements to this software at any time without notice. Please contact NATIONS and obtain
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* the latest version of this software before placing orders.
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* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes
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* no responsibility for the accuracy and reliability of this software.
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*
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* It is the responsibility of the user of this software to properly design, program, and test
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* the functionality and safety of any application made of this information and any resulting product.
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* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or
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* consequential damages arising in any way out of the use of this software or the Product.
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*
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* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any
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* malfunction or failure of which may cause loss of human life, bodily injury or severe property
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* damage. Such applications are deemed, "Insecure Usage".
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*
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* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS
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* harmless from and against all claims, costs, damages, and other liabilities, arising from or related
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* to any customer's Insecure Usage.
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* Any express or implied warranty with regard to this software or the Product, including,but not
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* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement
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* are disclaimed to the fullest extent permitted by law.
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* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe
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* or otherwise distribute this software for any purposes, in whole or in part.
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*
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* NATIONS products and technologies shall not be used for or incorporated into any products or systems
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* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations.
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* User shall comply with any applicable export control laws and regulations promulgated and administered by
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* the governments of any countries asserting jurisdiction over the parties or transactions.
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**/
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/**
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*\*\file n32g003_i2c.h
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*\*\author Nations
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*\*\version v1.0.0
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*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
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**/
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#ifndef __N32G003_I2C_H_
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#define __N32G003_I2C_H_
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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#include "n32g003.h"
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/** N32G003_StdPeriph_Driver
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*
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*/
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/** I2C Init structure definition **/
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typedef struct
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{
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uint32_t ClkSpeed; /* Specifies the clock frequency. */
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uint16_t DutyCycle; /* Specifies the I2C duty cycle. */
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uint16_t OwnAddr1; /* Specifies the first device own address. */
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uint16_t AckEnable; /* Enables or disables the acknowledgement. */
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uint16_t AddrMode; /* Specifies if 7-bit or 10-bit address is acknowledged. */
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} I2C_InitType;
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#define APB_FREQ_MAX_VALUE (48) /*48M*/
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#define CLK_SPEED_100K (100000)
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#define CLK_SPEED_400K (400000)
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#define CLK_SPEED_1M (1000000)
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#define SM_CLKCTRL_LOW_LIMIT (0x04)
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#define FM_CLKCTRL_LOW_LIMIT (0x01)
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#define SM_TRISE_100K (1000) /*1000ns*/
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#define FM_TRISE_400K (300) /*300ns*/
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#define FM_TRISE_1M (120) /*120ns*/
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/** Register shift macro definition **/
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#define RCC_FLAG_STS2_OFFSET (REG_BIT16_OFFSET)
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#define RCC_FLAG_GET_OFFSET (REG_BIT28_OFFSET)
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#define I2C_REG_BIT_MASK ((uint16_t)0x0000)
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/* I2C EN mask */
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#define I2C_EN_SET (I2C_CTRL1_EN)
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#define I2C_EN_RESET (~I2C_CTRL1_EN)
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/* I2C START mask */
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#define I2C_START_SET (I2C_CTRL1_STARTGEN)
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#define I2C_START_RESET (~I2C_CTRL1_STARTGEN)
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/* I2C STOP mask */
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#define I2C_STOP_SET (I2C_CTRL1_STOPGEN)
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#define I2C_STOP_RESET (~I2C_CTRL1_STOPGEN)
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/* I2C ACK mask */
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#define I2C_ACK_SET (I2C_CTRL1_ACKEN)
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#define I2C_ACK_RESET (~I2C_CTRL1_ACKEN)
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/* I2C ENGC mask */
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#define I2C_GCEN_SET (I2C_CTRL1_GCEN)
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#define I2C_GCEN_RESET (~I2C_CTRL1_GCEN)
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/* I2C SWRST mask */
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#define I2C_SWRESET_SET (I2C_CTRL1_SWRESET)
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#define I2C_SWRESET_RESET (~I2C_CTRL1_SWRESET)
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/* I2C PEC mask */
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#define I2C_PEC_SET (I2C_CTRL1_PEC)
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#define I2C_PEC_RESET (~I2C_CTRL1_PEC)
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/* I2C ENPEC mask */
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#define I2C_PECEN_SET (I2C_CTRL1_PECEN)
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#define I2C_PECEN_RESET (~I2C_CTRL1_PECEN)
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/* I2C NOSTRETCH mask */
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#define I2C_NOEXTEND_SET (I2C_CTRL1_NOEXTEND)
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#define I2C_NOEXTEND_RESET (~I2C_CTRL1_NOEXTEND)
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/* I2C registers Masks */
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#define I2C_ACKEN_CLR_MASK (~(I2C_CTRL1_ACKEN))
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#define I2C_ADDRMODE_CLR_MASK (~(I2C_OADDR1_ADDRMODE))
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#define I2C_OADDR_CLR_MASK (~(I2C_OADDR1_ADDR0 | I2C_OADDR1_ADDR1_7 | I2C_OADDR1_ADDR8_9))
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/* I2C FREQ mask */
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#define I2C_CLKFREQ_RESET (~I2C_CTRL2_CLKFREQ)
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/* I2C ADD0 mask */
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#define I2C_ADDR0_SET (I2C_OADDR1_ADDR0)
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#define I2C_ADDR0_RESET (~I2C_OADDR1_ADDR0)
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/* I2C ENDUAL mask */
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#define I2C_DUALEN_SET (((uint16_t)I2C_OADDR2_DUALEN))
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#define I2C_DUALEN_RESET (~((uint16_t)I2C_OADDR2_DUALEN))
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/* I2C ADD2 mask */
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#define I2C_ADDR2_SET ((uint16_t)I2C_OADDR2_ADDR2)
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#define I2C_ADDR2_RESET (~((uint16_t)I2C_OADDR2_ADDR2))
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/* I2C F/S mask */
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#define I2C_FSMODE_SET (I2C_CLKCTRL_FSMODE)
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/* I2C CHCFG mask */
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#define I2C_CLKCTRL_SET (I2C_CLKCTRL_CLKCTRL)
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/* I2C TMRISE mask */
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#define I2C_SDADFW_MASK (~I2C_GFLTRCTRL_SDADFW)
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#define I2C_SCLDFW_MASK (~I2C_GFLTRCTRL_SCLDFW)
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#define I2C_SDAAFW_MASK (~I2C_GFLTRCTRL_SDAAFW)
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#define I2C_SCLAFW_MASK (~I2C_GFLTRCTRL_SCLAFW)
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#define I2C_SDAAFENN_SET (I2C_GFLTRCTRL_SDAAFENN)
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#define I2C_SDAAFENN_RESET (~I2C_GFLTRCTRL_SDAAFENN)
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#define I2C_SCLAFENN_SET (I2C_GFLTRCTRL_SCLAFENN)
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#define I2C_SCLAFENN_RESET (~I2C_GFLTRCTRL_SCLAFENN)
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#define I2C_TMRISE_MASK (I2C_TMRISE_TRISE)
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/* I2C FLAG mask */
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#define I2C_FLAG_Mask ((uint32_t)0x00FFFFFF)
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/* I2C Interrupt Enable mask */
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#define I2C_INTEN_MASK ((uint32_t)0x07000000)
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/** I2C_duty_cycle **/
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#define I2C_SMDUTYCYCLE_1 (I2C_REG_BIT_MASK) /* I2C standard mode Tlow/Thigh = 1/1 */
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#define I2C_FMDUTYCYCLE_16_9 (I2C_CLKCTRL_DUTY) /* I2C fast mode Tlow/Thigh = 16/9 */
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#define I2C_FMDUTYCYCLE_2 (~I2C_CLKCTRL_DUTY) /* I2C fast mode Tlow/Thigh = 2 */
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/** I2C_acknowledgement **/
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#define I2C_ACKEN (I2C_CTRL1_ACKEN)
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#define I2C_ACKDIS (I2C_REG_BIT_MASK)
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/** I2C_transfer_direction **/
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#define I2C_DIRECTION_SEND ((uint8_t)0x00)
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#define I2C_DIRECTION_RECV ((uint8_t)0x01)
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/** I2C_acknowledged_address **/
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/* Bit 14 Should be kept at 1 by software*/
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#define I2C_ADDR_MODE_7BIT (((uint16_t)0x4000) | I2C_REG_BIT_MASK)
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#define I2C_ADDR_MODE_10BIT (((uint16_t)0x4000) | I2C_OADDR1_ADDRMODE)
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/** I2C_registers **/
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#define I2C_REG_CTRL1 ((uint8_t)0x00)
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#define I2C_REG_CTRL2 ((uint8_t)0x04)
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#define I2C_REG_OADDR1 ((uint8_t)0x08)
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#define I2C_REG_OADDR2 ((uint8_t)0x0C)
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#define I2C_REG_DAT ((uint8_t)0x10)
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#define I2C_REG_STS1 ((uint8_t)0x14)
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#define I2C_REG_STS2 ((uint8_t)0x18)
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#define I2C_REG_CLKCTRL ((uint8_t)0x1C)
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#define I2C_REG_TMRISE ((uint8_t)0x20)
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#define I2C_REG_GFLTRCTRL ((uint8_t)0x24)
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#define I2C_REG_BYTENUM ((uint8_t)0x28)
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/** I2C_PEC_position **/
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#define I2C_PEC_POS_NEXT (I2C_CTRL1_ACKPOS)
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#define I2C_PEC_POS_CURRENT (~I2C_CTRL1_ACKPOS)
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/** I2C_NCAK_position **/
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#define I2C_NACK_POS_NEXT (I2C_CTRL1_ACKPOS)
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#define I2C_NACK_POS_CURRENT (~I2C_CTRL1_ACKPOS)
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/** I2C_Analog_Filter_Width **/
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#define I2C_ANALOG_FILTER_WIDTH_5NS ((uint16_t)0x0000)
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#define I2C_ANALOG_FILTER_WIDTH_15NS (I2C_GFLTRCTRL_SDAAFW_0)
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#define I2C_ANALOG_FILTER_WIDTH_25NS (I2C_GFLTRCTRL_SDAAFW_1)
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#define I2C_ANALOG_FILTER_WIDTH_35NS (I2C_GFLTRCTRL_SDAAFW_0|I2C_GFLTRCTRL_SDAAFW_1)
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/** I2C_interrupts_definition **/
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#define I2C_INT_BUF (I2C_CTRL2_BUFINTEN)
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#define I2C_INT_EVENT (I2C_CTRL2_EVTINTEN)
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#define I2C_INT_ERR (I2C_CTRL2_ERRINTEN)
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/* I2C BYTE_NUM_EN mask */
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#define I2C_BYTENUMEN_SET (I2C_BYTENUM_BYTENUMEN)
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#define I2C_BYTENUMEN_RESET (~I2C_BYTENUM_BYTENUMEN)
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/* I2C BYTE_NUM byte number mask */
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#define I2C_BYTENUM_MASK (~I2C_BYTENUM_BYTENUM)
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/* I2C master sended status after finishing receiving data bytes */
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#define I2C_BYTENUM_LAST_STOP (~I2C_BYTENUM_RXFSEL)
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#define I2C_BYTENUM_LAST_START (I2C_BYTENUM_RXFSEL)
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/** I2C_interrupts_definition **/
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#define I2C_INT_PECERR (((uint32_t)0x01000000) | ((uint32_t)I2C_STS1_PECERR))
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#define I2C_INT_OVERRUN (((uint32_t)0x01000000) | ((uint32_t)I2C_STS1_OVERRUN))
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#define I2C_INT_ACKFAIL (((uint32_t)0x01000000) | ((uint32_t)I2C_STS1_ACKFAIL))
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#define I2C_INT_ARLOST (((uint32_t)0x01000000) | ((uint32_t)I2C_STS1_ARLOST))
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#define I2C_INT_BUSERR (((uint32_t)0x01000000) | ((uint32_t)I2C_STS1_BUSERR))
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#define I2C_INT_TXDATE (((uint32_t)0x06000000) | ((uint32_t)I2C_STS1_TXDATE))
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#define I2C_INT_RXDATNE (((uint32_t)0x06000000) | ((uint32_t)I2C_STS1_RXDATNE))
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#define I2C_INT_STOPF (((uint32_t)0x02000000) | ((uint32_t)I2C_STS1_STOPF))
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#define I2C_INT_ADDR10F (((uint32_t)0x02000000) | ((uint32_t)I2C_STS1_ADDR10F))
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#define I2C_INT_BYTEF (((uint32_t)0x02000000) | ((uint32_t)I2C_STS1_BSF))
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#define I2C_INT_ADDRF (((uint32_t)0x02000000) | ((uint32_t)I2C_STS1_ADDRF))
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#define I2C_INT_STARTBF (((uint32_t)0x02000000) | ((uint32_t)I2C_STS1_STARTBF))
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/** I2C_flags_definition **/
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/** STS2 register flags **/
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#define I2C_FLAG_DUALFLAG (((uint32_t)I2C_STS2_DUALFLAG)<<16)
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#define I2C_FLAG_GCALLADDR (((uint32_t)I2C_STS2_GCALLADDR)<<16)
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#define I2C_FLAG_TRF (((uint32_t)I2C_STS2_TRF)<<16)
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#define I2C_FLAG_BUSY (((uint32_t)I2C_STS2_BUSY)<<16)
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#define I2C_FLAG_MSMODE (((uint32_t)I2C_STS2_MSMODE)<<16)
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/** STS1 register flags **/
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#define I2C_FLAG_PECERR (((uint32_t)0x10000000) | ((uint32_t)I2C_STS1_PECERR))
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#define I2C_FLAG_OVERRUN (((uint32_t)0x10000000) | ((uint32_t)I2C_STS1_OVERRUN))
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#define I2C_FLAG_ACKFAIL (((uint32_t)0x10000000) | ((uint32_t)I2C_STS1_ACKFAIL))
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#define I2C_FLAG_ARLOST (((uint32_t)0x10000000) | ((uint32_t)I2C_STS1_ARLOST))
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#define I2C_FLAG_BUSERR (((uint32_t)0x10000000) | ((uint32_t)I2C_STS1_BUSERR))
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#define I2C_FLAG_TXDATE (((uint32_t)0x10000000) | ((uint32_t)I2C_STS1_TXDATE))
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#define I2C_FLAG_RXDATNE (((uint32_t)0x10000000) | ((uint32_t)I2C_STS1_RXDATNE))
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#define I2C_FLAG_STOPF (((uint32_t)0x10000000) | ((uint32_t)I2C_STS1_STOPF))
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#define I2C_FLAG_ADDR10F (((uint32_t)0x10000000) | ((uint32_t)I2C_STS1_ADDR10F))
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#define I2C_FLAG_BYTEF (((uint32_t)0x10000000) | ((uint32_t)I2C_STS1_BSF))
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#define I2C_FLAG_ADDRF (((uint32_t)0x10000000) | ((uint32_t)I2C_STS1_ADDRF))
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#define I2C_FLAG_STARTBF (((uint32_t)0x10000000) | ((uint32_t)I2C_STS1_STARTBF))
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/** I2C_Events **/
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/** I2C Master Events (Events grouped in order of communication) **/
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/**
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*\*\brief Communication start
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*\*\After sending the START condition (I2C_Generate_Start_Enable() function) the master
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*\*\has to wait for this event. It means that the Start condition has been correctly
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*\*\released on the I2C bus (the bus is free, no other devices is communicating).
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**/
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/* MSMODE */
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#define I2C_ROLE_MASTER (((uint32_t)I2C_STS2_MSMODE)<<16)
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/* EV5 */
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/* BUSY, MSMODE and STARTBF flag*/
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#define I2C_EVT_MASTER_MODE_FLAG (((uint32_t)I2C_STS1_STARTBF)\
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|((((uint32_t)I2C_STS2_BUSY)|((uint32_t)I2C_STS2_MSMODE))<<16))
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/**
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*\*\brief Address Acknowledge
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*\*\After checking on EV5 (start condition correctly released on the bus), the
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*\*\master sends the address of the slave(s) with which it will communicate
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*\*\(I2C_7bit_Addr_Send() function, it also determines the direction of the communication:
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*\*\Master transmitter or Receiver). Then the master has to wait that a slave acknowledges
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*\*\his address. If an acknowledge is sent on the bus, one of the following events will
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*\*\be set:
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*\*\ 1) In case of Master Receiver (7-bit addressing): the I2C_EVT_MASTER_RXMODE_FLAG
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*\*\ event is set.
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*\*\ 2) In case of Master Transmitter (7-bit addressing): the I2C_EVT_MASTER_TXMODE_FLAG
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*\*\ is set
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*\*\ 3) In case of 10-Bit addressing mode, the master (just after generating the START
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*\*\ and checking on EV5) has to send the header of 10-bit addressing mode (I2C_Data_Send()
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*\*\ function). Then master should wait on EV9. It means that the 10-bit addressing
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*\*\ header has been correctly sent on the bus. Then master should send the second part of
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*\*\ the 10-bit address (LSB) using the function I2C_7bit_Addr_Send(). Then master
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*\*\ should wait for event EV6.
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**/
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/* --EV6 */
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/* BUSY, MSMODE, ADDRF, TXDATE and TRF flags */
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#define I2C_EVT_MASTER_TXMODE_FLAG (((uint32_t)I2C_STS1_ADDRF)|((uint32_t)I2C_STS1_TXDATE)\
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|((((uint32_t)I2C_STS2_BUSY)|((uint32_t)I2C_STS2_MSMODE)|((uint32_t)I2C_STS2_TRF))<<16))
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/* BUSY, MSMODE and ADDRF flags */
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#define I2C_EVT_MASTER_RXMODE_FLAG (((uint32_t)I2C_STS1_ADDRF)\
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|((((uint32_t)I2C_STS2_BUSY)|((uint32_t)I2C_STS2_MSMODE))<<16))
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/* --EV9 */
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/* BUSY, MSMODE and ADD10RF flags */
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#define I2C_EVT_MASTER_MODE_ADDRESS10_FLAG (((uint32_t)I2C_STS1_ADDR10F)\
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|((((uint32_t)I2C_STS2_BUSY)|((uint32_t)I2C_STS2_MSMODE))<<16))
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/**
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*\*\brief Communication events
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*\*\If a communication is established (START condition generated and slave address
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*\*\acknowledged) then the master has to check on one of the following events for
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*\*\communication procedures:
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*\*\1) Master Receiver mode: The master has to wait on the event EV7 then to read
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*\*\ the data received from the slave (I2C_Data_Recv() function).
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*\*\2) Master Transmitter mode: The master has to send data (I2C_Data_Send()
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*\*\ function) then to wait on event EV8 or EV8_2.
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*\*\ These two events are similar:
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*\*\ - EV8 means that the data has been written in the data register and is
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*\*\ being shifted out.
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*\*\ - EV8_2 means that the data has been physically shifted out and output
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*\*\ on the bus.
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*\*\ In most cases, using EV8 is sufficient for the application.
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*\*\ Using EV8_2 leads to a slower communication but ensure more reliable test.
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*\*\ EV8_2 is also more suitable than EV8 for testing on the last data transmission
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*\*\ (before Stop condition generation).
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*\*\note In case the user software does not guarantee that this event EV7 is
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*\*\ managed before the current byte end of transfer, then user may check on EV7
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*\*\ and BSF flag at the same time (ie. (I2C_EVT_MASTER_DATA_RECVD_FLAG | I2C_FLAG_BYTEF)).
|
|
*\*\ In this case the communication may be slower.
|
|
**/
|
|
|
|
/* Master RECEIVER mode -----------------------------*/
|
|
/* --EV7 */
|
|
/* BUSY, MSMODE and RXDATNE flags */
|
|
#define I2C_EVT_MASTER_DATA_RECVD_FLAG (((uint32_t)I2C_STS1_RXDATNE)\
|
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|((((uint32_t)I2C_STS2_BUSY)|((uint32_t)I2C_STS2_MSMODE))<<16))
|
|
|
|
/* EV7x shifter register full */
|
|
/* BUSY, MSMODE, BSF and RXDATNE flags */
|
|
#define I2C_EVT_MASTER_DATA_RECVD_BSF_FLAG (((uint32_t)I2C_STS1_RXDATNE)|((uint32_t)I2C_STS1_BSF)\
|
|
|((((uint32_t)I2C_STS2_BUSY)|((uint32_t)I2C_STS2_MSMODE))<<16))
|
|
|
|
/* Master TRANSMITTER mode --------------------------*/
|
|
/* --EV8 */
|
|
/* TRF, BUSY, MSMODE, TXDATE flags */
|
|
#define I2C_EVT_MASTER_DATA_SENDING (((uint32_t)I2C_STS1_TXDATE)\
|
|
|((((uint32_t)I2C_STS2_BUSY)|((uint32_t)I2C_STS2_MSMODE)|((uint32_t)I2C_STS2_TRF))<<16))
|
|
/* --EV8_2 */
|
|
/* TRF, BUSY, MSMODE, TXDATE and BSF flags */
|
|
#define I2C_EVT_MASTER_DATA_SENDED (((uint32_t)I2C_STS1_BSF)|((uint32_t)I2C_STS1_TXDATE)\
|
|
|((((uint32_t)I2C_STS2_BUSY)|((uint32_t)I2C_STS2_MSMODE)|((uint32_t)I2C_STS2_TRF))<<16))
|
|
|
|
/*========================================
|
|
|
|
I2C Slave Events (Events grouped in order of communication)
|
|
==========================================*/
|
|
|
|
/**
|
|
*\*\brief Communication start events
|
|
*\*\Wait on one of these events at the start of the communication. It means that
|
|
*\*\the I2C peripheral detected a Start condition on the bus (generated by master
|
|
*\*\device) followed by the peripheral address. The peripheral generates an ACK
|
|
*\*\condition on the bus (if the acknowledge feature is enabled through function
|
|
*\*\I2C_ConfigAck()) and the events listed above are set :
|
|
*\*\1) In normal case (only one address managed by the slave), when the address
|
|
*\*\ sent by the master matches the own address of the peripheral (configured by
|
|
*\*\ OwnAddr1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set
|
|
*\*\ (where XXX could be TRANSMITTER or RECEIVER).
|
|
*\*\2) In case the address sent by the master matches the second address of the
|
|
*\*\ peripheral (configured by the function I2C_ConfigOwnAddr2() and enabled
|
|
*\*\ by the function I2C_EnableDualAddr()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED
|
|
*\*\ (where XXX could be TRANSMITTER or RECEIVER) are set.
|
|
*\*\3) In case the address sent by the master is General Call (address 0x00) and
|
|
*\*\ if the General Call is enabled for the peripheral (using function I2C_EnableGeneralCall())
|
|
*\*\ the following event is set I2C_EVT_SLAVE_GCALLADDR_MATCHED.
|
|
**/
|
|
|
|
/* --EV1 (all the events below are variants of EV1) */
|
|
/* 1) Case of One Single Address managed by the slave */
|
|
/* BUSY and ADDRF flags */
|
|
#define I2C_EVT_SLAVE_RECV_ADDR_MATCHED (((uint32_t)I2C_STS1_ADDRF)\
|
|
|((((uint32_t)I2C_STS2_BUSY))<<16))
|
|
/* TRF, BUSY, TXDATE and ADDRF flags */
|
|
#define I2C_EVT_SLAVE_SEND_ADDR_MATCHED (((uint32_t)I2C_STS1_TXDATE)|((uint32_t)I2C_STS1_ADDRF)\
|
|
|((((uint32_t)I2C_STS2_BUSY)|((uint32_t)I2C_STS2_TRF))<<16))
|
|
|
|
/* 2) Case of Dual address managed by the slave */
|
|
/* DUALF and BUSY flags */
|
|
#define I2C_EVT_SLAVE_RECV_ADDR2_MATCHED ((((uint32_t)I2C_STS2_BUSY)|((uint32_t)I2C_STS2_DUALFLAG))<<16)
|
|
/* DUALF, TRF, BUSY and TXDATE flags */
|
|
#define I2C_EVT_SLAVE_SEND_ADDR2_MATCHED (((uint32_t)I2C_STS1_TXDATE)\
|
|
|((((uint32_t)I2C_STS2_BUSY)|((uint32_t)I2C_STS2_DUALFLAG)|((uint32_t)I2C_STS2_TRF))<<16))
|
|
|
|
/* 3) Case of General Call enabled for the slave */
|
|
/* GENCALL and BUSY flags */
|
|
#define I2C_EVT_SLAVE_GCALLADDR_MATCHED ((((uint32_t)I2C_STS2_BUSY)|((uint32_t)I2C_STS2_GCALLADDR))<<16)
|
|
|
|
/**
|
|
*\*\brief Communication events
|
|
*\*\Wait on one of these events when EV1 has already been checked and:
|
|
*\*\- Slave RECEIVER mode:
|
|
*\*\ - EV2: When the application is expecting a data byte to be received.
|
|
*\*\ - EV4: When the application is expecting the end of the communication: master
|
|
*\*\ sends a stop condition and data transmission is stopped.
|
|
*\*\- Slave Transmitter mode:
|
|
*\*\ - EV3: When a byte has been transmitted by the slave and the application is expecting
|
|
*\*\ the end of the byte transmission. The two events I2C_EVT_SLAVE_DATA_SENDED and
|
|
*\*\ I2C_EVT_SLAVE_DATA_SENDING are similar. The second one can optionally be
|
|
*\*\ used when the user software doesn't guarantee the EV3 is managed before the
|
|
*\*\ current byte end of transfer.
|
|
*\*\ - EV3_2: When the master sends a NACK in order to tell slave that data transmission
|
|
*\*\ shall end (before sending the STOP condition). In this case slave has to stop sending
|
|
*\*\ data bytes and expect a Stop condition on the bus.
|
|
*\*\note In case the user software does not guarantee that the event EV2 is
|
|
*\*\ managed before the current byte end of transfer, then user may check on EV2
|
|
*\*\ and BSF flag at the same time (ie. (I2C_EVT_SLAVE_DATA_RECVD | I2C_FLAG_BYTEF)).
|
|
*\*\In this case the communication may be slower.
|
|
**/
|
|
|
|
/* Slave RECEIVER mode --------------------------*/
|
|
/* --EV2 */
|
|
/* BUSY and RXDATNE flags */
|
|
#define I2C_EVT_SLAVE_DATA_RECVD (((uint32_t)I2C_STS1_RXDATNE)\
|
|
|((((uint32_t)I2C_STS2_BUSY))<<16))
|
|
/* --EV2x */
|
|
/* no BUSY and RXDATNE flags */
|
|
#define I2C_EVT_SLAVE_DATA_RECVD_NOBUSY ((uint32_t)I2C_STS1_RXDATNE)
|
|
/* --EV4 */
|
|
/* STOPF flag */
|
|
#define I2C_EVT_SLAVE_STOP_RECVD ((uint32_t)I2C_STS1_STOPF)
|
|
|
|
/* Slave TRANSMITTER mode -----------------------*/
|
|
/* --EV3 */
|
|
/* TRF, BUSY, TXDATE and BSF flags */
|
|
#define I2C_EVT_SLAVE_DATA_SENDED (((uint32_t)I2C_STS1_BSF)|((uint32_t)I2C_STS1_TXDATE)\
|
|
|((((uint32_t)I2C_STS2_BUSY)|((uint32_t)I2C_STS2_TRF))<<16))
|
|
/* TRF, BUSY and TXDATE flags */
|
|
#define I2C_EVT_SLAVE_DATA_SENDING (((uint32_t)I2C_STS1_TXDATE)\
|
|
|((((uint32_t)I2C_STS2_BUSY)|((uint32_t)I2C_STS2_TRF))<<16))
|
|
/* --EV3_2 */
|
|
/* AF flag */
|
|
#define I2C_EVT_SLAVE_ACK_MISS ((uint32_t)I2C_STS1_ACKFAIL)
|
|
|
|
/*=========================== End of Events Description ==========================================*/
|
|
|
|
void I2C_Reset(I2C_Module* I2Cx);
|
|
void I2C_Initializes(I2C_Module* I2Cx, I2C_InitType* I2C_InitParam);
|
|
void I2C_Clock_Speed_Config(I2C_Module* I2Cx, uint32_t clk_speed, uint16_t duty_cycle);
|
|
void I2C_Acknowledgement_Config(I2C_Module* I2Cx, uint16_t ack);
|
|
void I2C_Addressing_Mode_Config(I2C_Module* I2Cx, uint16_t mode);
|
|
void I2C_Own_Addr1_Config(I2C_Module* I2Cx, uint16_t addr1);
|
|
void I2C_Initializes_Structure(I2C_InitType* I2C_InitStruct);
|
|
void I2C_ON(I2C_Module* I2Cx);
|
|
void I2C_OFF(I2C_Module* I2Cx);
|
|
void I2C_Generate_Start_Enable(I2C_Module* I2Cx);
|
|
void I2C_Generate_Start_Disable(I2C_Module* I2Cx);
|
|
void I2C_Generate_Stop_Enable(I2C_Module* I2Cx);
|
|
void I2C_Generate_Stop_Disable(I2C_Module* I2Cx);
|
|
void I2C_Acknowledg_Enable(I2C_Module* I2Cx);
|
|
void I2C_Acknowledg_Disable(I2C_Module* I2Cx);
|
|
void I2C_Own_Addr2_Set(I2C_Module* I2Cx, uint8_t address);
|
|
void I2C_Dual_Addr_Enable(I2C_Module* I2Cx);
|
|
void I2C_Dual_Addr_Disable(I2C_Module* I2Cx);
|
|
void I2C_General_Call_Enable(I2C_Module* I2Cx);
|
|
void I2C_General_Call_Disable(I2C_Module* I2Cx);
|
|
void I2C_Interrupts_Enable(I2C_Module* I2Cx, uint16_t I2C_IT);
|
|
void I2C_Interrupts_Disable(I2C_Module* I2Cx, uint16_t I2C_IT);
|
|
void I2C_Data_Send(I2C_Module* I2Cx, uint8_t data);
|
|
uint8_t I2C_Data_Recv(I2C_Module* I2Cx);
|
|
void I2C_7bit_Addr_Send(I2C_Module* I2Cx, uint8_t address, uint8_t mode);
|
|
uint16_t I2C_Register_Value_Get(I2C_Module* I2Cx, uint8_t I2C_Register);
|
|
void I2C_Software_Reset_Enable(I2C_Module* I2Cx);
|
|
void I2C_Software_Reset_Disable(I2C_Module* I2Cx);
|
|
void I2C_NACK_Position_Set(I2C_Module* I2Cx, uint16_t position);
|
|
void I2C_PEC_Send_Enable(I2C_Module* I2Cx);
|
|
void I2C_PEC_Send_Disable(I2C_Module* I2Cx);
|
|
void I2C_PEC_Position_Set(I2C_Module* I2Cx, uint16_t position);
|
|
void I2C_PEC_Compute_Enable(I2C_Module* I2Cx);
|
|
void I2C_PEC_Compute_Disable(I2C_Module* I2Cx);
|
|
uint8_t I2C_PEC_Get(I2C_Module* I2Cx);
|
|
void I2C_Extend_Clock_Enable(I2C_Module* I2Cx);
|
|
void I2C_Extend_Clock_Disable(I2C_Module* I2Cx);
|
|
void I2C_Fast_Mode_Duty_Cycle_Set(I2C_Module* I2Cx, uint16_t duty_cycle);
|
|
void I2C_SDA_Digital_Filter_Width_Set(I2C_Module* I2Cx, uint8_t width);
|
|
void I2C_SCL_Digital_Filter_Width_Set(I2C_Module* I2Cx, uint8_t width);
|
|
void I2C_SDA_Analog_Filter_Width_Set(I2C_Module* I2Cx, uint16_t width);
|
|
void I2C_SDA_Analog_Filter_Enable(I2C_Module* I2Cx);
|
|
void I2C_SDA_Analog_Filter_Disable(I2C_Module* I2Cx);
|
|
void I2C_SCL_Analog_Filter_Width_Set(I2C_Module* I2Cx, uint16_t width);
|
|
void I2C_SCL_Analog_Filter_Enable(I2C_Module* I2Cx);
|
|
void I2C_SCL_Analog_Filter_Disable(I2C_Module* I2Cx);
|
|
ErrorStatus I2C_Event_Check( I2C_Module* I2Cx, uint32_t I2C_event );
|
|
uint32_t I2C_Last_Event_Get( I2C_Module* I2Cx );
|
|
FlagStatus I2C_Flag_Status_Get( I2C_Module* I2Cx, uint32_t I2C_flag );
|
|
void I2C_Flag_Status_Clear( I2C_Module* I2Cx, uint32_t I2C_flag );
|
|
ITStatus I2C_Interrupt_Status_Get( I2C_Module* I2Cx, uint32_t Interrupt );
|
|
void I2C_Interrupt_Statu_Clear(I2C_Module* I2Cx, uint32_t Interrupt);
|
|
void I2C_ByteNum_enable(I2C_Module* I2Cx);
|
|
void I2C_ByteNum_Disable(I2C_Module* I2Cx);
|
|
void I2C_Master_Received_DataBytesNum_Set(I2C_Module* I2Cx, uint16_t Number_Of_bytes);
|
|
void I2C_ByteNum_Last_StartStop_Set(I2C_Module* I2Cx, uint16_t LastStatus);
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /*__N32G003_I2C_H */
|
|
/**
|
|
*
|
|
*/
|