12 Commits

Author SHA1 Message Date
evan.liu
fb681a4b69 数码管手动管脚控制: dispauto 开关 + dispset 命令 (APP V1.00.33)
- dispauto [on|off]: 关掉自动显示扫描, 7 脚置高阻, 供手动控制
- dispset <pin1-7> [0|1|z]: 手工驱动数码管 pin1~7 (pin1=PB0..pin7=PA6)
- app_display.c: g_disp_auto + display_auto_set/get + display_pin_map,
  display_task 自动关时释放管脚并让出
- 仅 APP 改动, Boot 不动 (仍 V1.00.07)
- docs/开发日志.md: 新增 §61
2026-09-13 09:12:02 +08:00
evan.liu
a93d2919a0 CLI 新增 disp 数码管显示值命令 (APP V1.00.32)
- disp <value> [f] [hex]: 设置 7 段数码管显示数值
  - 默认十进制 1 位小数 °C; f 点亮 °F 指示段; hex 按十六进制整数显示
- 手写 cli_parse_float/cli_parse_hex (不依赖 MicroLIB atof/strtod)
- 背景: 数码管 display_task 之前无任何任务调用 display_set(), 一直显示静态 0
- 仅 APP 改动, Boot 不动 (仍 V1.00.07)
- docs/开发日志.md: 新增 §60
2026-09-12 10:14:58 +08:00
evan.liu
3d6567819a CLI 新增 pinset 管脚高低电平命令 (Boot V1.00.07 / APP V1.00.31)
- pinset <pxN> [0|1]: 设置 GPIO 输出高低 / 读当前电平 (pa0-6/pb0-13)
- Boot/src/boot_cli.c + mcm-ddc-ble/src/cli_core.c 各加一份同名命令
- 对 SWD(PA4/PA5) / 控制台(PB6/PB7) 重配前打印 warning
- Boot V1.00.06 -> V1.00.07; APP V1.00.30 -> V1.00.31 (0x0001001F)
- docs/开发日志.md: 新增 §59
2026-09-12 09:58:55 +08:00
evan.liu
e74751634b YF30137 七脚数码管显示驱动(Charlieplexing) + 取消 Boot strap 下载检测 (APP V1.00.30 / Boot V1.00.06) 2026-09-06 20:11:53 +08:00
evan.liu
5917cafb0c CLI help 增加运行模式标识 + Boot 版本号改 1.00.XX
- help 首行打印 mode: Boot 用 'mode: BOOT download' / App 用 'mode: APP'
- Boot/src/boot_version.h: V1.01.04 -> V1.00.05 (版本格式对齐 APP 的 1.00.XX)
- mcm-ddc-ble: app_version V1.00.28 -> V1.00.29 (0x0001001D)
- docs/开发日志.md: 新增 §57
2026-09-06 09:09:18 +08:00
evan.liu
f4faf68ed8 boot V1.01.00: UART download mode (CLI + OTA frame upgrade in bootloader)
- boot_usart: bare-metal USART1 460800, polled TX, 3KB DMA ring RX, SysTick millis
- boot_cli: polled line editor + mini printf + command subset; wire-compatible
  with the app UART CLI (prompt/devinfo cur bank/ota marker) so
  ble_ota_update.py --uart works unchanged against the bootloader
- share app_ota.c/app_bootset.c into the Boot build via BOOT_FIRMWARE ifdef
  (single OTA engine source); frame constants moved to shared Boot/src/ota_wire.h
- entry: 2s Enter window after the boot banner, or forced when no jumpable
  image (invalid bootsetting + APP1 vector sanity fail) - brick recovery path
- OTA target in boot = inactive bank per bootsetting (APP1 when invalid)
- merge_image.py: hard-fail when boot bin exceeds the 16KB region
- APP V1.00.28 (shared-source touch only, behavior unchanged)
- tested: normal boot / download CLI / OTA APP1<->APP2 round trip / bricked
  recovery (bootsetting+APP1 sector erased -> forced download -> OTA restore)
- docs: dev log sec.52, ble_protocol sec.6.8, AGENTS.md
2026-09-05 17:25:53 +08:00
evan.liu
e0253d1bbf fw V1.00.27: add IWDG watchdog (4s timeout, idle-hook fed with 3s task heartbeat window, DBG freeze, reset-cause banner) + 'hang' fire-test cmd 2026-09-05 13:53:20 +08:00
evan.liu
8a7cebcf77 V1.00.26: UART baud 115200 -> 460800
- firmware BSP_USART_BAUDRATE 460800 (divider error +0.03%); uartrst/
  uartinfo follow the macro
- RX DMA ring 2KB -> 3KB: at 460800 2KB only covers 44ms, less than the
  ~45ms flash-erase interrupt-off window; stack top now 0x2000BDE8
  (guard warns <1KB from the 0x2000C000 cliff, by design)
- tools: ble_ota_update.py UartTransport and uart_cap.py default baud
- Verified: stream OTA 55832B in 2.6s @23kB/s (one lost frame recovered
  by go-back-N), PASS after reboot; text CLI fine at 460800
- docs: ble_protocol.md, design spec, AGENTS.md, dev log section 48
2026-09-05 10:01:23 +08:00
evan.liu
f729d16ff2 V1.00.25: UART OTA stream mode + RX DMA ring + SRAM cliff fix
Firmware:
- bsp_usart: RX moved from RXDNE byte-queue IRQ to DMA CH2 circular ring
  (2KB) + IDLE-irq wakeup; bytes keep landing during flash-erase
  interrupt-off windows (the reason lockstep was needed before)
- app_ota: stream mode (ble_protocol.md section 6.7) - 16B BEGIN with
  flags bit0=STREAM (UART channel only), DATA acked on 4KB sector
  crossings (original chunk length; two ack-gating bugs fixed during
  field test), throttled BAD_STATE for go-back-N
- FreeRTOS heap 20KB->18KB: the 2KB ring pushed the stack top past the
  0x2000C000 SRAM cliff (probed via SWD: accesses above fault on this
  silicon, usable app SRAM is 32KB) which locked the board at boot;
  merge_image.py now hard-fails the package when the image initial SP
  leaves (0x20004000, 0x2000C000]

Tools:
- ble_ota_update.py: UART stream sender (8KB window, stall watchdog
  rewind, auto-fallback to lockstep on pre-V1.00.24 firmware,
  --lockstep to force); case-insensitive option parsing
- flash_package.py/bat: stream NSpyocd output live (chunked reads keep
  the \r progress bar), vendor banner rebranded to CAIIC NSLINK UMP
- merge_image.py: initial-SP cliff guard

Verified: UART stream OTA both directions, 55.8KB in ~5.9s @9.5kB/s
0 rewinds (lockstep was 39s), PASS after reboot; board boot fixed and
verified via SWD.

Docs: ble_protocol.md section 6.7, dev log section 47 (+ SRAM cliff
post-mortem), AGENTS.md RAM rule rewritten (both cliffs) + V1.00.25
2026-09-05 09:48:28 +08:00
evan.liu
efc7bd129f V1.00.21: UART OTA channel verified + mode-switch handshake + loss-tolerant lockstep
- UART binary mode switch mechanism: enter handshake marker '[ota] binary
  mode ON', explicit exit via OTA_ABORT (immediate), 10s idle fallback
  (was 3s, must exceed the host retry window); host resync by CR probe
- fix: otaIdleMs not re-armed on mode entry - every second 'ota' entry was
  kicked out by an instant idle timeout (leftover count from prior session)
- lossy-link tolerance: device drops partial frames after a 100ms byte gap
  so host resends re-align; OTA session is now single-owner (second BEGIN
  on another channel gets BAD_STATE)
- ble_ota_update.py: wait for the enter marker instead of blind sleeps,
  per-frame resend (2s x3), BAD_STATE+expected-offset treated as implicit
  ack for duplicate DATA/BEGIN (resync after ack loss), stage-labeled
  timeouts with raw-rx dump
- verified on hardware: UART OTA full pass (55.7KB/41s, 4-5 lost frames
  auto-recovered) + BLE OTA regression pass; docs: dev log 44,
  ble_protocol.md 6.6 rework, AGENTS.md sync
2026-09-04 20:19:00 +08:00
evan.liu
520838ce65 V1.00.20: OTA_END ack guaranteed delivery via deferred reset
- app_ota.c: after END ok, wait until the RSP is consumed by the host
  (BLE e0005 read-out / UART TX done) plus 300ms grace before resetting,
  2s timeout fallback; polled from the BLE schedule task (rwip_schedule
  must keep running for the ATT read to be processed)
- main.c: app_ota_reset_poll() in the BLE schedule task loop
- docs: ble_protocol.md 6.6 note, dev log section 43, AGENTS.md sync
2026-09-04 17:35:01 +08:00
evan.liu
a546dc5f46 mcm-ddc-ble V1.00.16~17:实测板载硅片为256KB(0x01040000起CPU读回绕/SWD fault),Flash布局回退256KB(Boot16K/bs8K/APP_DATA8K不变,APP1 0x01008000/112K,APP2 0x01024000/112K);新增appsw命令切换运行bank(记录校验+目标镜像CRC32复算防呆);uvprojx新增APP2 target(链接0x01024000,VTOR基址宏化,版本号可被target覆盖);新增make_dual_package.bat双APP整包脚本(merge_image.py支持--app2/--with-appdata);新增信息项0x07 CUR_BANK识别当前运行bank;OTA双bank配套:出包同时产bank1/bank2两份载荷(清单带target_bank),OTA_END校验镜像向量表Reset地址落在目标bank(新状态6 bank_mismatch);flash_package.bat改用DFP pack的n32wb031keq6_2 target+smart_flash=false;appsw双bank切换与CUR_BANK已实测通过;文档同步(开发日志37~39/ble_protocol.md/AGENTS.md) 2026-09-04 15:22:53 +08:00