f729d16ff2
Firmware: - bsp_usart: RX moved from RXDNE byte-queue IRQ to DMA CH2 circular ring (2KB) + IDLE-irq wakeup; bytes keep landing during flash-erase interrupt-off windows (the reason lockstep was needed before) - app_ota: stream mode (ble_protocol.md section 6.7) - 16B BEGIN with flags bit0=STREAM (UART channel only), DATA acked on 4KB sector crossings (original chunk length; two ack-gating bugs fixed during field test), throttled BAD_STATE for go-back-N - FreeRTOS heap 20KB->18KB: the 2KB ring pushed the stack top past the 0x2000C000 SRAM cliff (probed via SWD: accesses above fault on this silicon, usable app SRAM is 32KB) which locked the board at boot; merge_image.py now hard-fails the package when the image initial SP leaves (0x20004000, 0x2000C000] Tools: - ble_ota_update.py: UART stream sender (8KB window, stall watchdog rewind, auto-fallback to lockstep on pre-V1.00.24 firmware, --lockstep to force); case-insensitive option parsing - flash_package.py/bat: stream NSpyocd output live (chunked reads keep the \r progress bar), vendor banner rebranded to CAIIC NSLINK UMP - merge_image.py: initial-SP cliff guard Verified: UART stream OTA both directions, 55.8KB in ~5.9s @9.5kB/s 0 rewinds (lockstep was 39s), PASS after reboot; board boot fixed and verified via SWD. Docs: ble_protocol.md section 6.7, dev log section 47 (+ SRAM cliff post-mortem), AGENTS.md RAM rule rewritten (both cliffs) + V1.00.25
70 lines
2.4 KiB
C
70 lines
2.4 KiB
C
/**
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* @file bsp_usart.h
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* @brief USART1 support: printf retarget (polling TX), DMA TX, RX DMA
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* circular ring + IDLE interrupt. TX=PB6, RX=PB7, 115200 8N1.
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*/
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#ifndef __BSP_USART_H__
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#define __BSP_USART_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "n32wb03x.h"
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#define BSP_USARTx USART1
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#define BSP_USART_CLK RCC_APB2_PERIPH_USART1
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#define BSP_USART_GPIO GPIOB
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#define BSP_USART_GPIO_CLK RCC_APB2_PERIPH_GPIOB
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#define BSP_USART_TX_PIN GPIO_PIN_6
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#define BSP_USART_RX_PIN GPIO_PIN_7
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#define BSP_USART_TX_GPIO_AF GPIO_AF4_USART1
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#define BSP_USART_RX_GPIO_AF GPIO_AF4_USART1
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#define BSP_USART_BAUDRATE 115200
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/* USART1 TX DMA channel (remap required on this chip) */
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#define BSP_USART_TX_DMA_CH DMA_CH1
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#define BSP_USART_TX_DMA_TC DMA_FLAG_TC1
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#define BSP_USART_TX_DMA_REMAP DMA_REMAP_USART1_TX
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/* USART1 RX DMA channel: circular mode into a 2KB ring, drained by
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* bsp_usart_read_byte(). DMA keeps sampling while interrupts are off
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* (flash erase windows during UART OTA streaming). */
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#define BSP_USART_RX_DMA_CH DMA_CH2
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#define BSP_USART_RX_DMA_REMAP DMA_REMAP_USART1_RX
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#define BSP_USART_DAT_ADDR (USART1_BASE + 0x04)
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/* Pass to bsp_usart_read_byte() to block without timeout */
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#define BSP_USART_WAIT_FOREVER 0xFFFFFFFFu
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void bsp_usart_init(void);
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/* Re-apply the baud rate at runtime (keeps RX interrupt/DMA setup).
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* Used by the "uartrst" CLI command after a baud parameter change. */
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void bsp_usart_set_baud(uint32_t baud);
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/* TX: send a buffer through DMA (polled completion) */
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void bsp_usart_write_dma(const uint8_t* data, uint16_t len);
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/* RX: fetch one received byte. Source order: the inject queue (BLE
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* downlink feeding the CLI) first, then the DMA RX ring. Returns 1 on
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* success, 0 on timeout. */
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int bsp_usart_read_byte(uint8_t* ch, uint32_t timeout_ms);
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/* RX: inject bytes from task context (BLE downlink feeds the CLI through
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* this). Bytes are dropped when the inject queue is full. */
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void bsp_usart_rx_inject(const uint8_t* data, uint16_t len);
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/* TX mutex so that DMA bursts and polling printf lines do not interleave.
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* No-ops while the scheduler is not running. */
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void bsp_usart_tx_lock(void);
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void bsp_usart_tx_unlock(void);
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/* Called from USART1_IRQHandler (see n32wb03x_it.c) */
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void bsp_usart_rx_isr_handler(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* __BSP_USART_H__ */
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