mothercup/mcm-ddc-04/app/n32wb03x_it.c

82 lines
2.6 KiB
C

/**
* @file n32wb03x_it.c
* @brief Cortex-M0 exception handlers.
*
* SVC_Handler / PendSV_Handler / SysTick_Handler are NOT defined here:
* they are provided by the FreeRTOS ARM_CM0 port, mapped in FreeRTOSConfig.h:
* vPortSVCHandler -> SVC_Handler
* xPortPendSVHandler -> PendSV_Handler
* xPortSysTickHandler -> SysTick_Handler
*/
#include "n32wb03x_it.h"
#include "bsp_usart.h"
#include <stdio.h>
/******************************************************************************/
/* Cortex-M0 Processor Exceptions Handlers */
/******************************************************************************/
/**
* @brief This function handles NMI exception.
*/
void NMI_Handler(void)
{
}
/**
* @brief Read EXC_RETURN (LR value on exception entry). ARMCC embedded asm.
*/
__asm static uint32_t hardfault_exc_return(void)
{
MOV r0, lr
BX lr
}
/**
* @brief This function handles Hard Fault exception.
*
* ARMv6-M has no CFSR/HFSR, so dump the exception stack frame instead.
* Frame layout (8 words): R0 R1 R2 R3 R12 LR PC xPSR.
* EXC_RETURN bit2 selects the stack the faulting context used.
* PC (frame[6]) is the faulting instruction - look it up in the .map file.
*/
void HardFault_Handler(void)
{
uint32_t *frame = (uint32_t*)__get_MSP();
/* EXC_RETURN bit2: 0 = fault from MSP (handler/thread-msp), 1 = PSP */
if (hardfault_exc_return() & 0x4u)
{
frame = (uint32_t*)__get_PSP();
}
/* polling printf path (scheduler may not be running) */
printf("\n*** HardFault ***\n");
printf("R0 =%08lX R1 =%08lX R2 =%08lX R3 =%08lX\n",
(unsigned long)frame[0], (unsigned long)frame[1],
(unsigned long)frame[2], (unsigned long)frame[3]);
printf("R12 =%08lX LR =%08lX PC =%08lX xPSR=%08lX\n",
(unsigned long)frame[4], (unsigned long)frame[5],
(unsigned long)frame[6], (unsigned long)frame[7]);
/* Go to infinite loop when Hard Fault exception occurs */
while (1)
{
}
}
/******************************************************************************/
/* N32WB03X Peripherals Interrupt Handlers */
/* Add here the Interrupt Handler for the used peripheral(s) (PPP), for the */
/* available peripheral interrupt handler's name please refer to the startup */
/* file (startup_n32wb03x.s). */
/******************************************************************************/
/**
* @brief This function handles USART1 global interrupt (RXDNE -> RX queue).
*/
void USART1_IRQHandler(void)
{
bsp_usart_rx_isr_handler();
}