/**
 * @file dfu_layout.h
 * @brief Flash memory map and bootsetting record for the CAIIC dual-bank
 *        bootloader + OTA design (256KB flash - the boards actually carry
 *        the 256KB silicon; reads above 0x0103FFFF alias/fault, see dev
 *        log section 37).
 *
 * Layout: Boot / bootsetting / APP_DATA unchanged (16KB/8KB/8KB); the
 * remaining 224KB is split into two 112KB APP banks.
 * Shared by the bootloader (Boot/) and the application (mcm-ddc-ble/).
 */
#ifndef __DFU_LAYOUT_H__
#define __DFU_LAYOUT_H__

#ifdef __cplusplus
extern "C" {
#endif

#include <stdint.h>

/* Flash base of this chip family */
#define CAIIC_FLASH_BASE            0x01000000u

/* Region map (256KB total, ends at 0x01040000) */
#define CAIIC_BOOT_BASE             0x01000000u
#define CAIIC_BOOT_SIZE             0x00004000u   /* 16KB  bootloader */
#define CAIIC_BOOTSETTING_ADDR      0x01004000u
#define CAIIC_BOOTSETTING_SIZE      0x00002000u   /* 8KB, only one 4KB sector used */
#define CAIIC_APP_DATA_ADDR         0x01006000u
#define CAIIC_APP_DATA_SIZE         0x00002000u   /* 8KB reserved (user data) */
#define CAIIC_APP1_BASE             0x01008000u
#define CAIIC_APP_BANK_SIZE         0x0001C000u   /* 112KB per bank */
#define CAIIC_APP2_BASE             0x01024000u
#define CAIIC_IMAGE_UPDATE_BASE     0x01040000u   /* end of flash; no update region */
#define CAIIC_IMAGE_UPDATE_SIZE     0x00000000u

/* Flash erase unit */
#define CAIIC_FLASH_SECTOR_SIZE     0x1000u       /* 4KB */

/* Bootsetting record */
#define CAIIC_BOOT_MAGIC            0xCA11C011u
#define CAIIC_ACTIVE_BANK1          1u
#define CAIIC_ACTIVE_BANK2          2u

typedef struct
{
    uint32_t start_address; /* absolute jump (vector table) address of the image */
    uint32_t size;          /* image size in bytes */
    uint32_t crc32;         /* IEEE CRC32 of the whole image (verified at OTA time) */
    uint32_t version;       /* e.g. 0x010001 = V1.00.01 */
} caiic_bank_t;

typedef struct
{
    uint32_t      magic;        /* CAIIC_BOOT_MAGIC */
    uint32_t      active_bank;  /* CAIIC_ACTIVE_BANK1 / 2 */
    caiic_bank_t  bank1;
    caiic_bank_t  bank2;
    uint32_t      crc32;        /* CRC32 over all fields above this one */
} caiic_bootsetting_t;

/* Vector table remap: PWR->VTOR_REG = CAIIC_VTOR_EN | vector base */
#define CAIIC_VTOR_EN               0x80000000u

#ifdef __cplusplus
}
#endif

#endif /* __DFU_LAYOUT_H__ */