6 Commits

Author SHA1 Message Date
evan.liu
ead16ef671 V1.00.23 + OTA tool fine-grained progress display
- firmware version bump V1.00.22 -> V1.00.23 (0x00010017), no code change;
  user-verified BLE OTA (APP1->APP2) and UART OTA both PASS
- ble_ota_update.py: frame-level live progress bar on tty (bar/pct/bytes/
  rate/per-frame ack RTT, ~10fps throttled), 5%-step lines when redirected;
  resend/resync notices no longer mix into the bar line; END summary now
  reports resent/resynced counters; BEGIN/END stage banners
- docs: dev log 46, AGENTS.md sync
2026-09-04 21:33:25 +08:00
evan.liu
5dcbdbad65 V1.00.22 + OTA tool bank-misselection fix (triple protection)
- firmware: version bump to V1.00.22 (0x00010016), no code change
- ble_ota_update.py: cur-bank detection now reads the full devinfo output
  and parses strictly (early break at the 'cur bank:' prefix could miss
  'APP2' and silently default to APP1 -> wrong payload selection, caught
  by the device bank_mismatch guard on hardware)
- new pre-flight check_blob_bank(): payload vector reset PC must land in
  the target bank before transferring (BLE and UART paths)
- UART path: post-reboot verification over the text CLI (bank+version),
  deterministic PASS/FAIL like the BLE path
- verified: UART OTA APP2->APP1 V1.00.22 full pass with auto-verify
- docs: dev log 45, AGENTS.md sync
2026-09-04 20:49:15 +08:00
evan.liu
efc7bd129f V1.00.21: UART OTA channel verified + mode-switch handshake + loss-tolerant lockstep
- UART binary mode switch mechanism: enter handshake marker '[ota] binary
  mode ON', explicit exit via OTA_ABORT (immediate), 10s idle fallback
  (was 3s, must exceed the host retry window); host resync by CR probe
- fix: otaIdleMs not re-armed on mode entry - every second 'ota' entry was
  kicked out by an instant idle timeout (leftover count from prior session)
- lossy-link tolerance: device drops partial frames after a 100ms byte gap
  so host resends re-align; OTA session is now single-owner (second BEGIN
  on another channel gets BAD_STATE)
- ble_ota_update.py: wait for the enter marker instead of blind sleeps,
  per-frame resend (2s x3), BAD_STATE+expected-offset treated as implicit
  ack for duplicate DATA/BEGIN (resync after ack loss), stage-labeled
  timeouts with raw-rx dump
- verified on hardware: UART OTA full pass (55.7KB/41s, 4-5 lost frames
  auto-recovered) + BLE OTA regression pass; docs: dev log 44,
  ble_protocol.md 6.6 rework, AGENTS.md sync
2026-09-04 20:19:00 +08:00
evan.liu
520838ce65 V1.00.20: OTA_END ack guaranteed delivery via deferred reset
- app_ota.c: after END ok, wait until the RSP is consumed by the host
  (BLE e0005 read-out / UART TX done) plus 300ms grace before resetting,
  2s timeout fallback; polled from the BLE schedule task (rwip_schedule
  must keep running for the ATT read to be processed)
- main.c: app_ota_reset_poll() in the BLE schedule task loop
- docs: ble_protocol.md 6.6 note, dev log section 43, AGENTS.md sync
2026-09-04 17:35:01 +08:00
evan.liu
266fcec731 mcm-ddc-ble V1.00.18:发布命名整理(生产整包mothercup_ble_prod,OTA单文件发布件mothercup_ble_ota);合并OTA包头扩为52B(新增hdr_len/total_size/payload_crc,原json清单信息全部收进头部,单文件发布);merge_image.py新增--combo-name;ble_ota_update.py/ble_ota.bat PC端BLE OTA升级器(实验性:CUR_BANK选包/扇区擦除避让节流/复位检测,实机调通中);SWD单bank升级流程实测通过(bin\@基址部分烧录+bsset修记录+appsw切入);格式与升级流程写入ble_protocol.md §7供App/UART升级开发;开发日志40~41 2026-09-04 16:01:41 +08:00
evan.liu
a546dc5f46 mcm-ddc-ble V1.00.16~17:实测板载硅片为256KB(0x01040000起CPU读回绕/SWD fault),Flash布局回退256KB(Boot16K/bs8K/APP_DATA8K不变,APP1 0x01008000/112K,APP2 0x01024000/112K);新增appsw命令切换运行bank(记录校验+目标镜像CRC32复算防呆);uvprojx新增APP2 target(链接0x01024000,VTOR基址宏化,版本号可被target覆盖);新增make_dual_package.bat双APP整包脚本(merge_image.py支持--app2/--with-appdata);新增信息项0x07 CUR_BANK识别当前运行bank;OTA双bank配套:出包同时产bank1/bank2两份载荷(清单带target_bank),OTA_END校验镜像向量表Reset地址落在目标bank(新状态6 bank_mismatch);flash_package.bat改用DFP pack的n32wb031keq6_2 target+smart_flash=false;appsw双bank切换与CUR_BANK已实测通过;文档同步(开发日志37~39/ble_protocol.md/AGENTS.md) 2026-09-04 15:22:53 +08:00