717 lines
33 KiB
C
717 lines
33 KiB
C
/**
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* Copyright (c) 2022, Nations Technologies Inc.
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*
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* All rights reserved.
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*
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* This software is the exclusive property of Nations Technologies Inc. (Hereinafter
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* referred to as NATIONS). This software, and the product of NATIONS described herein
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* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties
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* of the People's Republic of China and other applicable jurisdictions worldwide.
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*
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* NATIONS does not grant any license under its patents, copyrights, trademarks, or other
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* intellectual property rights. Names and brands of third party may be mentioned or referred
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* thereto (if any) for identification purposes only.
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*
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* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and
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* improvements to this software at any time without notice. Please contact NATIONS and obtain
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* the latest version of this software before placing orders.
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* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes
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* no responsibility for the accuracy and reliability of this software.
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*
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* It is the responsibility of the user of this software to properly design, program, and test
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* the functionality and safety of any application made of this information and any resulting product.
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* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or
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* consequential damages arising in any way out of the use of this software or the Product.
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*
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* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any
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* malfunction or failure of which may cause loss of human life, bodily injury or severe property
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* damage. Such applications are deemed, "Insecure Usage".
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*
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* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS
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* harmless from and against all claims, costs, damages, and other liabilities, arising from or related
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* to any customer's Insecure Usage.
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* Any express or implied warranty with regard to this software or the Product, including,but not
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* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement
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* are disclaimed to the fullest extent permitted by law.
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* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe
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* or otherwise distribute this software for any purposes, in whole or in part.
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*
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* NATIONS products and technologies shall not be used for or incorporated into any products or systems
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* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations.
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* User shall comply with any applicable export control laws and regulations promulgated and administered by
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* the governments of any countries asserting jurisdiction over the parties or transactions.
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**/
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/**
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*\*\file n32g003_tim.h
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*\*\author Nations
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*\*\version v1.0.0
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*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
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**/
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#ifndef __N32G003_TIM_H__
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#define __N32G003_TIM_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "n32g003.h"
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#include "stdbool.h"
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/**
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*\*\brief TIM Time Base Init structure definition
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*\*\note This structure is used with all TIMx except for TIM6 and TIM7.
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**/
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typedef struct
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{
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uint16_t Prescaler; /* Specifies the prescaler value used to divide the TIM clock.
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This parameter can be a number between 0x0000 and 0xFFFF */
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uint16_t CntMode; /* Specifies the counter mode.
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This parameter can be a value of TIM_Counter_Mode */
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uint16_t Period; /* Specifies the period value to be loaded into the active
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Auto-Reload Register at the next update event.
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This parameter must be a number between 0x0000 and 0xFFFF. */
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uint16_t ClkDiv; /* Specifies the clock division.
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This parameter can be a value of TIM_Clock_Division_CKD */
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uint8_t RepetCnt; /* Specifies the repetition counter value. Each time the REPCNT downcounter
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reaches zero, an update event is generated and counting restarts
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from the REPCNT value (N).
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This means in PWM mode that (N+1) corresponds to:
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- the number of PWM periods in edge-aligned mode
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- the number of half PWM period in center-aligned mode
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This parameter must be a number between 0x00 and 0xFF.
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@note This parameter is valid only for TIM1 and TIM8. */
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bool CapCh1Sel; /* channel 1 select capture in from comp if 1, from IOM if 0
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Tim1,Tim3 valid*/
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bool CapEtrClrFromCompEn; /* etr clearref select from comp if 1, from ETR IOM if 0
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Tim1,Tim3 valid*/
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bool CapEtrSelFromTscEn;
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} TIM_TimeBaseInitType;
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/**
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*\*\brief TIM Output Compare Init structure definition
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**/
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typedef struct
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{
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uint16_t OcMode; /* Specifies the TIM mode.
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This parameter can be a value of TIM_Output_Compare_and_PWM_modes */
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uint16_t OutputState; /* Specifies the TIM Output Compare state.
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This parameter can be a value of TIM_Output_Compare_state */
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uint16_t OutputNState; /* Specifies the TIM complementary Output Compare state.
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This parameter can be a value of TIM_Output_Compare_N_state
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- note This parameter is valid only for TIM1. */
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uint16_t Pulse; /* Specifies the pulse value to be loaded into the Capture Compare Register.
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This parameter can be a number between 0x0000 and 0xFFFF */
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uint16_t OcPolarity; /* Specifies the output polarity.
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This parameter can be a value of TIM_Output_Compare_Polarity */
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uint16_t OcNPolarity; /* Specifies the complementary output polarity.
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This parameter can be a value of TIM_Output_Compare_N_Polarity
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- note This parameter is valid only for TIM1. */
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uint16_t OcIdleState; /* Specifies the TIM Output Compare pin state during Idle state.
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This parameter can be a value of TIM_Output_Compare_Idle_State
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- note This parameter is valid only for TIM1. */
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uint16_t OcNIdleState; /* Specifies the TIM Output Compare pin state during Idle state.
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This parameter can be a value of TIM_Output_Compare_N_Idle_State
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- note This parameter is valid only for TIM1. */
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} OCInitType;
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/**
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*\*\brief TIM Input Capture Init structure definition
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**/
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typedef struct
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{
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uint16_t Channel; /*! Specifies the TIM channel.This parameter can be a value of Channel */
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uint16_t IcPolarity; /* Specifies the active edge of the input signal. */
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uint16_t IcSelection; /* Specifies the input. */
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uint16_t IcPrescaler; /* Specifies the Input Capture Prescaler. */
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uint16_t IcFilter; /* Specifies the input capture filter. */
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} TIM_ICInitType;
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/**
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*\*\brief BKDT structure definition
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*\*\note This structure is used only with TIM1 and TIM8.
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**/
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typedef struct
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{
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uint16_t OssrState; /* Specifies the Off-State selection used in Run mode.
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This parameter can be a value of OSSR_Off_State_Selection_for_Run_mode_state */
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uint16_t OssiState; /* Specifies the Off-State used in Idle state.
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This parameter can be a value of OSSI_Off_State_Selection_for_Idle_mode_state */
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uint16_t LockLevel; /* Specifies the LOCK level parameters.
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This parameter can be a value of Lock_level */
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uint16_t DeadTime; /* Specifies the delay time between the switching-off and the
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switching-on of the outputs.
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This parameter can be a number between 0x00 and 0xFF */
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uint16_t Break; /* Specifies whether the TIM Break input is enabled or not.
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This parameter can be a value of Break_Input_enable_disable */
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uint16_t BreakPolarity; /* Specifies the TIM Break Input pin polarity.
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This parameter can be a value of Break_Polarity */
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uint16_t AutomaticOutput; /* Specifies whether the TIM Automatic Output feature is enabled or not.
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This parameter can be a value of TIM_AOE_Bit_Set_Reset */
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bool IomBreakEn; /* EXTENDMODE valid, open iom as break in*/
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bool LockUpBreakEn; /* EXTENDMODE valid, open lockup(hardfault) as break in*/
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bool PvdBreakEn; /* EXTENDMODE valid, open pvd(sys voltage too high or too low) as break in*/
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} TIM_BDTRInitType;
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#define TIM_REG16_BIT_ZERO ((uint16_t)0x0000)
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#define TIM_REG32_BIT_ZERO ((uint32_t)0x00000000)
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#define TIM_AR_PRELOAD_MASK (TIM_CTRL1_ARPEN)
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/** TIM_AR_PRELOAD **/
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#define TIM_AR_PRELOAD_ENABLE (TIM_CTRL1_ARPEN)
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#define TIM_AR_PRELOAD_DISABLE (TIM_REG32_BIT_ZERO)
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#define TIM_UPRS_MASK (TIM_CTRL1_UPRS)
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/** TIM_Update_Source **/
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#define TIM_UPRS_GLOBAL (TIM_REG32_BIT_ZERO)
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#define TIM_UPRS_REGULAR (TIM_CTRL1_UPRS)
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#define TIM_UPDATE_SRC_GLOBAL (TIM_REG16_BIT_ZERO) /* Source of update is the counter overflow/underflow \
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or the setting of UG bit, or an update generation \
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through the slave mode controller. */
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#define TIM_UPDATE_SRC_REGULAR ((uint16_t)0x0001) /* Source of update is counter overflow/underflow. */
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#define TIM_UPDIS_MASK (TIM_CTRL1_UPDIS)
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/** TIM_Update_Disable **/
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#define TIM_UPDATE_EVENT_DISABLE (TIM_CTRL1_UPDIS)
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#define TIM_UPDATE_EVENT_ENABLE (TIM_REG32_BIT_ZERO)
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#define TIM_ON_MASK (TIM_CTRL1_CNTEN)
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/** TIM_On **/
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#define TIM_ON (TIM_CTRL1_CNTEN)
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/* TIM_Break_In_Source */
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#define TIM_LOCKUP_AS_BREAK_IN (TIM_CTRL1_LBKPEN)
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#define TIM_PVD_AS_BREAK_IN (TIM_CTRL1_PBKPEN)
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#define TIM_COMP_AS_BREAK_IN (TIM_CTRL1_IOMBKPEN)
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#define TIM_CCUSEL_MASK (TIM_CTRL2_CCUSEL)
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/** TIM_CCUSEL **/
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#define TIM_CCUSEL_COM_AND_TRIG (TIM_CTRL2_CCUSEL)
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#define TIM_CCUSEL_COM (TIM_REG32_BIT_ZERO)
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/** TIM_CCPCTL **/
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#define TIM_CCPCTL_MASK (TIM_CTRL2_CCPCTL)
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#define TIM_CCPCTL_PRELOAD (TIM_CTRL2_CCPCTL)
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#define TIM_CCPCTL_NOT_PRELOAD (TIM_REG32_BIT_ZERO)
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/** TIM_REPCNT MASK**/
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#define TIM_REPCNT_MASK (TIM_REPCNT_REPCNT)
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#define TIM_OC1MODE_MASK (TIM_CCMOD1_OC1MD)
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#define TIM_OC2MODE_MASK (TIM_CCMOD1_OC2MD)
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#define TIM_OC3MODE_MASK (TIM_CCMOD2_OC3MD)
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#define TIM_OC4MODE_MASK (TIM_CCMOD2_OC4MD)
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#define TIM_OC5MODE_MASK (TIM_CCMOD3_OC5MD)
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/** TIM_Output_Compare_and_PWM_modes**/
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#define TIM_OCMODE_TIMING (TIM_REG16_BIT_ZERO)
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#define TIM_OCMODE_ACTIVE (TIM_CCMOD1_OC1MD_0)
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#define TIM_OCMODE_INACTIVE (TIM_CCMOD1_OC1MD_1)
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#define TIM_OCMODE_TOGGLE (TIM_CCMOD1_OC1MD_0 | TIM_CCMOD1_OC1MD_1)
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#define TIM_OCMODE_PWM1 (TIM_CCMOD1_OC1MD_2 | TIM_CCMOD1_OC1MD_1)
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#define TIM_OCMODE_PWM2 (TIM_CCMOD1_OC1MD_2 | TIM_CCMOD1_OC1MD_1 | TIM_CCMOD1_OC1MD_2 | TIM_CCMOD1_OC1MD_0)
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#define TIM_FORCED_ACTION_ACTIVE (TIM_CCMOD1_OC1MD_2 | TIM_CCMOD1_OC1MD_0)
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#define TIM_FORCED_ACTION_INACTIVE (TIM_CCMOD1_OC1MD_2)
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#define TIM_OPMODE_MASK (TIM_CTRL1_ONEPM)
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/** TIM_One_Pulse_Mode **/
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#define TIM_OPMODE_SINGLE (TIM_CTRL1_ONEPM)
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#define TIM_OPMODE_REPET (TIM_REG16_BIT_ZERO)
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/** Channel **/
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#define TIM_CH_1 ((uint16_t)0x0000)
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#define TIM_CH_2 ((uint16_t)0x0004)
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#define TIM_CH_3 ((uint16_t)0x0008)
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#define TIM_CH_4 ((uint16_t)0x000C)
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#define TIM_CH_5 ((uint16_t)0x0010)
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#define TIM_CLK_DIV_MASK (TIM_CTRL1_CLKD)
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/** TIM_Clock_Division_CKD **/
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#define TIM_CLK_DIV1 (TIM_REG16_BIT_ZERO)
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#define TIM_CLK_DIV2 (TIM_CTRL1_CLKD_0)
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#define TIM_CLK_DIV4 (TIM_CTRL1_CLKD_1)
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#define TIM_CNT_MODE_MASK (TIM_CTRL1_DIR | TIM_CTRL1_CAMSEL)
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/** TIM_Counter_Mode **/
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#define TIM_CNT_MODE_UP (TIM_REG16_BIT_ZERO)
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#define TIM_CNT_MODE_DOWN (TIM_CTRL1_DIR)
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#define TIM_CNT_MODE_CENTER_ALIGN1 (TIM_CTRL1_CAMSEL_0)
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#define TIM_CNT_MODE_CENTER_ALIGN2 (TIM_CTRL1_CAMSEL_1)
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#define TIM_CNT_MODE_CENTER_ALIGN3 (TIM_CTRL1_CAMSEL_1 | TIM_CTRL1_CAMSEL_0)
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/** TIM_CHxSEL **/
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#define TIM_CH1_SEL (TIM_CTRL1_C1SEL)
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/** TIM_OCREF_CLEAR_SEL **/
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#define TIM_OCREF_CLEAR_SEL (TIM_CTRL1_CLRSEL)
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/** TIM_TI1_SEL **/
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#define TIM_TI1_SEL (TIM_CTRL2_TI1SEL)
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/** TIM_ETR_Selection **/
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#define TIM_ETR_SEL (TIM_CTRL2_TSCSEL)
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#define TIM_OC_POLARITY_MASK (TIM_CCEN_CC1P)
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/** TIM_Output_Compare_Polarity **/
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#define TIM_OC_POLARITY_HIGH (TIM_REG16_BIT_ZERO)
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#define TIM_OC_POLARITY_LOW (TIM_CCEN_CC1P)
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#define TIM_OCN_POLARITY_MASK (TIM_CCEN_CC1NP)
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/** TIM_Output_Compare_N_Polarity **/
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#define TIM_OCN_POLARITY_HIGH (TIM_REG16_BIT_ZERO)
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#define TIM_OCN_POLARITY_LOW (TIM_CCEN_CC1NP)
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/** TIM_Output_Compare_state **/
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#define TIM_OUTPUT_STATE_DISABLE (TIM_REG16_BIT_ZERO)
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#define TIM_OUTPUT_STATE_ENABLE (TIM_CCEN_CC1EN)
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/** TIM_Output_Compare_N_state **/
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#define TIM_OUTPUT_NSTATE_DISABLE (TIM_REG16_BIT_ZERO)
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#define TIM_OUTPUT_NSTATE_ENABLE (TIM_CCEN_CC1NEN)
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/** TIM_Capture_Compare_state **/
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#define TIM_CAP_CMP_ENABLE (TIM_CCEN_CC1EN)
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#define TIM_CAP_CMP_DISABLE (TIM_REG16_BIT_ZERO)
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/** TIM_Capture_Compare_N_state **/
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#define TIM_CAP_CMP_N_ENABLE (TIM_CCEN_CC1NEN)
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#define TIM_CAP_CMP_N_DISABLE (TIM_REG16_BIT_ZERO)
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/** Break_Input_enable_disable **/
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#define TIM_BREAK_IN_ENABLE (TIM_BKDT_BKEN)
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#define TIM_BREAK_IN_DISABLE (TIM_REG16_BIT_ZERO)
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/** Break_Polarity **/
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#define TIM_BREAK_POLARITY_LOW (TIM_REG16_BIT_ZERO)
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#define TIM_BREAK_POLARITY_HIGH (TIM_BKDT_BKP)
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/** TIM_AOEN_Bit_Set_Reset **/
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#define TIM_AUTO_OUTPUT_ENABLE (TIM_BKDT_AOEN)
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#define TIM_AUTO_OUTPUT_DISABLE (TIM_REG16_BIT_ZERO)
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/** TIM_MOEN_Bit_Set_Reset **/
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#define TIM_MAIN_OUTPUT_ENABLE (TIM_BKDT_MOEN)
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#define TIM_MAIN_OUTPUT_DISABLE (TIM_REG16_BIT_ZERO)
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/** Lock_level **/
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#define TIM_LOCK_LEVEL_OFF (TIM_REG16_BIT_ZERO)
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#define TIM_LOCK_LEVEL_1 (TIM_BKDT_LCKCFG_0)
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#define TIM_LOCK_LEVEL_2 (TIM_BKDT_LCKCFG_1)
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#define TIM_LOCK_LEVEL_3 (TIM_BKDT_LCKCFG_1 | TIM_BKDT_LCKCFG_0)
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/** OSSI_Off_State_Selection_for_Idle_mode_state **/
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#define TIM_OSSI_STATE_ENABLE (TIM_BKDT_OSSI)
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#define TIM_OSSI_STATE_DISABLE (TIM_REG16_BIT_ZERO)
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/** OSSR_Off_State_Selection_for_Run_mode_state **/
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#define TIM_OSSR_STATE_ENABLE (TIM_BKDT_OSSR)
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#define TIM_OSSR_STATE_DISABLE (TIM_REG16_BIT_ZERO)
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#define TIM_OC1_IDLE_STATE_MASK (TIM_CTRL2_OI1)
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#define TIM_OC2_IDLE_STATE_MASK (TIM_CTRL2_OI2)
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#define TIM_OC3_IDLE_STATE_MASK (TIM_CTRL2_OI3)
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#define TIM_OC4_IDLE_STATE_MASK (TIM_CTRL2_OI4)
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#define TIM_OC5_IDLE_STATE_MASK (TIM_CTRL2_OI5)
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/** TIM_Output_Compare_Idle_State **/
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#define TIM_OC_IDLE_STATE_SET (TIM_CTRL2_OI1)
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#define TIM_OC_IDLE_STATE_RESET (TIM_REG16_BIT_ZERO)
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#define TIM_OC1N_IDLE_STATE_MASK (TIM_CTRL2_OI1N)
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#define TIM_OC2N_IDLE_STATE_MASK (TIM_CTRL2_OI2N)
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#define TIM_OC3N_IDLE_STATE_MASK (TIM_CTRL2_OI3N)
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/** TIM_Output_Compare_N_Idle_State **/
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#define TIM_OCN_IDLE_STATE_SET (TIM_CTRL2_OI1N)
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#define TIM_OCN_IDLE_STATE_RESET (TIM_REG16_BIT_ZERO)
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/** TIM_Input_Capture_Polarity **/
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#define TIM_IC_POLARITY_RISING (TIM_REG16_BIT_ZERO)
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#define TIM_IC_POLARITY_FALLING (TIM_CCEN_CC1P)
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#define TIM_IC_POLARITY_BOTHEDGE (TIM_CCEN_CC1P | TIM_CCEN_CC1NP)
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#define TIM_IC1_SELECTION_MASK (TIM_CCMOD1_CC1SEL)
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#define TIM_IC2_SELECTION_MASK (TIM_CCMOD1_CC2SEL)
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#define TIM_IC3_SELECTION_MASK (TIM_CCMOD2_CC3SEL)
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#define TIM_IC4_SELECTION_MASK (TIM_CCMOD2_CC4SEL)
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/** TIM_Input_Capture_Selection **/
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#define TIM_IC_SELECTION_DIRECTTI (TIM_CCMOD1_CC1SEL_0) /* TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */
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#define TIM_IC_SELECTION_INDIRECTTI (TIM_CCMOD1_CC1SEL_1) /* TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively. */
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#define TIM_IC_SELECTION_TRC (TIM_CCMOD1_CC1SEL_1 | TIM_CCMOD1_CC1SEL_0) /* TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
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/** TIM_Input_Capture1_Filter **/
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#define TIM_IC1_FILTER_MASK (TIM_CCMOD1_IC1F)
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/** TIM_Input_Capture2_Filter **/
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#define TIM_IC2_FILTER_MASK (TIM_CCMOD1_IC2F)
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/** TIM_Input_Capture3_Filter **/
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#define TIM_IC3_FILTER_MASK (TIM_CCMOD2_IC3F)
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/** TIM_Input_Capture4_Filter **/
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#define TIM_IC4_FILTER_MASK (TIM_CCMOD2_IC4F)
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#define TIM_IC1_PSC_MASK (TIM_CCMOD1_IC1PSC)
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#define TIM_IC2_PSC_MASK (TIM_CCMOD1_IC2PSC)
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#define TIM_IC3_PSC_MASK (TIM_CCMOD2_IC3PSC)
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#define TIM_IC4_PSC_MASK (TIM_CCMOD2_IC4PSC)
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/** TIM_Input_Capture_Prescaler **/
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#define TIM_IC_PSC_DIV1 (TIM_REG16_BIT_ZERO)
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#define TIM_IC_PSC_DIV2 (TIM_CCMOD1_IC1PSC_0) /* Capture performed once every 2 events. */
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#define TIM_IC_PSC_DIV4 (TIM_CCMOD1_IC1PSC_1) /* Capture performed once every 4 events. */
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#define TIM_IC_PSC_DIV8 (TIM_CCMOD1_IC1PSC_1 | TIM_CCMOD1_IC1PSC_0) /* Capture performed once every 8 events. */
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/** TIM_interrupt_sources **/
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#define TIM_INT_UPDATE (TIM_STS_UDITF)
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#define TIM_INT_CC1 (TIM_STS_CC1ITF)
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#define TIM_INT_CC2 (TIM_STS_CC2ITF)
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#define TIM_INT_CC3 (TIM_STS_CC3ITF)
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#define TIM_INT_CC4 (TIM_STS_CC4ITF)
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#define TIM_INT_COM (TIM_STS_COMITF)
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#define TIM_INT_TRIG (TIM_STS_TITF)
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#define TIM_INT_BREAK (TIM_STS_BITF)
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/** TIM_External_Trigger_Prescaler **/
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#define TIM_EXT_TRG_PSC_MASK (TIM_SMCTRL_EXTPS)
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#define TIM_EXT_TRG_PSC_OFF (TIM_REG16_BIT_ZERO)
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#define TIM_EXT_TRG_PSC_DIV2 (TIM_SMCTRL_EXTPS_0)
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#define TIM_EXT_TRG_PSC_DIV4 (TIM_SMCTRL_EXTPS_1)
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#define TIM_EXT_TRG_PSC_DIV8 (TIM_SMCTRL_EXTPS_1 | TIM_SMCTRL_EXTPS_0)
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#define TIM_TRIG_SEL_MASK (TIM_SMCTRL_TSEL)
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/** TIM_Internal_Trigger_Selection **/
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#define TIM_TRIG_SEL_IN_TR0 (TIM_REG16_BIT_ZERO)
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#define TIM_TRIG_SEL_IN_TR1 (TIM_SMCTRL_TSEL_0)
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#define TIM_TRIG_SEL_IN_TR2 (TIM_SMCTRL_TSEL_1)
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#define TIM_TRIG_SEL_IN_TR3 (TIM_SMCTRL_TSEL_1 | TIM_SMCTRL_TSEL_0)
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#define TIM_TRIG_SEL_TI1F_ED (TIM_SMCTRL_TSEL_2)
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#define TIM_TRIG_SEL_TI1FP1 (TIM_SMCTRL_TSEL_2 | TIM_SMCTRL_TSEL_0)
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#define TIM_TRIG_SEL_TI2FP2 (TIM_SMCTRL_TSEL_2 | TIM_SMCTRL_TSEL_1)
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#define TIM_TRIG_SEL_ETRF (TIM_SMCTRL_TSEL_2 | TIM_SMCTRL_TSEL_1 | TIM_SMCTRL_TSEL_0)
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/** TIM_TIx_External_Clock_Source **/
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#define TIM_EXT_CLK_SRC_TI1 (TIM_SMCTRL_TSEL_2 | TIM_SMCTRL_TSEL_0)
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#define TIM_EXT_CLK_SRC_TI2 (TIM_SMCTRL_TSEL_2 | TIM_SMCTRL_TSEL_1)
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#define TIM_EXT_CLK_SRC_TI1ED (TIM_SMCTRL_TSEL_2)
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/** TIM_External_Trigger_Polarity **/
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#define TIM_EXT_TRIG_POLARITY_INVERTED (TIM_SMCTRL_EXTP)
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#define TIM_EXT_TRIG_POLARITY_NONINVERTED (TIM_REG16_BIT_ZERO)
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/** TIM_TIx_External_Clock_Filter **/
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#define TIM_EXT_TRIG_FILTER_MASK (TIM_SMCTRL_EXTF)
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/** TIM_External_Clock_Mode2 **/
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#define TIM_EXT_CLOCK_MODE2_ENABLE (TIM_SMCTRL_EXCEN)
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#define TIM_PSC_RELOAD_MODE_MASK (TIM_EVTGEN_UDGN)
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/** TIM_Prescaler_Reload_Mode **/
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#define TIM_PSC_RELOAD_MODE_UPDATE (TIM_REG16_BIT_ZERO)
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#define TIM_PSC_RELOAD_MODE_IMMEDIATE (TIM_EVTGEN_UDGN)
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/** TIM_Event_Source **/
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#define TIM_EVT_SRC_UPDATE (TIM_EVTGEN_UDGN)
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#define TIM_EVT_SRC_CC1 (TIM_EVTGEN_CC1GN)
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#define TIM_EVT_SRC_CC2 (TIM_EVTGEN_CC2GN)
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#define TIM_EVT_SRC_CC3 (TIM_EVTGEN_CC3GN)
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#define TIM_EVT_SRC_CC4 (TIM_EVTGEN_CC4GN)
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#define TIM_EVT_SRC_COM (TIM_EVTGEN_CCUDGN)
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#define TIM_EVT_SRC_TRIG (TIM_EVTGEN_TGN)
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#define TIM_EVT_SRC_BREAK (TIM_EVTGEN_BGN)
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#define TIM_OC1_PRELOAD_MASK (TIM_CCMOD1_OC1PEN)
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#define TIM_OC2_PRELOAD_MASK (TIM_CCMOD1_OC2PEN)
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#define TIM_OC3_PRELOAD_MASK (TIM_CCMOD2_OC3PEN)
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#define TIM_OC4_PRELOAD_MASK (TIM_CCMOD2_OC4PEN)
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#define TIM_OC5_PRELOAD_MASK (TIM_CCMOD3_OC5PEN)
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/** TIM_Output_Compare_Preload_State **/
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#define TIM_OC_PRELOAD_ENABLE (TIM_CCMOD1_OC1PEN)
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#define TIM_OC_PRELOAD_DISABLE (TIM_REG16_BIT_ZERO)
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#define TIM_OC1_FAST_MASK (TIM_CCMOD1_OC1FEN)
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#define TIM_OC2_FAST_MASK (TIM_CCMOD1_OC2FEN)
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#define TIM_OC3_FAST_MASK (TIM_CCMOD2_OC3FEN)
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#define TIM_OC4_FAST_MASK (TIM_CCMOD2_OC4FEN)
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#define TIM_OC5_FAST_MASK (TIM_CCMOD3_OC5FEN)
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/** TIM_Output_Compare_Fast_State **/
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#define TIM_OC_FAST_ENABLE (TIM_CCMOD1_OC1FEN)
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#define TIM_OC_FAST_DISABLE (TIM_REG16_BIT_ZERO)
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#define TIM_OC1_CLEAR_MASK (TIM_CCMOD1_OC1CEN)
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#define TIM_OC2_CLEAR_MASK (TIM_CCMOD1_OC2CEN)
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#define TIM_OC3_CLEAR_MASK (TIM_CCMOD2_OC3CEN)
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#define TIM_OC4_CLEAR_MASK (TIM_CCMOD2_OC4CEN)
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#define TIM_OC5_CLEAR_MASK (TIM_CCMOD3_OC5CEN)
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/** TIM_Output_Compare_Clear_State **/
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#define TIM_OC_CLEAR_ENABLE (TIM_CCMOD1_OC1CEN)
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#define TIM_OC_CLEAR_DISABLE (TIM_REG16_BIT_ZERO)
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#define TIM_TRGO_SRC_MASK (TIM_CTRL2_MMSEL)
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/** TIM_Trigger_Output_Source **/
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#define TIM_TRGO_SRC_RESET (TIM_REG16_BIT_ZERO)
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#define TIM_TRGO_SRC_ENABLE (TIM_CTRL2_MMSEL_0)
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#define TIM_TRGO_SRC_UPDATE (TIM_CTRL2_MMSEL_1)
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#define TIM_TRGO_SRC_OC1 (TIM_CTRL2_MMSEL_1 | TIM_CTRL2_MMSEL_0)
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#define TIM_TRGO_SRC_OC1REF (TIM_CTRL2_MMSEL_2)
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#define TIM_TRGO_SRC_OC2REF (TIM_CTRL2_MMSEL_2 | TIM_CTRL2_MMSEL_0)
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#define TIM_TRGO_SRC_OC3REF (TIM_CTRL2_MMSEL_2 | TIM_CTRL2_MMSEL_1)
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#define TIM_TRGO_SRC_OC4REF (TIM_CTRL2_MMSEL_2 | TIM_CTRL2_MMSEL_1 | TIM_CTRL2_MMSEL_0)
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/** ETR selection **/
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#define TIM_ETR_Seletct_ExtGpio (TIM_REG16_BIT_ZERO)
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#define TIM_ETR_Seletct_innerTsc (TIM_CTRL2_TSCSEL)
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#define TIM_SLAVE_MODE_MASK (TIM_SMCTRL_SMSEL)
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/** TIM_Slave_Mode **/
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#define TIM_SLAVE_MODE_RESET (TIM_SMCTRL_SMSEL_2)
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#define TIM_SLAVE_MODE_GATED (TIM_SMCTRL_SMSEL_2 | TIM_SMCTRL_SMSEL_0)
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#define TIM_SLAVE_MODE_TRIG (TIM_SMCTRL_SMSEL_2 | TIM_SMCTRL_SMSEL_1)
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#define TIM_SLAVE_MODE_EXT1 (TIM_SMCTRL_SMSEL_2 | TIM_SMCTRL_SMSEL_1 | TIM_SMCTRL_SMSEL_0)
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#define TIM_MASTER_SLAVE_MODE_MASK (TIM_SMCTRL_MSMD)
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/** TIM_Master_Slave_Mode **/
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#define TIM_MASTER_SLAVE_MODE_ENABLE (TIM_SMCTRL_MSMD)
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#define TIM_MASTER_SLAVE_MODE_DISABLE (TIM_REG16_BIT_ZERO)
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/** TIM_Flags **/
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#define TIM_FLAG_UPDATE (TIM_STS_UDITF)
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#define TIM_FLAG_CC1 (TIM_STS_CC1ITF)
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#define TIM_FLAG_CC2 (TIM_STS_CC2ITF)
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#define TIM_FLAG_CC3 (TIM_STS_CC3ITF)
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#define TIM_FLAG_CC4 (TIM_STS_CC4ITF)
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#define TIM_FLAG_COM (TIM_STS_COMITF)
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#define TIM_FLAG_TRIG (TIM_STS_TITF)
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#define TIM_FLAG_BREAK (TIM_STS_BITF)
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#define TIM_FLAG_CC1OF (TIM_STS_CC1OCF)
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#define TIM_FLAG_CC2OF (TIM_STS_CC2OCF)
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#define TIM_FLAG_CC3OF (TIM_STS_CC3OCF)
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#define TIM_FLAG_CC4OF (TIM_STS_CC4OCF)
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#define TIM_FLAG_CC5 (TIM_STS_CC5ITF)
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/** TIM_CCxEN **/
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#define TIM_CC1EN (TIM_CCEN_CC1EN)
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#define TIM_CC1NEN (TIM_CCEN_CC1NEN)
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#define TIM_CC2EN (TIM_CCEN_CC2EN)
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#define TIM_CC2NEN (TIM_CCEN_CC2NEN)
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#define TIM_CC3EN (TIM_CCEN_CC3EN)
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#define TIM_CC3NEN (TIM_CCEN_CC3NEN)
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#define TIM_CC4EN (TIM_CCEN_CC4EN)
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#define TIM_CC5EN (TIM_CCEN_CC5EN)
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/** TIM_CCxP **/
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#define TIM_CC1P (TIM_CCEN_CC1P)
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#define TIM_CC1NP (TIM_CCEN_CC1NP)
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#define TIM_CC2P (TIM_CCEN_CC2P)
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#define TIM_CC2NP (TIM_CCEN_CC2NP)
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#define TIM_CC3P (TIM_CCEN_CC3P)
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#define TIM_CC3NP (TIM_CCEN_CC3NP)
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#define TIM_CC4P (TIM_CCEN_CC4P)
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#define TIM_CC5P (TIM_CCEN_CC5P)
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/* TIM_CCDATx*/
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#define TIM_CCDAT1_MASK (TIM_CCDAT1_CCDAT1)
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#define TIM_CCDAT2_MASK (TIM_CCDAT2_CCDAT2)
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#define TIM_CCDAT3_MASK (TIM_CCDAT3_CCDAT3)
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#define TIM_CCDAT4_MASK (TIM_CCDAT4_CCDAT4)
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/* ---------------------- TIM registers bit mask ------------------------ */
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#define SMCTRL_ETRP_MASK ((uint16_t)0x8000)
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#define SMCTRL_ETRCEN_MASK ((uint16_t)0x4000)
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#define SMCTRL_ETRPSC_MASK ((uint16_t)0x3000)
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#define SMCTRL_ETRFIL_MASK ((uint16_t)0x0f00)
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#define CAPCMPMOD_OFFSET ((uint16_t)0x0018)
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#define CAPCMPEN_CCE_SET ((uint16_t)0x0001)
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#define CAPCMPEN_CCNE_SET ((uint16_t)0x0004)
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void TIM_Reset(TIM_Module* TIMx);
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/** TIM_Base functions **/
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void TIM_Base_Count_Mode_Set(TIM_Module* TIMx, uint32_t cnt_mode);
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/* function in N32G003 */
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void TIM_Base_Auto_Reload_Set(TIM_Module* TIMx, uint16_t auto_reload);
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void TIM_Base_Prescaler_Set(TIM_Module* TIMx, uint16_t prescaler);
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void TIM_Base_Reload_Mode_Set(TIM_Module* TIMx, uint16_t reload_mode);
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void TIM_Base_Count_Set(TIM_Module* TIMx, uint16_t count);
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uint16_t TIM_Base_Count_Get(TIM_Module* TIMx);
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uint16_t TIM_Auto_Reload_Get(TIM_Module* TIMx);
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uint16_t TIM_Base_Prescaler_Get(TIM_Module* TIMx);
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void TIM_Base_Repeat_Count_Set(TIM_Module* TIMx, uint8_t repeat_cnt);
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void TIM_Base_Channel1(TIM_Module* TIMx, bool channel_selection);
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void TIM_Base_OCrefClear(TIM_Module* TIMx, bool OCrefClear_selection);
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void TIM_Base_Initialize(TIM_Module* TIMx, TIM_TimeBaseInitType* TIM_TimeBaseInitStruct);
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void TIM_Base_Struct_Initialize(TIM_TimeBaseInitType* TIM_TimeBaseInitStruct);
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void TIM_On(TIM_Module* TIMx);
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void TIM_Off(TIM_Module* TIMx);
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/** Preload functions **/
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void TIM_Output_Channel1_Preload_Set(TIM_Module* TIMx, uint16_t TIM_output_channel_preload);
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void TIM_Output_Channel2_Preload_Set(TIM_Module* TIMx, uint16_t TIM_output_channel_preload);
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void TIM_Output_Channel3_Preload_Set(TIM_Module* TIMx, uint16_t TIM_output_channel_preload);
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void TIM_Output_Channel4_Preload_Set(TIM_Module* TIMx, uint16_t TIM_output_channel_preload);
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void TIM_Output_Channel5_Preload_Set(TIM_Module* TIMx, uint16_t TIM_output_channel_preload);
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void TIM_Auto_Reload_Preload_Enable(TIM_Module* TIMx);
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void TIM_Auto_Reload_Preload_Disable(TIM_Module* TIMx);
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void TIM_Update_Event_Enable(TIM_Module* TIMx);
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void TIM_Update_Event_Disable(TIM_Module* TIMx);
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void TIM_Update_Request_Source_Set(TIM_Module* TIMx, uint16_t TIM_update_source);
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void TIM_Event_Generate(TIM_Module* TIMx, uint16_t TIM_event_source);
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void TIM_Commutation_Event_Enable(TIM_Module* TIMx);
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void TIM_Commutation_Event_Disable(TIM_Module* TIMx);
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void TIM_Capture_Compare_Control_Preload_Enable(TIM_Module* TIMx);
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void TIM_Capture_Compare_Control_Preload_Disable(TIM_Module* TIMx);
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/** Channel functions **/
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void TIM_Compare1_Set(TIM_Module* TIMx, uint16_t compare1);
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void TIM_Compare2_Set(TIM_Module* TIMx, uint16_t compare2);
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void TIM_Compare3_Set(TIM_Module* TIMx, uint16_t compare3);
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void TIM_Compare4_Set(TIM_Module* TIMx, uint16_t compare4);
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void TIM_Compare5_Set(TIM_Module* TIMx, uint16_t compare5);
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uint16_t TIM_Compare_Capture1_Get(TIM_Module* TIMx);
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uint16_t TIM_Compare_Capture2_Get(TIM_Module* TIMx);
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uint16_t TIM_Compare_Capture3_Get(TIM_Module* TIMx);
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uint16_t TIM_Compare_Capture4_Get(TIM_Module* TIMx);
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uint16_t TIM_Compare_Capture5_Get(TIM_Module* TIMx);
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FlagStatus TIM_CCEN_Status_Get(TIM_Module* TIMx, uint32_t TIM_CCEN);
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/** Chanel input&Cascade functions **/
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void TIM_Trigger_Source_Select(TIM_Module* TIMx, uint16_t TIM_trigger_source);
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void Input_Channel1_Config(TIM_Module* TIMx, uint16_t input_channel_polarity,
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uint16_t input_channel_selection, uint16_t input_channel_filter);
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void Input_Channel2_Config(TIM_Module* TIMx, uint16_t input_channel_polarity,
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uint16_t input_channel_selection, uint16_t input_channel_filter);
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void Input_Channel3_Config(TIM_Module* TIMx, uint16_t input_channel_polarity,
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uint16_t input_channel_selection, uint16_t input_channel_filter);
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void Input_Channel4_Config(TIM_Module* TIMx, uint16_t input_channel_polarity,
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uint16_t input_channel_selection, uint16_t input_channel_filter);
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void TIM_External_Trigger_Polarity_Set(TIM_Module* TIMx,
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uint16_t external_trigger_polarity);
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void TIM_External_Trigger_Filter_Set(TIM_Module* TIMx,
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uint16_t external_trigger_filter);
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void TIM_External_Trigger_Prescaler_Set(TIM_Module* TIMx,
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uint16_t external_trigger_prescaler);
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void TIM_Clock_Division_Set(TIM_Module* TIMx, uint16_t clock_division);
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void TIM_Internal_Clock_Set(TIM_Module* TIMx);
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void TIM_Input_Capture1_Prescaler_Set(TIM_Module* TIMx, uint16_t TIM_input_capture_prescaler);
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void TIM_Input_Capture2_Prescaler_Set(TIM_Module* TIMx, uint16_t TIM_input_capture_prescaler);
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void TIM_Input_Capture3_Prescaler_Set(TIM_Module* TIMx, uint16_t TIM_input_capture_prescaler);
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void TIM_Input_Capture4_Prescaler_Set(TIM_Module* TIMx, uint16_t TIM_input_capture_prescaler);
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void TIM_Internal_Trig_To_Ext_Set(TIM_Module* TIMx, uint16_t input_trigger_source);
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void TIM_Trigger_As_External_Clock(TIM_Module* TIMx, uint16_t external_clock_source, uint16_t input_channel_polarity, uint16_t input_channel_filter);
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void TIM_External_Clock_Mode1_Set(TIM_Module* TIMx, uint16_t external_trigger_prescaler, uint16_t external_trigger_polarity, uint16_t external_trigger_filter);
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void TIM_External_Clock_Mode2_Set(TIM_Module* TIMx, uint16_t external_trigger_prescaler, uint16_t external_trigger_polarity, uint16_t external_trigger_filter);
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void TIM_Slave_Mode_Select(TIM_Module* TIMx, uint16_t TIM_slave_mode);
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void TIM_Master_Slave_Mode_Set(TIM_Module* TIMx, uint16_t TIM_master_slave_mode);
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void TIM_Output_Trigger_Select(TIM_Module* TIMx, uint16_t TIM_trigger_output_source);
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void TIM_One_Pulse_Mode_Select(TIM_Module* TIMx, uint16_t TIM_one_pulse_mode);
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void TIM_Input_Channel_Initialize(TIM_Module* TIMx, TIM_ICInitType* TIM_ICInitStruct);
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void TIM_PWM_Input_Channel_Config(TIM_Module* TIMx, TIM_ICInitType* TIM_ICInitStruct);
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void TIM_Input_Struct_Initialize(TIM_ICInitType* TIM_ICInitStruct);
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/** Channel output functions **/
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void TIM_Output_Channel_Polarity_Set(TIM_Module* TIMx, uint32_t output_channel_polarity, uint16_t channel);
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void TIM_Output_Channel_N_Polarity_Set(TIM_Module* TIMx, uint32_t output_channel_N_polarity, uint16_t channel);
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void TIM_Capture_Compare_Ch_Enable(TIM_Module* TIMx, uint16_t channel);
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void TIM_Capture_Compare_Ch_Disable(TIM_Module* TIMx, uint16_t channel);
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void TIM_Capture_Compare_Ch_N_Enable(TIM_Module* TIMx, uint16_t channel);
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void TIM_Capture_Compare_Ch_N_Disable(TIM_Module* TIMx, uint16_t channel);
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void TIM_Output_Channel_Mode_Set(TIM_Module* TIMx, uint32_t output_channel_mode, uint16_t channel);
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void TIM_Forced_Output_Channel1_Set(TIM_Module* TIMx, uint16_t TIM_ForcedAction);
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void TIM_Forced_Output_Channel2_Set(TIM_Module* TIMx, uint16_t TIM_ForcedAction);
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void TIM_Forced_Output_Channel3_Set(TIM_Module* TIMx, uint16_t TIM_ForcedAction);
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void TIM_Forced_Output_Channel4_Set(TIM_Module* TIMx, uint16_t TIM_ForcedAction);
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void TIM_Forced_Output_Channel5_Set(TIM_Module* TIMx, uint16_t TIM_ForcedAction);
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void TIM_Output_Channel1_Fast_Set(TIM_Module* TIMx, uint16_t TIM_output_channel_fast);
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void TIM_Output_Channel2_Fast_Set(TIM_Module* TIMx, uint16_t TIM_output_channel_fast);
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void TIM_Output_Channel3_Fast_Set(TIM_Module* TIMx, uint16_t TIM_output_channel_fast);
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void TIM_Output_Channel4_Fast_Set(TIM_Module* TIMx, uint16_t TIM_output_channel_fast);
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void TIM_Output_Channel5_Fast_Set(TIM_Module* TIMx, uint16_t TIM_output_channel_fast);
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void TIM_Output_Channel1_Reference_Clear(TIM_Module* TIMx, uint16_t TIM_output_chanenl_clear);
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void TIM_Output_Channel2_Reference_Clear(TIM_Module* TIMx, uint16_t TIM_output_chanenl_clear);
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void TIM_Output_Channel3_Reference_Clear(TIM_Module* TIMx, uint16_t TIM_output_chanenl_clear);
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void TIM_Output_Channel4_Reference_Clear(TIM_Module* TIMx, uint16_t TIM_output_chanenl_clear);
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void TIM_Output_Channel5_Reference_Clear(TIM_Module* TIMx, uint16_t TIM_output_chanenl_clear);
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void TIM_PWM_Output_Enable(TIM_Module* TIMx);
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void TIM_PWM_Output_Disable(TIM_Module* TIMx);
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void TIM_Output_Channel1_Initialize(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct);
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|
void TIM_Output_Channel2_Initialize(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct);
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void TIM_Output_Channel3_Initialize(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct);
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void TIM_Output_Channel4_Initialize(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct);
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|
void TIM_Output_Channel5_Initialize(TIM_Module* TIMx, OCInitType* TIM_OCInitStruct);
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void TIM_Output_Channel_Struct_Initialize(OCInitType* TIM_OCInitStruct);
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/** Brake functions **/
|
|
void TIM_Lock_Up_Break_Enable(TIM_Module* TIMx);
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|
void TIM_Lock_Up_Break_Disable(TIM_Module* TIMx);
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|
void TIM_Pvd_Break_Enable(TIM_Module* TIMx);
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|
void TIM_Pvd_Break_Disable(TIM_Module* TIMx);
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|
void TIM_IOM_Comp_Break(TIM_Module* TIMx, bool IOM_Comp_Selection);
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|
void TIM_Break_And_Dead_Time_Set(TIM_Module* TIMx, TIM_BDTRInitType* TIM_BDTRInitStruct);
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void TIM_Break_And_Dead_Time_Struct_Initialize(TIM_BDTRInitType* TIM_BDTRInitStruct);
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/** Interrupt functions **/
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void TIM_Interrupt_Enable(TIM_Module* TIMx, uint16_t TIM_IT);
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void TIM_Interrupt_Disable(TIM_Module* TIMx, uint16_t TIM_IT);
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FlagStatus TIM_Flag_Status_Get(TIM_Module* TIMx, uint32_t TIM_FLAG);
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ITStatus TIM_Interrupt_Status_Get(TIM_Module* TIMx, uint32_t TIM_IT);
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void TIM_Flag_Clear(TIM_Module* TIMx, uint32_t TIM_FLAG);
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void TIM_Interrupt_Status_Clear(TIM_Module* TIMx, uint32_t TIM_IT);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _N32G003_TIM_H__ */
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