329 lines
15 KiB
C
329 lines
15 KiB
C
/**
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* Copyright (c) 2022, Nations Technologies Inc.
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*
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* All rights reserved.
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*
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* This software is the exclusive property of Nations Technologies Inc. (Hereinafter
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* referred to as NATIONS). This software, and the product of NATIONS described herein
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* (Hereinafter referred to as the Product) are owned by NATIONS under the laws and treaties
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* of the People's Republic of China and other applicable jurisdictions worldwide.
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*
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* NATIONS does not grant any license under its patents, copyrights, trademarks, or other
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* intellectual property rights. Names and brands of third party may be mentioned or referred
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* thereto (if any) for identification purposes only.
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*
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* NATIONS reserves the right to make changes, corrections, enhancements, modifications, and
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* improvements to this software at any time without notice. Please contact NATIONS and obtain
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* the latest version of this software before placing orders.
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* Although NATIONS has attempted to provide accurate and reliable information, NATIONS assumes
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* no responsibility for the accuracy and reliability of this software.
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*
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* It is the responsibility of the user of this software to properly design, program, and test
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* the functionality and safety of any application made of this information and any resulting product.
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* In no event shall NATIONS be liable for any direct, indirect, incidental, special,exemplary, or
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* consequential damages arising in any way out of the use of this software or the Product.
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*
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* NATIONS Products are neither intended nor warranted for usage in systems or equipment, any
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* malfunction or failure of which may cause loss of human life, bodily injury or severe property
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* damage. Such applications are deemed, "Insecure Usage".
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*
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* All Insecure Usage shall be made at user's risk. User shall indemnify NATIONS and hold NATIONS
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* harmless from and against all claims, costs, damages, and other liabilities, arising from or related
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* to any customer's Insecure Usage.
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* Any express or implied warranty with regard to this software or the Product, including,but not
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* limited to, the warranties of merchantability, fitness for a particular purpose and non-infringement
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* are disclaimed to the fullest extent permitted by law.
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* Unless otherwise explicitly permitted by NATIONS, anyone may not duplicate, modify, transcribe
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* or otherwise distribute this software for any purposes, in whole or in part.
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*
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* NATIONS products and technologies shall not be used for or incorporated into any products or systems
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* whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations.
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* User shall comply with any applicable export control laws and regulations promulgated and administered by
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* the governments of any countries asserting jurisdiction over the parties or transactions.
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**/
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/**
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*\*\file n32g003_pwr.h
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*\*\author Nations
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*\*\version v1.0.0
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*\*\copyright Copyright (c) 2022, Nations Technologies Inc. All rights reserved.
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*/
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#ifndef __N32G003_PWR_H
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#define __N32G003_PWR_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "n32g003.h"
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/*** PWR Structure Definition Start ***/
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/** PWR wakeup PINx enmu definition **/
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typedef enum
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{
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WAKEUP_PIN1 = 0x0100,
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WAKEUP_PIN2 = 0x0200,
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} WAKEUP_PINX;
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/*** PWR Structure Definition End ***/
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/*** PWR Macro Definition Start ***/
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/** PWR CTRL register bit mask definition **/
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#define PWR_CTRL_PLS_MASK (~((uint32_t)PWR_CTRL_PLS))
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#define PWR_CTRL_PDSTP_MASK (~((uint32_t)PWR_CTRL_PDSTP))
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#define PWR_CTRL_PDRS_MASK (~((uint32_t)PWR_CTRL_PDRS))
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/** PWR CTRL2 register bit mask definition **/
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#define PWR_CTRL2_LVRLS_MASK (~((uint32_t)PWR_CTRL2_LVRLS))
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/** PWR CTRLSTS register bit mask definition **/
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#define PWR_CTRLSTS_WKUPPOL_MASK (~((uint32_t)PWR_CTRLSTS_WKUPPOL))
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/** PWR CTRL5 register bit mask definition **/
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#define PWR_CTRL5_STPMRSEL_MASK (~((uint32_t)PWR_CTRL5_STPMRSEL))
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/** PWR PVD enable definition **/
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#define PWR_PVD_ENABLE ((uint32_t)PWR_CTRL_PVDEN)
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/** PWR PVD interrupt enable definition **/
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#define PWR_PVD_INT_ENABLE ((uint32_t)PWR_CTRL_PVDITEN)
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/** PWR PVD Filter enable definition **/
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#define PWR_PVD_FIL_ENABLE ((uint32_t)PWR_CTRL_PVDFILEN)
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/** PWR LVR enable definition **/
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#define PWR_LVR_ENABLE ((uint32_t)PWR_CTRL2_LVREN)
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/** PWR LVR reset enable definition **/
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#define PWR_LVR_RST_ENABLE ((uint32_t)PWR_CTRL2_LVRRSTEN)
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/** PWR LVR Filter enable definition **/
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#define PWR_LVR_FIL_ENABLE ((uint32_t)PWR_CTRL2_LVRFILEN)
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/** PWR wakup PIN polarity definition **/
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#define PWR_PIN_RISING ((uint32_t)0x00000001)
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#define PWR_PIN_FALLING ((uint32_t)0x00000000)
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/** PWR clear WKUPF definition **/
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#define PWR_CLEAR_WKUPF ((uint32_t)PWR_CTRL_CLRWKUPF)
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/** PWR PVD output Flag definition **/
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#define PWR_PVD_OUTPUT_FLAG ((uint32_t)PWR_CTRLSTS_PVDO)
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/** PWR PD Flag definition **/
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#define PWR_DBGPD_FLAG ((uint32_t)PWR_CTRLSTS_DBGPDF)
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/** PWR PA2/PA1wakeup Flag definition **/
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#define PWR_WKUP_FLAG ((uint32_t)PWR_CTRLSTS_WKUPF)
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/** PWR LVR output Flag definition **/
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#define PWR_LVR_OUTPUT_FLAG ((uint32_t)PWR_CTRL2_LVRO)
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/** PWR PD mode definition **/
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#define PWR_PD_MODE ((uint32_t)PWR_CTRL_PDSTP)
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/** PWR control HSI definition **/
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#define PWR_CONTROL_HSI ((uint32_t)PWR_CTRL3_HSIPWR)
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/** PWR control PDR select signal definition **/
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#define PWR_CONTROL_PDR_SEL ((uint32_t)PWR_CTRL3_PDRSEL)
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/** PWR HSI 40M trim definition **/
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#define PWR_HSI_TRIM_40M ((uint32_t)PWR_CTRL3_HSISEL)
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/** PWR enable VDDD output voltage select definition **/
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#define PWR_VDDD_OUTPUT_SEL_EN ((uint32_t)PWR_CTRL6_STPMREN)
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/** PWR PVD threshold level definition **/
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#define PWR_PVD_LEVEL_1V8 ((uint32_t)(PWR_CTRL_PLS_0 \
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& PWR_CTRL_PLS_1 \
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& PWR_CTRL_PLS_2 \
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& PWR_CTRL_PLS_3)) /* 1.8v PWR_CTRL bit[8:5]:0000 */
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#define PWR_PVD_LEVEL_2V0 ((uint32_t)PWR_CTRL_PLS_0) /* 2.0v PWR_CTRL bit[8:5]:0001 */
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#define PWR_PVD_LEVEL_2V2 ((uint32_t)PWR_CTRL_PLS_1) /* 2.2v PWR_CTRL bit[8:5]:0010 */
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#define PWR_PVD_LEVEL_2V4 ((uint32_t)(PWR_CTRL_PLS_0 \
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| PWR_CTRL_PLS_1)) /* 2.4v PWR_CTRL bit[8:5]:0011 */
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#define PWR_PVD_LEVEL_2V6 ((uint32_t)PWR_CTRL_PLS_2) /* 2.6v PWR_CTRL bit[8:5]:0100 */
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#define PWR_PVD_LEVEL_2V8 ((uint32_t)(PWR_CTRL_PLS_0 \
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| PWR_CTRL_PLS_2)) /* 2.8v PWR_CTRL bit[8:5]:0101 */
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#define PWR_PVD_LEVEL_3V0 ((uint32_t)(PWR_CTRL_PLS_1 \
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| PWR_CTRL_PLS_2)) /* 3.0v PWR_CTRL bit[8:5]:0110 */
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#define PWR_PVD_LEVEL_3V2 ((uint32_t)(PWR_CTRL_PLS_0 \
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| PWR_CTRL_PLS_1 \
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| PWR_CTRL_PLS_2)) /* 3.2v PWR_CTRL bit[8:5]:0111 */
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#define PWR_PVD_LEVEL_3V4 ((uint32_t)PWR_CTRL_PLS_3) /* 3.4v PWR_CTRL bit[8:5]:1000 */
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#define PWR_PVD_LEVEL_3V6 ((uint32_t)(PWR_CTRL_PLS_0 \
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| PWR_CTRL_PLS_3)) /* 3.6v PWR_CTRL bit[8:5]:1001 */
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#define PWR_PVD_LEVEL_3V8 ((uint32_t)(PWR_CTRL_PLS_1 \
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| PWR_CTRL_PLS_3)) /* 3.8v PWR_CTRL bit[8:5]:1010 */
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#define PWR_PVD_LEVEL_4V0 ((uint32_t)(PWR_CTRL_PLS_0 \
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| PWR_CTRL_PLS_1 \
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| PWR_CTRL_PLS_3)) /* 4.0v PWR_CTRL bit[8:5]:1011 */
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#define PWR_PVD_LEVEL_4V2 ((uint32_t)(PWR_CTRL_PLS_2 \
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| PWR_CTRL_PLS_3)) /* 4.2v PWR_CTRL bit[8:5]:1100 */
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#define PWR_PVD_LEVEL_4V4 ((uint32_t)(PWR_CTRL_PLS_0 \
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| PWR_CTRL_PLS_2 \
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| PWR_CTRL_PLS_3)) /* 4.4v PWR_CTRL bit[8:5]:1101 */
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#define PWR_PVD_LEVEL_4V6 ((uint32_t)(PWR_CTRL_PLS_1 \
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| PWR_CTRL_PLS_2 \
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| PWR_CTRL_PLS_3)) /* 4.6v PWR_CTRL bit[8:5]:1110 */
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#define PWR_PVD_LEVEL_4V8 ((uint32_t)(PWR_CTRL_PLS_0 \
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| PWR_CTRL_PLS_1 \
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| PWR_CTRL_PLS_2 \
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| PWR_CTRL_PLS_3)) /* 4.8v PWR_CTRL bit[8:5]:1111 */
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/** PWR LVR threshold level definition **/
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#define PWR_LVR_LEVEL_1V8 ((uint32_t)(PWR_CTRL2_LVRLS_0 \
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& PWR_CTRL2_LVRLS_1 \
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& PWR_CTRL2_LVRLS_2 \
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& PWR_CTRL2_LVRLS_3)) /* 1.8v PWR_CTRL2 bit[14:11]:0000 */
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#define PWR_LVR_LEVEL_2V0 ((uint32_t)PWR_CTRL2_LVRLS_0) /* 2.0v PWR_CTRL2 bit[14:11]:0001 */
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#define PWR_LVR_LEVEL_2V2 ((uint32_t)PWR_CTRL2_LVRLS_1) /* 2.2v PWR_CTRL2 bit[14:11]:0010 */
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#define PWR_LVR_LEVEL_2V4 ((uint32_t)(PWR_CTRL2_LVRLS_0 \
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| PWR_CTRL2_LVRLS_1)) /* 2.4v PWR_CTRL2 bit[14:11]:0011 */
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#define PWR_LVR_LEVEL_2V6 ((uint32_t)PWR_CTRL2_LVRLS_2) /* 2.6v PWR_CTRL2 bit[14:11]:0100 */
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#define PWR_LVR_LEVEL_2V8 ((uint32_t)(PWR_CTRL2_LVRLS_0 \
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| PWR_CTRL2_LVRLS_2)) /* 2.8v PWR_CTRL2 bit[14:11]:0101 */
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#define PWR_LVR_LEVEL_3V0 ((uint32_t)(PWR_CTRL2_LVRLS_1 \
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| PWR_CTRL2_LVRLS_2)) /* 3.0v PWR_CTRL2 bit[14:11]:0110 */
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#define PWR_LVR_LEVEL_3V2 ((uint32_t)(PWR_CTRL2_LVRLS_0 \
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| PWR_CTRL2_LVRLS_1 \
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| PWR_CTRL2_LVRLS_2)) /* 3.2v PWR_CTRL2 bit[14:11]:0111 */
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#define PWR_LVR_LEVEL_3V4 ((uint32_t)PWR_CTRL2_LVRLS_3) /* 3.4v PWR_CTRL2 bit[14:11]:1000 */
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#define PWR_LVR_LEVEL_3V6 ((uint32_t)(PWR_CTRL2_LVRLS_0 \
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| PWR_CTRL2_LVRLS_3)) /* 3.6v PWR_CTRL2 bit[14:11]:1001 */
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#define PWR_LVR_LEVEL_3V8 ((uint32_t)(PWR_CTRL2_LVRLS_1 \
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| PWR_CTRL2_LVRLS_3)) /* 3.8v PWR_CTRL2 bit[14:11]:1010 */
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#define PWR_LVR_LEVEL_4V0 ((uint32_t)(PWR_CTRL2_LVRLS_0 \
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| PWR_CTRL2_LVRLS_1 \
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| PWR_CTRL2_LVRLS_3)) /* 4.0v PWR_CTRL2 bit[14:11]:1011 */
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#define PWR_LVR_LEVEL_4V2 ((uint32_t)(PWR_CTRL2_LVRLS_2 \
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| PWR_CTRL2_LVRLS_3)) /* 4.2v PWR_CTRL2 bit[14:11]:1100 */
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#define PWR_LVR_LEVEL_4V4 ((uint32_t)(PWR_CTRL2_LVRLS_0 \
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| PWR_CTRL2_LVRLS_2 \
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| PWR_CTRL2_LVRLS_3)) /* 4.4v PWR_CTRL2 bit[14:11]:1101 */
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#define PWR_LVR_LEVEL_4V6 ((uint32_t)(PWR_CTRL2_LVRLS_1 \
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| PWR_CTRL2_LVRLS_2 \
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| PWR_CTRL2_LVRLS_3)) /* 4.6v PWR_CTRL2 bit[14:11]:1110 */
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#define PWR_LVR_LEVEL_4V8 ((uint32_t)(PWR_CTRL2_LVRLS_0 \
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| PWR_CTRL2_LVRLS_1 \
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| PWR_CTRL2_LVRLS_2 \
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| PWR_CTRL2_LVRLS_3)) /* 4.8v PWR_CTRL2 bit[14:11]:1111 */
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/** PWR PDR trigger level definition **/
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#define PWR_PDR_LEVEL_0V8 ((uint32_t)PWR_CTRL_PDRS_0) /* 0.8v PWR_CTRL bit[10:9]:01 */
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#define PWR_PDR_LEVEL_1V0 ((uint32_t)PWR_CTRL_PDRS_1) /* 1.0v PWR_CTRL bit[10:9]:10 */
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#define PWR_PDR_LEVEL_1V2 ((uint32_t)(PWR_CTRL_PDRS_0 \
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| PWR_CTRL_PDRS_1)) /* 0.2v PWR_CTRL bit[10:9]:11 */
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/** PWR VDDD output voltage definition **/
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#define PWR_VDDD_OUTPUT_1V5 ((uint32_t)PWR_CTRL5_STPMRSEL_0) /* 1.5v PWR_CTRL5 bit[3:2]:01 */
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#define PWR_VDDD_OUTPUT_1V0 ((uint32_t)PWR_CTRL5_STPMRSEL_1) /* 1.0v PWR_CTRL5 bit[3:2]:10 */
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#define PWR_VDDD_OUTPUT_1V2 ((uint32_t)(PWR_CTRL5_STPMRSEL_0 \
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| PWR_CTRL5_STPMRSEL_1)) /* 0.2v PWR_CTRL5 bit[3:2]:11 */
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/** PWR STOP mode entry definition **/
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#define PWR_STOP_ENTRY_WFI ((uint8_t)0x01) /* enter STOP mode with WFI instruction */
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#define PWR_STOP_ENTRY_WFE ((uint8_t)0x02) /* enter STOP mode with WFE instruction */
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/** PWR PD mode entry definition **/
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#define PWR_PD_ENTRY_WFI ((uint8_t)0x01) /* enter PD mode with WFI instruction */
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#define PWR_PD_ENTRY_WFE ((uint8_t)0x02) /* enter PD mode with WFE instruction */
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/** PWR DBG_CTRL definition **/
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#define PWR_DBG_SLEEP ((uint32_t)DBG_CTRL_SLEEP)
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#define PWR_DBG_STOP ((uint32_t)DBG_CTRL_STOP)
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#define PWR_DBG_PD ((uint32_t)DBG_CTRL_PD)
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#define PWR_DBG_IWDG ((uint32_t)DBG_CTRL_IWDGSTP)
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#define PWR_DBG_TIM1 ((uint32_t)DBG_CTRL_TIM1STP)
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#define PWR_DBG_TIM3 ((uint32_t)DBG_CTRL_TIM3STP)
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#define PWR_DBG_TIM6 ((uint32_t)DBG_CTRL_TIM6STP)
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/** PWR registers write protection keys definition **/
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#define PWR_CTRL2_KEYS ((uint32_t)0xA5000000)
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#define PWR_CTRL4_KEYS ((uint32_t)0x01753603)
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/** PWR bit shift number definition **/
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#define PWR_BIT_SHIFT_2 ((uint32_t)REG_BIT2_OFFSET)
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#define PWR_BIT_SHIFT_10 ((uint32_t)REG_BIT10_OFFSET)
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/*** PWR Macro Definition End ***/
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/*** PWR Driving Functions Declaration ***/
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void PWR_Reset(void);
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void PWR_PVD_Enable(void);
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void PWR_PVD_Disable(void);
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void PWR_PVD_Interrupt_Enable(void);
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void PWR_PVD_Interrupt_Disable(void);
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void PWR_PVD_Filter_Enable(void);
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void PWR_PVD_Filter_Disable(void);
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void PWR_PVD_Level_Config(uint32_t level);
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void PWR_LVR_Enable(void);
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void PWR_LVR_Disable(void);
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void PWR_LVR_Reset_Enable(void);
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void PWR_LVR_Reset_Disable(void);
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void PWR_LVR_Filter_Enable(void);
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void PWR_LVR_Filter_Disable(void);
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void PWR_LVR_Level_Config(uint32_t level);
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void PWR_Wakeup_Pin_Enable(WAKEUP_PINX pin, uint32_t polarity);
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void PWR_Wakeup_Pin_Disable(WAKEUP_PINX pin);
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void PWR_STOP_Mode_Enter(uint8_t enter_mode);
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void PWR_PD_Mode_Enter(uint8_t enter_mode);
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void PWR_HSI_40M_Trim_Select(void);
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void PWR_PDR_Trigger_Level_Config(uint32_t level);
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void PWR_VDDD_Output_Config(uint32_t voltage_output);
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void PWR_CTRL2_write_Protection_Enable(void);
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void PWR_CTRL4_write_Protection_Enable(void);
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FlagStatus PWR_Flag_Status_Get(uint32_t flag);
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void PWR_Flag_Status_Clear(uint32_t flag);
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void DBG_Peripheral_ON(uint32_t DBG_Periph);
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void DBG_Peripheral_OFF(uint32_t DBG_Periph);
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#ifdef __cplusplus
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}
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#endif
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#endif /* __N32G003_PWR_H */
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